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sys/dev/ubsec/ubsec.c
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1 /* $FreeBSD: releng/5.1/sys/dev/ubsec/ubsec.c 114105 2003-04-27 04:26:22Z sam $ */ 2 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Jason L. Wright 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 * 41 */ 42 43 /* 44 * uBsec 5[56]01, 58xx hardware crypto accelerator 45 */ 46 47 #include "opt_ubsec.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/proc.h> 52 #include <sys/errno.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/mbuf.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/sysctl.h> 59 #include <sys/endian.h> 60 61 #include <vm/vm.h> 62 #include <vm/pmap.h> 63 64 #include <machine/clock.h> 65 #include <machine/bus.h> 66 #include <machine/resource.h> 67 #include <sys/bus.h> 68 #include <sys/rman.h> 69 70 #include <crypto/sha1.h> 71 #include <opencrypto/cryptodev.h> 72 #include <opencrypto/cryptosoft.h> 73 #include <sys/md5.h> 74 #include <sys/random.h> 75 76 #include <pci/pcivar.h> 77 #include <pci/pcireg.h> 78 79 /* grr, #defines for gratuitous incompatibility in queue.h */ 80 #define SIMPLEQ_HEAD STAILQ_HEAD 81 #define SIMPLEQ_ENTRY STAILQ_ENTRY 82 #define SIMPLEQ_INIT STAILQ_INIT 83 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 84 #define SIMPLEQ_EMPTY STAILQ_EMPTY 85 #define SIMPLEQ_FIRST STAILQ_FIRST 86 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 87 #define SIMPLEQ_FOREACH STAILQ_FOREACH 88 /* ditto for endian.h */ 89 #define letoh16(x) le16toh(x) 90 #define letoh32(x) le32toh(x) 91 92 #ifdef UBSEC_RNDTEST 93 #include <dev/rndtest/rndtest.h> 94 #endif 95 #include <dev/ubsec/ubsecreg.h> 96 #include <dev/ubsec/ubsecvar.h> 97 98 /* 99 * Prototypes and count for the pci_device structure 100 */ 101 static int ubsec_probe(device_t); 102 static int ubsec_attach(device_t); 103 static int ubsec_detach(device_t); 104 static int ubsec_suspend(device_t); 105 static int ubsec_resume(device_t); 106 static void ubsec_shutdown(device_t); 107 108 static device_method_t ubsec_methods[] = { 109 /* Device interface */ 110 DEVMETHOD(device_probe, ubsec_probe), 111 DEVMETHOD(device_attach, ubsec_attach), 112 DEVMETHOD(device_detach, ubsec_detach), 113 DEVMETHOD(device_suspend, ubsec_suspend), 114 DEVMETHOD(device_resume, ubsec_resume), 115 DEVMETHOD(device_shutdown, ubsec_shutdown), 116 117 /* bus interface */ 118 DEVMETHOD(bus_print_child, bus_generic_print_child), 119 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 120 121 { 0, 0 } 122 }; 123 static driver_t ubsec_driver = { 124 "ubsec", 125 ubsec_methods, 126 sizeof (struct ubsec_softc) 127 }; 128 static devclass_t ubsec_devclass; 129 130 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 131 MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 132 #ifdef UBSEC_RNDTEST 133 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 134 #endif 135 136 static void ubsec_intr(void *); 137 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 138 static int ubsec_freesession(void *, u_int64_t); 139 static int ubsec_process(void *, struct cryptop *, int); 140 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 141 static void ubsec_feed(struct ubsec_softc *); 142 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 143 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 144 static int ubsec_feed2(struct ubsec_softc *); 145 static void ubsec_rng(void *); 146 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 147 struct ubsec_dma_alloc *, int); 148 #define ubsec_dma_sync(_dma, _flags) \ 149 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 150 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 151 static int ubsec_dmamap_aligned(struct ubsec_operand *op); 152 153 static void ubsec_reset_board(struct ubsec_softc *sc); 154 static void ubsec_init_board(struct ubsec_softc *sc); 155 static void ubsec_init_pciregs(device_t dev); 156 static void ubsec_totalreset(struct ubsec_softc *sc); 157 158 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 159 160 static int ubsec_kprocess(void*, struct cryptkop *, int); 161 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 162 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 163 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 164 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 165 static int ubsec_ksigbits(struct crparam *); 166 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 167 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168 169 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 170 171 #ifdef UBSEC_DEBUG 172 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 173 static void ubsec_dump_mcr(struct ubsec_mcr *); 174 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 175 176 static int ubsec_debug = 0; 177 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 178 0, "control debugging msgs"); 179 #endif 180 181 #define READ_REG(sc,r) \ 182 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 183 184 #define WRITE_REG(sc,reg,val) \ 185 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 186 187 #define SWAP32(x) (x) = htole32(ntohl((x))) 188 #define HTOLE32(x) (x) = htole32(x) 189 190 struct ubsec_stats ubsecstats; 191 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 192 ubsec_stats, "driver statistics"); 193 194 static int 195 ubsec_probe(device_t dev) 196 { 197 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 198 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 199 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 200 return (0); 201 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 202 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 203 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 204 return (0); 205 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 206 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 207 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 213 )) 214 return (0); 215 return (ENXIO); 216 } 217 218 static const char* 219 ubsec_partname(struct ubsec_softc *sc) 220 { 221 /* XXX sprintf numbers when not decoded */ 222 switch (pci_get_vendor(sc->sc_dev)) { 223 case PCI_VENDOR_BROADCOM: 224 switch (pci_get_device(sc->sc_dev)) { 225 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 226 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 227 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 228 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 229 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 230 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 231 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 232 } 233 return "Broadcom unknown-part"; 234 case PCI_VENDOR_BLUESTEEL: 235 switch (pci_get_device(sc->sc_dev)) { 236 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 237 } 238 return "Bluesteel unknown-part"; 239 case PCI_VENDOR_SUN: 240 switch (pci_get_device(sc->sc_dev)) { 241 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 242 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 243 } 244 return "Sun unknown-part"; 245 } 246 return "Unknown-vendor unknown-part"; 247 } 248 249 static void 250 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 251 { 252 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 253 } 254 255 static int 256 ubsec_attach(device_t dev) 257 { 258 struct ubsec_softc *sc = device_get_softc(dev); 259 struct ubsec_dma *dmap; 260 u_int32_t cmd, i; 261 int rid; 262 263 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!")); 264 bzero(sc, sizeof (*sc)); 265 sc->sc_dev = dev; 266 267 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 268 269 SIMPLEQ_INIT(&sc->sc_queue); 270 SIMPLEQ_INIT(&sc->sc_qchip); 271 SIMPLEQ_INIT(&sc->sc_queue2); 272 SIMPLEQ_INIT(&sc->sc_qchip2); 273 SIMPLEQ_INIT(&sc->sc_q2free); 274 275 /* XXX handle power management */ 276 277 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 278 279 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 280 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 281 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 282 283 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 284 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 285 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 286 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 287 288 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 289 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 290 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 291 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 292 293 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 294 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 295 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 296 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 297 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 298 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 299 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 300 /* NB: the 5821/5822 defines some additional status bits */ 301 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 302 BS_STAT_MCR2_ALLEMPTY; 303 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 304 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 305 } 306 307 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 308 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 309 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 310 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 311 312 if (!(cmd & PCIM_CMD_MEMEN)) { 313 device_printf(dev, "failed to enable memory mapping\n"); 314 goto bad; 315 } 316 317 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 318 device_printf(dev, "failed to enable bus mastering\n"); 319 goto bad; 320 } 321 322 /* 323 * Setup memory-mapping of PCI registers. 324 */ 325 rid = BS_BAR; 326 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 327 0, ~0, 1, RF_ACTIVE); 328 if (sc->sc_sr == NULL) { 329 device_printf(dev, "cannot map register space\n"); 330 goto bad; 331 } 332 sc->sc_st = rman_get_bustag(sc->sc_sr); 333 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 334 335 /* 336 * Arrange interrupt line. 337 */ 338 rid = 0; 339 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 340 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 341 if (sc->sc_irq == NULL) { 342 device_printf(dev, "could not map interrupt\n"); 343 goto bad1; 344 } 345 /* 346 * NB: Network code assumes we are blocked with splimp() 347 * so make sure the IRQ is mapped appropriately. 348 */ 349 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 350 ubsec_intr, sc, &sc->sc_ih)) { 351 device_printf(dev, "could not establish interrupt\n"); 352 goto bad2; 353 } 354 355 sc->sc_cid = crypto_get_driverid(0); 356 if (sc->sc_cid < 0) { 357 device_printf(dev, "could not get crypto driver id\n"); 358 goto bad3; 359 } 360 361 /* 362 * Setup DMA descriptor area. 363 */ 364 if (bus_dma_tag_create(NULL, /* parent */ 365 1, 0, /* alignment, bounds */ 366 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 367 BUS_SPACE_MAXADDR, /* highaddr */ 368 NULL, NULL, /* filter, filterarg */ 369 0x3ffff, /* maxsize */ 370 UBS_MAX_SCATTER, /* nsegments */ 371 0xffff, /* maxsegsize */ 372 BUS_DMA_ALLOCNOW, /* flags */ 373 &sc->sc_dmat)) { 374 device_printf(dev, "cannot allocate DMA tag\n"); 375 goto bad4; 376 } 377 SIMPLEQ_INIT(&sc->sc_freequeue); 378 dmap = sc->sc_dmaa; 379 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 380 struct ubsec_q *q; 381 382 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 383 M_DEVBUF, M_NOWAIT); 384 if (q == NULL) { 385 device_printf(dev, "cannot allocate queue buffers\n"); 386 break; 387 } 388 389 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 390 &dmap->d_alloc, 0)) { 391 device_printf(dev, "cannot allocate dma buffers\n"); 392 free(q, M_DEVBUF); 393 break; 394 } 395 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 396 397 q->q_dma = dmap; 398 sc->sc_queuea[i] = q; 399 400 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 401 } 402 403 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 404 405 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 406 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 407 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 408 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 409 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 410 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 411 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 412 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 413 414 /* 415 * Reset Broadcom chip 416 */ 417 ubsec_reset_board(sc); 418 419 /* 420 * Init Broadcom specific PCI settings 421 */ 422 ubsec_init_pciregs(dev); 423 424 /* 425 * Init Broadcom chip 426 */ 427 ubsec_init_board(sc); 428 429 #ifndef UBSEC_NO_RNG 430 if (sc->sc_flags & UBS_FLAGS_RNG) { 431 sc->sc_statmask |= BS_STAT_MCR2_DONE; 432 #ifdef UBSEC_RNDTEST 433 sc->sc_rndtest = rndtest_attach(dev); 434 if (sc->sc_rndtest) 435 sc->sc_harvest = rndtest_harvest; 436 else 437 sc->sc_harvest = default_harvest; 438 #else 439 sc->sc_harvest = default_harvest; 440 #endif 441 442 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 443 &sc->sc_rng.rng_q.q_mcr, 0)) 444 goto skip_rng; 445 446 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 447 &sc->sc_rng.rng_q.q_ctx, 0)) { 448 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 449 goto skip_rng; 450 } 451 452 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 453 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 454 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 455 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 456 goto skip_rng; 457 } 458 459 if (hz >= 100) 460 sc->sc_rnghz = hz / 100; 461 else 462 sc->sc_rnghz = 1; 463 /* NB: 1 means the callout runs w/o Giant locked */ 464 callout_init(&sc->sc_rngto, 1); 465 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 466 skip_rng: 467 ; 468 } 469 #endif /* UBSEC_NO_RNG */ 470 471 if (sc->sc_flags & UBS_FLAGS_KEY) { 472 sc->sc_statmask |= BS_STAT_MCR2_DONE; 473 474 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 475 ubsec_kprocess, sc); 476 #if 0 477 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 478 ubsec_kprocess, sc); 479 #endif 480 } 481 return (0); 482 bad4: 483 crypto_unregister_all(sc->sc_cid); 484 bad3: 485 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 486 bad2: 487 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 488 bad1: 489 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 490 bad: 491 mtx_destroy(&sc->sc_mtx); 492 return (ENXIO); 493 } 494 495 /* 496 * Detach a device that successfully probed. 497 */ 498 static int 499 ubsec_detach(device_t dev) 500 { 501 struct ubsec_softc *sc = device_get_softc(dev); 502 503 KASSERT(sc != NULL, ("ubsec_detach: null software carrier")); 504 505 /* XXX wait/abort active ops */ 506 507 UBSEC_LOCK(sc); 508 509 callout_stop(&sc->sc_rngto); 510 511 crypto_unregister_all(sc->sc_cid); 512 513 #ifdef UBSEC_RNDTEST 514 if (sc->sc_rndtest) 515 rndtest_detach(sc->sc_rndtest); 516 #endif 517 518 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 519 struct ubsec_q *q; 520 521 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 522 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 523 ubsec_dma_free(sc, &q->q_dma->d_alloc); 524 free(q, M_DEVBUF); 525 } 526 #ifndef UBSEC_NO_RNG 527 if (sc->sc_flags & UBS_FLAGS_RNG) { 528 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 529 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 530 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 531 } 532 #endif /* UBSEC_NO_RNG */ 533 534 bus_generic_detach(dev); 535 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 536 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 537 538 bus_dma_tag_destroy(sc->sc_dmat); 539 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 540 541 UBSEC_UNLOCK(sc); 542 543 mtx_destroy(&sc->sc_mtx); 544 545 return (0); 546 } 547 548 /* 549 * Stop all chip i/o so that the kernel's probe routines don't 550 * get confused by errant DMAs when rebooting. 551 */ 552 static void 553 ubsec_shutdown(device_t dev) 554 { 555 #ifdef notyet 556 ubsec_stop(device_get_softc(dev)); 557 #endif 558 } 559 560 /* 561 * Device suspend routine. 562 */ 563 static int 564 ubsec_suspend(device_t dev) 565 { 566 struct ubsec_softc *sc = device_get_softc(dev); 567 568 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier")); 569 #ifdef notyet 570 /* XXX stop the device and save PCI settings */ 571 #endif 572 sc->sc_suspended = 1; 573 574 return (0); 575 } 576 577 static int 578 ubsec_resume(device_t dev) 579 { 580 struct ubsec_softc *sc = device_get_softc(dev); 581 582 KASSERT(sc != NULL, ("ubsec_resume: null software carrier")); 583 #ifdef notyet 584 /* XXX retore PCI settings and start the device */ 585 #endif 586 sc->sc_suspended = 0; 587 return (0); 588 } 589 590 /* 591 * UBSEC Interrupt routine 592 */ 593 static void 594 ubsec_intr(void *arg) 595 { 596 struct ubsec_softc *sc = arg; 597 volatile u_int32_t stat; 598 struct ubsec_q *q; 599 struct ubsec_dma *dmap; 600 int npkts = 0, i; 601 602 UBSEC_LOCK(sc); 603 604 stat = READ_REG(sc, BS_STAT); 605 stat &= sc->sc_statmask; 606 if (stat == 0) { 607 UBSEC_UNLOCK(sc); 608 return; 609 } 610 611 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 612 613 /* 614 * Check to see if we have any packets waiting for us 615 */ 616 if ((stat & BS_STAT_MCR1_DONE)) { 617 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 618 q = SIMPLEQ_FIRST(&sc->sc_qchip); 619 dmap = q->q_dma; 620 621 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 622 break; 623 624 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 625 626 npkts = q->q_nstacked_mcrs; 627 sc->sc_nqchip -= 1+npkts; 628 /* 629 * search for further sc_qchip ubsec_q's that share 630 * the same MCR, and complete them too, they must be 631 * at the top. 632 */ 633 for (i = 0; i < npkts; i++) { 634 if(q->q_stacked_mcr[i]) { 635 ubsec_callback(sc, q->q_stacked_mcr[i]); 636 } else { 637 break; 638 } 639 } 640 ubsec_callback(sc, q); 641 } 642 643 /* 644 * Don't send any more packet to chip if there has been 645 * a DMAERR. 646 */ 647 if (!(stat & BS_STAT_DMAERR)) 648 ubsec_feed(sc); 649 } 650 651 /* 652 * Check to see if we have any key setups/rng's waiting for us 653 */ 654 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 655 (stat & BS_STAT_MCR2_DONE)) { 656 struct ubsec_q2 *q2; 657 struct ubsec_mcr *mcr; 658 659 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 660 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 661 662 ubsec_dma_sync(&q2->q_mcr, 663 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 664 665 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 666 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 667 ubsec_dma_sync(&q2->q_mcr, 668 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 669 break; 670 } 671 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 672 ubsec_callback2(sc, q2); 673 /* 674 * Don't send any more packet to chip if there has been 675 * a DMAERR. 676 */ 677 if (!(stat & BS_STAT_DMAERR)) 678 ubsec_feed2(sc); 679 } 680 } 681 682 /* 683 * Check to see if we got any DMA Error 684 */ 685 if (stat & BS_STAT_DMAERR) { 686 #ifdef UBSEC_DEBUG 687 if (ubsec_debug) { 688 volatile u_int32_t a = READ_REG(sc, BS_ERR); 689 690 printf("dmaerr %s@%08x\n", 691 (a & BS_ERR_READ) ? "read" : "write", 692 a & BS_ERR_ADDR); 693 } 694 #endif /* UBSEC_DEBUG */ 695 ubsecstats.hst_dmaerr++; 696 ubsec_totalreset(sc); 697 ubsec_feed(sc); 698 } 699 700 if (sc->sc_needwakeup) { /* XXX check high watermark */ 701 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 702 #ifdef UBSEC_DEBUG 703 if (ubsec_debug) 704 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 705 sc->sc_needwakeup); 706 #endif /* UBSEC_DEBUG */ 707 sc->sc_needwakeup &= ~wakeup; 708 crypto_unblock(sc->sc_cid, wakeup); 709 } 710 711 UBSEC_UNLOCK(sc); 712 } 713 714 /* 715 * ubsec_feed() - aggregate and post requests to chip 716 */ 717 static void 718 ubsec_feed(struct ubsec_softc *sc) 719 { 720 struct ubsec_q *q, *q2; 721 int npkts, i; 722 void *v; 723 u_int32_t stat; 724 725 /* 726 * Decide how many ops to combine in a single MCR. We cannot 727 * aggregate more than UBS_MAX_AGGR because this is the number 728 * of slots defined in the data structure. Note that 729 * aggregation only happens if ops are marked batch'able. 730 * Aggregating ops reduces the number of interrupts to the host 731 * but also (potentially) increases the latency for processing 732 * completed ops as we only get an interrupt when all aggregated 733 * ops have completed. 734 */ 735 if (sc->sc_nqueue == 0) 736 return; 737 if (sc->sc_nqueue > 1) { 738 npkts = 0; 739 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 740 npkts++; 741 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 742 break; 743 } 744 } else 745 npkts = 1; 746 /* 747 * Check device status before going any further. 748 */ 749 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 750 if (stat & BS_STAT_DMAERR) { 751 ubsec_totalreset(sc); 752 ubsecstats.hst_dmaerr++; 753 } else 754 ubsecstats.hst_mcr1full++; 755 return; 756 } 757 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 758 ubsecstats.hst_maxqueue = sc->sc_nqueue; 759 if (npkts > UBS_MAX_AGGR) 760 npkts = UBS_MAX_AGGR; 761 if (npkts < 2) /* special case 1 op */ 762 goto feed1; 763 764 ubsecstats.hst_totbatch += npkts-1; 765 #ifdef UBSEC_DEBUG 766 if (ubsec_debug) 767 printf("merging %d records\n", npkts); 768 #endif /* UBSEC_DEBUG */ 769 770 q = SIMPLEQ_FIRST(&sc->sc_queue); 771 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 772 --sc->sc_nqueue; 773 774 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 775 if (q->q_dst_map != NULL) 776 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 777 778 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 779 780 for (i = 0; i < q->q_nstacked_mcrs; i++) { 781 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 782 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 783 BUS_DMASYNC_PREWRITE); 784 if (q2->q_dst_map != NULL) 785 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 786 BUS_DMASYNC_PREREAD); 787 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 788 --sc->sc_nqueue; 789 790 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 791 sizeof(struct ubsec_mcr_add)); 792 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 793 q->q_stacked_mcr[i] = q2; 794 } 795 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 796 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 797 sc->sc_nqchip += npkts; 798 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 799 ubsecstats.hst_maxqchip = sc->sc_nqchip; 800 ubsec_dma_sync(&q->q_dma->d_alloc, 801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 802 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 803 offsetof(struct ubsec_dmachunk, d_mcr)); 804 return; 805 feed1: 806 q = SIMPLEQ_FIRST(&sc->sc_queue); 807 808 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 809 if (q->q_dst_map != NULL) 810 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 811 ubsec_dma_sync(&q->q_dma->d_alloc, 812 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 813 814 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 815 offsetof(struct ubsec_dmachunk, d_mcr)); 816 #ifdef UBSEC_DEBUG 817 if (ubsec_debug) 818 printf("feed1: q->chip %p %08x stat %08x\n", 819 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 820 stat); 821 #endif /* UBSEC_DEBUG */ 822 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 823 --sc->sc_nqueue; 824 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 825 sc->sc_nqchip++; 826 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 827 ubsecstats.hst_maxqchip = sc->sc_nqchip; 828 return; 829 } 830 831 /* 832 * Allocate a new 'session' and return an encoded session id. 'sidp' 833 * contains our registration id, and should contain an encoded session 834 * id on successful allocation. 835 */ 836 static int 837 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 838 { 839 struct cryptoini *c, *encini = NULL, *macini = NULL; 840 struct ubsec_softc *sc = arg; 841 struct ubsec_session *ses = NULL; 842 MD5_CTX md5ctx; 843 SHA1_CTX sha1ctx; 844 int i, sesn; 845 846 KASSERT(sc != NULL, ("ubsec_newsession: null softc")); 847 if (sidp == NULL || cri == NULL || sc == NULL) 848 return (EINVAL); 849 850 for (c = cri; c != NULL; c = c->cri_next) { 851 if (c->cri_alg == CRYPTO_MD5_HMAC || 852 c->cri_alg == CRYPTO_SHA1_HMAC) { 853 if (macini) 854 return (EINVAL); 855 macini = c; 856 } else if (c->cri_alg == CRYPTO_DES_CBC || 857 c->cri_alg == CRYPTO_3DES_CBC) { 858 if (encini) 859 return (EINVAL); 860 encini = c; 861 } else 862 return (EINVAL); 863 } 864 if (encini == NULL && macini == NULL) 865 return (EINVAL); 866 867 if (sc->sc_sessions == NULL) { 868 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 869 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 870 if (ses == NULL) 871 return (ENOMEM); 872 sesn = 0; 873 sc->sc_nsessions = 1; 874 } else { 875 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 876 if (sc->sc_sessions[sesn].ses_used == 0) { 877 ses = &sc->sc_sessions[sesn]; 878 break; 879 } 880 } 881 882 if (ses == NULL) { 883 sesn = sc->sc_nsessions; 884 ses = (struct ubsec_session *)malloc((sesn + 1) * 885 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 886 if (ses == NULL) 887 return (ENOMEM); 888 bcopy(sc->sc_sessions, ses, sesn * 889 sizeof(struct ubsec_session)); 890 bzero(sc->sc_sessions, sesn * 891 sizeof(struct ubsec_session)); 892 free(sc->sc_sessions, M_DEVBUF); 893 sc->sc_sessions = ses; 894 ses = &sc->sc_sessions[sesn]; 895 sc->sc_nsessions++; 896 } 897 } 898 899 bzero(ses, sizeof(struct ubsec_session)); 900 ses->ses_used = 1; 901 if (encini) { 902 /* get an IV, network byte order */ 903 /* XXX may read fewer than requested */ 904 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 905 906 /* Go ahead and compute key in ubsec's byte order */ 907 if (encini->cri_alg == CRYPTO_DES_CBC) { 908 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 909 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 910 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 911 } else 912 bcopy(encini->cri_key, ses->ses_deskey, 24); 913 914 SWAP32(ses->ses_deskey[0]); 915 SWAP32(ses->ses_deskey[1]); 916 SWAP32(ses->ses_deskey[2]); 917 SWAP32(ses->ses_deskey[3]); 918 SWAP32(ses->ses_deskey[4]); 919 SWAP32(ses->ses_deskey[5]); 920 } 921 922 if (macini) { 923 for (i = 0; i < macini->cri_klen / 8; i++) 924 macini->cri_key[i] ^= HMAC_IPAD_VAL; 925 926 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 927 MD5Init(&md5ctx); 928 MD5Update(&md5ctx, macini->cri_key, 929 macini->cri_klen / 8); 930 MD5Update(&md5ctx, hmac_ipad_buffer, 931 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 932 bcopy(md5ctx.state, ses->ses_hminner, 933 sizeof(md5ctx.state)); 934 } else { 935 SHA1Init(&sha1ctx); 936 SHA1Update(&sha1ctx, macini->cri_key, 937 macini->cri_klen / 8); 938 SHA1Update(&sha1ctx, hmac_ipad_buffer, 939 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 940 bcopy(sha1ctx.h.b32, ses->ses_hminner, 941 sizeof(sha1ctx.h.b32)); 942 } 943 944 for (i = 0; i < macini->cri_klen / 8; i++) 945 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 946 947 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 948 MD5Init(&md5ctx); 949 MD5Update(&md5ctx, macini->cri_key, 950 macini->cri_klen / 8); 951 MD5Update(&md5ctx, hmac_opad_buffer, 952 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 953 bcopy(md5ctx.state, ses->ses_hmouter, 954 sizeof(md5ctx.state)); 955 } else { 956 SHA1Init(&sha1ctx); 957 SHA1Update(&sha1ctx, macini->cri_key, 958 macini->cri_klen / 8); 959 SHA1Update(&sha1ctx, hmac_opad_buffer, 960 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 961 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 962 sizeof(sha1ctx.h.b32)); 963 } 964 965 for (i = 0; i < macini->cri_klen / 8; i++) 966 macini->cri_key[i] ^= HMAC_OPAD_VAL; 967 } 968 969 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 970 return (0); 971 } 972 973 /* 974 * Deallocate a session. 975 */ 976 static int 977 ubsec_freesession(void *arg, u_int64_t tid) 978 { 979 struct ubsec_softc *sc = arg; 980 int session; 981 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 982 983 KASSERT(sc != NULL, ("ubsec_freesession: null softc")); 984 if (sc == NULL) 985 return (EINVAL); 986 987 session = UBSEC_SESSION(sid); 988 if (session >= sc->sc_nsessions) 989 return (EINVAL); 990 991 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 992 return (0); 993 } 994 995 static void 996 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 997 { 998 struct ubsec_operand *op = arg; 999 1000 KASSERT(nsegs <= UBS_MAX_SCATTER, 1001 ("Too many DMA segments returned when mapping operand")); 1002 #ifdef UBSEC_DEBUG 1003 if (ubsec_debug) 1004 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1005 (u_int) mapsize, nsegs); 1006 #endif 1007 op->mapsize = mapsize; 1008 op->nsegs = nsegs; 1009 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1010 } 1011 1012 static int 1013 ubsec_process(void *arg, struct cryptop *crp, int hint) 1014 { 1015 struct ubsec_q *q = NULL; 1016 int err = 0, i, j, nicealign; 1017 struct ubsec_softc *sc = arg; 1018 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1019 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1020 int sskip, dskip, stheend, dtheend; 1021 int16_t coffset; 1022 struct ubsec_session *ses; 1023 struct ubsec_pktctx ctx; 1024 struct ubsec_dma *dmap = NULL; 1025 1026 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1027 ubsecstats.hst_invalid++; 1028 return (EINVAL); 1029 } 1030 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1031 ubsecstats.hst_badsession++; 1032 return (EINVAL); 1033 } 1034 1035 UBSEC_LOCK(sc); 1036 1037 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1038 ubsecstats.hst_queuefull++; 1039 sc->sc_needwakeup |= CRYPTO_SYMQ; 1040 UBSEC_UNLOCK(sc); 1041 return (ERESTART); 1042 } 1043 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1044 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1045 UBSEC_UNLOCK(sc); 1046 1047 dmap = q->q_dma; /* Save dma pointer */ 1048 bzero(q, sizeof(struct ubsec_q)); 1049 bzero(&ctx, sizeof(ctx)); 1050 1051 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1052 q->q_dma = dmap; 1053 ses = &sc->sc_sessions[q->q_sesn]; 1054 1055 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1056 q->q_src_m = (struct mbuf *)crp->crp_buf; 1057 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1058 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1059 q->q_src_io = (struct uio *)crp->crp_buf; 1060 q->q_dst_io = (struct uio *)crp->crp_buf; 1061 } else { 1062 ubsecstats.hst_badflags++; 1063 err = EINVAL; 1064 goto errout; /* XXX we don't handle contiguous blocks! */ 1065 } 1066 1067 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1068 1069 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1070 dmap->d_dma->d_mcr.mcr_flags = 0; 1071 q->q_crp = crp; 1072 1073 crd1 = crp->crp_desc; 1074 if (crd1 == NULL) { 1075 ubsecstats.hst_nodesc++; 1076 err = EINVAL; 1077 goto errout; 1078 } 1079 crd2 = crd1->crd_next; 1080 1081 if (crd2 == NULL) { 1082 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1083 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1084 maccrd = crd1; 1085 enccrd = NULL; 1086 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1087 crd1->crd_alg == CRYPTO_3DES_CBC) { 1088 maccrd = NULL; 1089 enccrd = crd1; 1090 } else { 1091 ubsecstats.hst_badalg++; 1092 err = EINVAL; 1093 goto errout; 1094 } 1095 } else { 1096 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1097 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1098 (crd2->crd_alg == CRYPTO_DES_CBC || 1099 crd2->crd_alg == CRYPTO_3DES_CBC) && 1100 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1101 maccrd = crd1; 1102 enccrd = crd2; 1103 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1104 crd1->crd_alg == CRYPTO_3DES_CBC) && 1105 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1106 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1107 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1108 enccrd = crd1; 1109 maccrd = crd2; 1110 } else { 1111 /* 1112 * We cannot order the ubsec as requested 1113 */ 1114 ubsecstats.hst_badalg++; 1115 err = EINVAL; 1116 goto errout; 1117 } 1118 } 1119 1120 if (enccrd) { 1121 encoffset = enccrd->crd_skip; 1122 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1123 1124 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1125 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1126 1127 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1128 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1129 else { 1130 ctx.pc_iv[0] = ses->ses_iv[0]; 1131 ctx.pc_iv[1] = ses->ses_iv[1]; 1132 } 1133 1134 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1135 if (crp->crp_flags & CRYPTO_F_IMBUF) 1136 m_copyback(q->q_src_m, 1137 enccrd->crd_inject, 1138 8, (caddr_t)ctx.pc_iv); 1139 else if (crp->crp_flags & CRYPTO_F_IOV) 1140 cuio_copyback(q->q_src_io, 1141 enccrd->crd_inject, 1142 8, (caddr_t)ctx.pc_iv); 1143 } 1144 } else { 1145 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1146 1147 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1148 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1149 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1150 m_copydata(q->q_src_m, enccrd->crd_inject, 1151 8, (caddr_t)ctx.pc_iv); 1152 else if (crp->crp_flags & CRYPTO_F_IOV) 1153 cuio_copydata(q->q_src_io, 1154 enccrd->crd_inject, 8, 1155 (caddr_t)ctx.pc_iv); 1156 } 1157 1158 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1159 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1160 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1161 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1162 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1163 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1164 SWAP32(ctx.pc_iv[0]); 1165 SWAP32(ctx.pc_iv[1]); 1166 } 1167 1168 if (maccrd) { 1169 macoffset = maccrd->crd_skip; 1170 1171 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1172 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1173 else 1174 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1175 1176 for (i = 0; i < 5; i++) { 1177 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1178 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1179 1180 HTOLE32(ctx.pc_hminner[i]); 1181 HTOLE32(ctx.pc_hmouter[i]); 1182 } 1183 } 1184 1185 if (enccrd && maccrd) { 1186 /* 1187 * ubsec cannot handle packets where the end of encryption 1188 * and authentication are not the same, or where the 1189 * encrypted part begins before the authenticated part. 1190 */ 1191 if ((encoffset + enccrd->crd_len) != 1192 (macoffset + maccrd->crd_len)) { 1193 ubsecstats.hst_lenmismatch++; 1194 err = EINVAL; 1195 goto errout; 1196 } 1197 if (enccrd->crd_skip < maccrd->crd_skip) { 1198 ubsecstats.hst_skipmismatch++; 1199 err = EINVAL; 1200 goto errout; 1201 } 1202 sskip = maccrd->crd_skip; 1203 cpskip = dskip = enccrd->crd_skip; 1204 stheend = maccrd->crd_len; 1205 dtheend = enccrd->crd_len; 1206 coffset = enccrd->crd_skip - maccrd->crd_skip; 1207 cpoffset = cpskip + dtheend; 1208 #ifdef UBSEC_DEBUG 1209 if (ubsec_debug) { 1210 printf("mac: skip %d, len %d, inject %d\n", 1211 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1212 printf("enc: skip %d, len %d, inject %d\n", 1213 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1214 printf("src: skip %d, len %d\n", sskip, stheend); 1215 printf("dst: skip %d, len %d\n", dskip, dtheend); 1216 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1217 coffset, stheend, cpskip, cpoffset); 1218 } 1219 #endif 1220 } else { 1221 cpskip = dskip = sskip = macoffset + encoffset; 1222 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1223 cpoffset = cpskip + dtheend; 1224 coffset = 0; 1225 } 1226 ctx.pc_offset = htole16(coffset >> 2); 1227 1228 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1229 ubsecstats.hst_nomap++; 1230 err = ENOMEM; 1231 goto errout; 1232 } 1233 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1234 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1235 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1236 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1237 q->q_src_map = NULL; 1238 ubsecstats.hst_noload++; 1239 err = ENOMEM; 1240 goto errout; 1241 } 1242 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1243 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1244 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1245 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1246 q->q_src_map = NULL; 1247 ubsecstats.hst_noload++; 1248 err = ENOMEM; 1249 goto errout; 1250 } 1251 } 1252 nicealign = ubsec_dmamap_aligned(&q->q_src); 1253 1254 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1255 1256 #ifdef UBSEC_DEBUG 1257 if (ubsec_debug) 1258 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1259 #endif 1260 for (i = j = 0; i < q->q_src_nsegs; i++) { 1261 struct ubsec_pktbuf *pb; 1262 bus_size_t packl = q->q_src_segs[i].ds_len; 1263 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1264 1265 if (sskip >= packl) { 1266 sskip -= packl; 1267 continue; 1268 } 1269 1270 packl -= sskip; 1271 packp += sskip; 1272 sskip = 0; 1273 1274 if (packl > 0xfffc) { 1275 err = EIO; 1276 goto errout; 1277 } 1278 1279 if (j == 0) 1280 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1281 else 1282 pb = &dmap->d_dma->d_sbuf[j - 1]; 1283 1284 pb->pb_addr = htole32(packp); 1285 1286 if (stheend) { 1287 if (packl > stheend) { 1288 pb->pb_len = htole32(stheend); 1289 stheend = 0; 1290 } else { 1291 pb->pb_len = htole32(packl); 1292 stheend -= packl; 1293 } 1294 } else 1295 pb->pb_len = htole32(packl); 1296 1297 if ((i + 1) == q->q_src_nsegs) 1298 pb->pb_next = 0; 1299 else 1300 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1301 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1302 j++; 1303 } 1304 1305 if (enccrd == NULL && maccrd != NULL) { 1306 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1307 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1308 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1309 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1310 #ifdef UBSEC_DEBUG 1311 if (ubsec_debug) 1312 printf("opkt: %x %x %x\n", 1313 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1314 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1315 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1316 #endif 1317 } else { 1318 if (crp->crp_flags & CRYPTO_F_IOV) { 1319 if (!nicealign) { 1320 ubsecstats.hst_iovmisaligned++; 1321 err = EINVAL; 1322 goto errout; 1323 } 1324 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1325 &q->q_dst_map)) { 1326 ubsecstats.hst_nomap++; 1327 err = ENOMEM; 1328 goto errout; 1329 } 1330 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1331 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1332 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1333 q->q_dst_map = NULL; 1334 ubsecstats.hst_noload++; 1335 err = ENOMEM; 1336 goto errout; 1337 } 1338 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1339 if (nicealign) { 1340 q->q_dst = q->q_src; 1341 } else { 1342 int totlen, len; 1343 struct mbuf *m, *top, **mp; 1344 1345 ubsecstats.hst_unaligned++; 1346 totlen = q->q_src_mapsize; 1347 if (q->q_src_m->m_flags & M_PKTHDR) { 1348 len = MHLEN; 1349 MGETHDR(m, M_DONTWAIT, MT_DATA); 1350 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1351 m_free(m); 1352 m = NULL; 1353 } 1354 } else { 1355 len = MLEN; 1356 MGET(m, M_DONTWAIT, MT_DATA); 1357 } 1358 if (m == NULL) { 1359 ubsecstats.hst_nombuf++; 1360 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1361 goto errout; 1362 } 1363 if (totlen >= MINCLSIZE) { 1364 MCLGET(m, M_DONTWAIT); 1365 if ((m->m_flags & M_EXT) == 0) { 1366 m_free(m); 1367 ubsecstats.hst_nomcl++; 1368 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1369 goto errout; 1370 } 1371 len = MCLBYTES; 1372 } 1373 m->m_len = len; 1374 top = NULL; 1375 mp = ⊤ 1376 1377 while (totlen > 0) { 1378 if (top) { 1379 MGET(m, M_DONTWAIT, MT_DATA); 1380 if (m == NULL) { 1381 m_freem(top); 1382 ubsecstats.hst_nombuf++; 1383 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1384 goto errout; 1385 } 1386 len = MLEN; 1387 } 1388 if (top && totlen >= MINCLSIZE) { 1389 MCLGET(m, M_DONTWAIT); 1390 if ((m->m_flags & M_EXT) == 0) { 1391 *mp = m; 1392 m_freem(top); 1393 ubsecstats.hst_nomcl++; 1394 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1395 goto errout; 1396 } 1397 len = MCLBYTES; 1398 } 1399 m->m_len = len = min(totlen, len); 1400 totlen -= len; 1401 *mp = m; 1402 mp = &m->m_next; 1403 } 1404 q->q_dst_m = top; 1405 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1406 cpskip, cpoffset); 1407 if (bus_dmamap_create(sc->sc_dmat, 1408 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1409 ubsecstats.hst_nomap++; 1410 err = ENOMEM; 1411 goto errout; 1412 } 1413 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1414 q->q_dst_map, q->q_dst_m, 1415 ubsec_op_cb, &q->q_dst, 1416 BUS_DMA_NOWAIT) != 0) { 1417 bus_dmamap_destroy(sc->sc_dmat, 1418 q->q_dst_map); 1419 q->q_dst_map = NULL; 1420 ubsecstats.hst_noload++; 1421 err = ENOMEM; 1422 goto errout; 1423 } 1424 } 1425 } else { 1426 ubsecstats.hst_badflags++; 1427 err = EINVAL; 1428 goto errout; 1429 } 1430 1431 #ifdef UBSEC_DEBUG 1432 if (ubsec_debug) 1433 printf("dst skip: %d\n", dskip); 1434 #endif 1435 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1436 struct ubsec_pktbuf *pb; 1437 bus_size_t packl = q->q_dst_segs[i].ds_len; 1438 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1439 1440 if (dskip >= packl) { 1441 dskip -= packl; 1442 continue; 1443 } 1444 1445 packl -= dskip; 1446 packp += dskip; 1447 dskip = 0; 1448 1449 if (packl > 0xfffc) { 1450 err = EIO; 1451 goto errout; 1452 } 1453 1454 if (j == 0) 1455 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1456 else 1457 pb = &dmap->d_dma->d_dbuf[j - 1]; 1458 1459 pb->pb_addr = htole32(packp); 1460 1461 if (dtheend) { 1462 if (packl > dtheend) { 1463 pb->pb_len = htole32(dtheend); 1464 dtheend = 0; 1465 } else { 1466 pb->pb_len = htole32(packl); 1467 dtheend -= packl; 1468 } 1469 } else 1470 pb->pb_len = htole32(packl); 1471 1472 if ((i + 1) == q->q_dst_nsegs) { 1473 if (maccrd) 1474 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1475 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1476 else 1477 pb->pb_next = 0; 1478 } else 1479 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1480 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1481 j++; 1482 } 1483 } 1484 1485 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1486 offsetof(struct ubsec_dmachunk, d_ctx)); 1487 1488 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1489 struct ubsec_pktctx_long *ctxl; 1490 1491 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1492 offsetof(struct ubsec_dmachunk, d_ctx)); 1493 1494 /* transform small context into long context */ 1495 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1496 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1497 ctxl->pc_flags = ctx.pc_flags; 1498 ctxl->pc_offset = ctx.pc_offset; 1499 for (i = 0; i < 6; i++) 1500 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1501 for (i = 0; i < 5; i++) 1502 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1503 for (i = 0; i < 5; i++) 1504 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1505 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1506 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1507 } else 1508 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1509 offsetof(struct ubsec_dmachunk, d_ctx), 1510 sizeof(struct ubsec_pktctx)); 1511 1512 UBSEC_LOCK(sc); 1513 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1514 sc->sc_nqueue++; 1515 ubsecstats.hst_ipackets++; 1516 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1517 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1518 ubsec_feed(sc); 1519 UBSEC_UNLOCK(sc); 1520 return (0); 1521 1522 errout: 1523 if (q != NULL) { 1524 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1525 m_freem(q->q_dst_m); 1526 1527 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1528 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1529 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1530 } 1531 if (q->q_src_map != NULL) { 1532 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1533 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1534 } 1535 1536 UBSEC_LOCK(sc); 1537 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1538 UBSEC_UNLOCK(sc); 1539 } 1540 if (err != ERESTART) { 1541 crp->crp_etype = err; 1542 crypto_done(crp); 1543 } else { 1544 sc->sc_needwakeup |= CRYPTO_SYMQ; 1545 } 1546 return (err); 1547 } 1548 1549 static void 1550 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1551 { 1552 struct cryptop *crp = (struct cryptop *)q->q_crp; 1553 struct cryptodesc *crd; 1554 struct ubsec_dma *dmap = q->q_dma; 1555 1556 ubsecstats.hst_opackets++; 1557 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1558 1559 ubsec_dma_sync(&dmap->d_alloc, 1560 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1561 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1562 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1563 BUS_DMASYNC_POSTREAD); 1564 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1565 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1566 } 1567 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1568 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1569 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1570 1571 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1572 m_freem(q->q_src_m); 1573 crp->crp_buf = (caddr_t)q->q_dst_m; 1574 } 1575 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1576 1577 /* copy out IV for future use */ 1578 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1579 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1580 if (crd->crd_alg != CRYPTO_DES_CBC && 1581 crd->crd_alg != CRYPTO_3DES_CBC) 1582 continue; 1583 if (crp->crp_flags & CRYPTO_F_IMBUF) 1584 m_copydata((struct mbuf *)crp->crp_buf, 1585 crd->crd_skip + crd->crd_len - 8, 8, 1586 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1587 else if (crp->crp_flags & CRYPTO_F_IOV) { 1588 cuio_copydata((struct uio *)crp->crp_buf, 1589 crd->crd_skip + crd->crd_len - 8, 8, 1590 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1591 } 1592 break; 1593 } 1594 } 1595 1596 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1597 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1598 crd->crd_alg != CRYPTO_SHA1_HMAC) 1599 continue; 1600 if (crp->crp_flags & CRYPTO_F_IMBUF) 1601 m_copyback((struct mbuf *)crp->crp_buf, 1602 crd->crd_inject, 12, 1603 (caddr_t)dmap->d_dma->d_macbuf); 1604 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1605 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1606 crp->crp_mac, 12); 1607 break; 1608 } 1609 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1610 crypto_done(crp); 1611 } 1612 1613 static void 1614 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1615 { 1616 int i, j, dlen, slen; 1617 caddr_t dptr, sptr; 1618 1619 j = 0; 1620 sptr = srcm->m_data; 1621 slen = srcm->m_len; 1622 dptr = dstm->m_data; 1623 dlen = dstm->m_len; 1624 1625 while (1) { 1626 for (i = 0; i < min(slen, dlen); i++) { 1627 if (j < hoffset || j >= toffset) 1628 *dptr++ = *sptr++; 1629 slen--; 1630 dlen--; 1631 j++; 1632 } 1633 if (slen == 0) { 1634 srcm = srcm->m_next; 1635 if (srcm == NULL) 1636 return; 1637 sptr = srcm->m_data; 1638 slen = srcm->m_len; 1639 } 1640 if (dlen == 0) { 1641 dstm = dstm->m_next; 1642 if (dstm == NULL) 1643 return; 1644 dptr = dstm->m_data; 1645 dlen = dstm->m_len; 1646 } 1647 } 1648 } 1649 1650 /* 1651 * feed the key generator, must be called at splimp() or higher. 1652 */ 1653 static int 1654 ubsec_feed2(struct ubsec_softc *sc) 1655 { 1656 struct ubsec_q2 *q; 1657 1658 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1659 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1660 break; 1661 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1662 1663 ubsec_dma_sync(&q->q_mcr, 1664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1665 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1666 1667 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1668 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1669 --sc->sc_nqueue2; 1670 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1671 } 1672 return (0); 1673 } 1674 1675 /* 1676 * Callback for handling random numbers 1677 */ 1678 static void 1679 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1680 { 1681 struct cryptkop *krp; 1682 struct ubsec_ctx_keyop *ctx; 1683 1684 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1685 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1686 1687 switch (q->q_type) { 1688 #ifndef UBSEC_NO_RNG 1689 case UBS_CTXOP_RNGBYPASS: { 1690 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1691 1692 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1693 (*sc->sc_harvest)(sc->sc_rndtest, 1694 rng->rng_buf.dma_vaddr, 1695 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1696 rng->rng_used = 0; 1697 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1698 break; 1699 } 1700 #endif 1701 case UBS_CTXOP_MODEXP: { 1702 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1703 u_int rlen, clen; 1704 1705 krp = me->me_krp; 1706 rlen = (me->me_modbits + 7) / 8; 1707 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1708 1709 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1710 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1711 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1712 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1713 1714 if (clen < rlen) 1715 krp->krp_status = E2BIG; 1716 else { 1717 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1718 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1719 (krp->krp_param[krp->krp_iparams].crp_nbits 1720 + 7) / 8); 1721 bcopy(me->me_C.dma_vaddr, 1722 krp->krp_param[krp->krp_iparams].crp_p, 1723 (me->me_modbits + 7) / 8); 1724 } else 1725 ubsec_kshift_l(me->me_shiftbits, 1726 me->me_C.dma_vaddr, me->me_normbits, 1727 krp->krp_param[krp->krp_iparams].crp_p, 1728 krp->krp_param[krp->krp_iparams].crp_nbits); 1729 } 1730 1731 crypto_kdone(krp); 1732 1733 /* bzero all potentially sensitive data */ 1734 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1735 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1736 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1737 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1738 1739 /* Can't free here, so put us on the free list. */ 1740 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1741 break; 1742 } 1743 case UBS_CTXOP_RSAPRIV: { 1744 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1745 u_int len; 1746 1747 krp = rp->rpr_krp; 1748 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1749 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1750 1751 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1752 bcopy(rp->rpr_msgout.dma_vaddr, 1753 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1754 1755 crypto_kdone(krp); 1756 1757 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1758 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1759 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1760 1761 /* Can't free here, so put us on the free list. */ 1762 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1763 break; 1764 } 1765 default: 1766 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1767 letoh16(ctx->ctx_op)); 1768 break; 1769 } 1770 } 1771 1772 #ifndef UBSEC_NO_RNG 1773 static void 1774 ubsec_rng(void *vsc) 1775 { 1776 struct ubsec_softc *sc = vsc; 1777 struct ubsec_q2_rng *rng = &sc->sc_rng; 1778 struct ubsec_mcr *mcr; 1779 struct ubsec_ctx_rngbypass *ctx; 1780 1781 UBSEC_LOCK(sc); 1782 if (rng->rng_used) { 1783 UBSEC_UNLOCK(sc); 1784 return; 1785 } 1786 sc->sc_nqueue2++; 1787 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1788 goto out; 1789 1790 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1791 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1792 1793 mcr->mcr_pkts = htole16(1); 1794 mcr->mcr_flags = 0; 1795 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1796 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1797 mcr->mcr_ipktbuf.pb_len = 0; 1798 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1799 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1800 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1801 UBS_PKTBUF_LEN); 1802 mcr->mcr_opktbuf.pb_next = 0; 1803 1804 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1805 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1806 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1807 1808 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1809 1810 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1811 rng->rng_used = 1; 1812 ubsec_feed2(sc); 1813 ubsecstats.hst_rng++; 1814 UBSEC_UNLOCK(sc); 1815 1816 return; 1817 1818 out: 1819 /* 1820 * Something weird happened, generate our own call back. 1821 */ 1822 sc->sc_nqueue2--; 1823 UBSEC_UNLOCK(sc); 1824 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1825 } 1826 #endif /* UBSEC_NO_RNG */ 1827 1828 static void 1829 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1830 { 1831 bus_addr_t *paddr = (bus_addr_t*) arg; 1832 *paddr = segs->ds_addr; 1833 } 1834 1835 static int 1836 ubsec_dma_malloc( 1837 struct ubsec_softc *sc, 1838 bus_size_t size, 1839 struct ubsec_dma_alloc *dma, 1840 int mapflags 1841 ) 1842 { 1843 int r; 1844 1845 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1846 r = bus_dma_tag_create(NULL, /* parent */ 1847 1, 0, /* alignment, bounds */ 1848 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1849 BUS_SPACE_MAXADDR, /* highaddr */ 1850 NULL, NULL, /* filter, filterarg */ 1851 size, /* maxsize */ 1852 1, /* nsegments */ 1853 size, /* maxsegsize */ 1854 BUS_DMA_ALLOCNOW, /* flags */ 1855 &dma->dma_tag); 1856 if (r != 0) { 1857 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1858 "bus_dma_tag_create failed; error %u\n", r); 1859 goto fail_0; 1860 } 1861 1862 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1863 if (r != 0) { 1864 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1865 "bus_dmamap_create failed; error %u\n", r); 1866 goto fail_1; 1867 } 1868 1869 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1870 BUS_DMA_NOWAIT, &dma->dma_map); 1871 if (r != 0) { 1872 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1873 "bus_dmammem_alloc failed; size %zu, error %u\n", 1874 size, r); 1875 goto fail_2; 1876 } 1877 1878 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1879 size, 1880 ubsec_dmamap_cb, 1881 &dma->dma_paddr, 1882 mapflags | BUS_DMA_NOWAIT); 1883 if (r != 0) { 1884 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1885 "bus_dmamap_load failed; error %u\n", r); 1886 goto fail_3; 1887 } 1888 1889 dma->dma_size = size; 1890 return (0); 1891 1892 fail_3: 1893 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1894 fail_2: 1895 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1896 fail_1: 1897 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1898 bus_dma_tag_destroy(dma->dma_tag); 1899 fail_0: 1900 dma->dma_map = NULL; 1901 dma->dma_tag = NULL; 1902 return (r); 1903 } 1904 1905 static void 1906 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1907 { 1908 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1909 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1910 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1911 bus_dma_tag_destroy(dma->dma_tag); 1912 } 1913 1914 /* 1915 * Resets the board. Values in the regesters are left as is 1916 * from the reset (i.e. initial values are assigned elsewhere). 1917 */ 1918 static void 1919 ubsec_reset_board(struct ubsec_softc *sc) 1920 { 1921 volatile u_int32_t ctrl; 1922 1923 ctrl = READ_REG(sc, BS_CTRL); 1924 ctrl |= BS_CTRL_RESET; 1925 WRITE_REG(sc, BS_CTRL, ctrl); 1926 1927 /* 1928 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1929 */ 1930 DELAY(10); 1931 } 1932 1933 /* 1934 * Init Broadcom registers 1935 */ 1936 static void 1937 ubsec_init_board(struct ubsec_softc *sc) 1938 { 1939 u_int32_t ctrl; 1940 1941 ctrl = READ_REG(sc, BS_CTRL); 1942 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1943 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1944 1945 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1946 ctrl |= BS_CTRL_MCR2INT; 1947 else 1948 ctrl &= ~BS_CTRL_MCR2INT; 1949 1950 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1951 ctrl &= ~BS_CTRL_SWNORM; 1952 1953 WRITE_REG(sc, BS_CTRL, ctrl); 1954 } 1955 1956 /* 1957 * Init Broadcom PCI registers 1958 */ 1959 static void 1960 ubsec_init_pciregs(device_t dev) 1961 { 1962 #if 0 1963 u_int32_t misc; 1964 1965 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1966 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1967 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1968 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1969 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1970 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1971 #endif 1972 1973 /* 1974 * This will set the cache line size to 1, this will 1975 * force the BCM58xx chip just to do burst read/writes. 1976 * Cache line read/writes are to slow 1977 */ 1978 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1979 } 1980 1981 /* 1982 * Clean up after a chip crash. 1983 * It is assumed that the caller in splimp() 1984 */ 1985 static void 1986 ubsec_cleanchip(struct ubsec_softc *sc) 1987 { 1988 struct ubsec_q *q; 1989 1990 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1991 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1992 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1993 ubsec_free_q(sc, q); 1994 } 1995 sc->sc_nqchip = 0; 1996 } 1997 1998 /* 1999 * free a ubsec_q 2000 * It is assumed that the caller is within splimp(). 2001 */ 2002 static int 2003 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2004 { 2005 struct ubsec_q *q2; 2006 struct cryptop *crp; 2007 int npkts; 2008 int i; 2009 2010 npkts = q->q_nstacked_mcrs; 2011 2012 for (i = 0; i < npkts; i++) { 2013 if(q->q_stacked_mcr[i]) { 2014 q2 = q->q_stacked_mcr[i]; 2015 2016 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2017 m_freem(q2->q_dst_m); 2018 2019 crp = (struct cryptop *)q2->q_crp; 2020 2021 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2022 2023 crp->crp_etype = EFAULT; 2024 crypto_done(crp); 2025 } else { 2026 break; 2027 } 2028 } 2029 2030 /* 2031 * Free header MCR 2032 */ 2033 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2034 m_freem(q->q_dst_m); 2035 2036 crp = (struct cryptop *)q->q_crp; 2037 2038 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2039 2040 crp->crp_etype = EFAULT; 2041 crypto_done(crp); 2042 return(0); 2043 } 2044 2045 /* 2046 * Routine to reset the chip and clean up. 2047 * It is assumed that the caller is in splimp() 2048 */ 2049 static void 2050 ubsec_totalreset(struct ubsec_softc *sc) 2051 { 2052 ubsec_reset_board(sc); 2053 ubsec_init_board(sc); 2054 ubsec_cleanchip(sc); 2055 } 2056 2057 static int 2058 ubsec_dmamap_aligned(struct ubsec_operand *op) 2059 { 2060 int i; 2061 2062 for (i = 0; i < op->nsegs; i++) { 2063 if (op->segs[i].ds_addr & 3) 2064 return (0); 2065 if ((i != (op->nsegs - 1)) && 2066 (op->segs[i].ds_len & 3)) 2067 return (0); 2068 } 2069 return (1); 2070 } 2071 2072 static void 2073 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2074 { 2075 switch (q->q_type) { 2076 case UBS_CTXOP_MODEXP: { 2077 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2078 2079 ubsec_dma_free(sc, &me->me_q.q_mcr); 2080 ubsec_dma_free(sc, &me->me_q.q_ctx); 2081 ubsec_dma_free(sc, &me->me_M); 2082 ubsec_dma_free(sc, &me->me_E); 2083 ubsec_dma_free(sc, &me->me_C); 2084 ubsec_dma_free(sc, &me->me_epb); 2085 free(me, M_DEVBUF); 2086 break; 2087 } 2088 case UBS_CTXOP_RSAPRIV: { 2089 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2090 2091 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2092 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2093 ubsec_dma_free(sc, &rp->rpr_msgin); 2094 ubsec_dma_free(sc, &rp->rpr_msgout); 2095 free(rp, M_DEVBUF); 2096 break; 2097 } 2098 default: 2099 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2100 break; 2101 } 2102 } 2103 2104 static int 2105 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2106 { 2107 struct ubsec_softc *sc = arg; 2108 int r; 2109 2110 if (krp == NULL || krp->krp_callback == NULL) 2111 return (EINVAL); 2112 2113 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2114 struct ubsec_q2 *q; 2115 2116 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2117 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2118 ubsec_kfree(sc, q); 2119 } 2120 2121 switch (krp->krp_op) { 2122 case CRK_MOD_EXP: 2123 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2124 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2125 else 2126 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2127 break; 2128 case CRK_MOD_EXP_CRT: 2129 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2130 default: 2131 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2132 krp->krp_op); 2133 krp->krp_status = EOPNOTSUPP; 2134 crypto_kdone(krp); 2135 return (0); 2136 } 2137 return (0); /* silence compiler */ 2138 } 2139 2140 /* 2141 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2142 */ 2143 static int 2144 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2145 { 2146 struct ubsec_q2_modexp *me; 2147 struct ubsec_mcr *mcr; 2148 struct ubsec_ctx_modexp *ctx; 2149 struct ubsec_pktbuf *epb; 2150 int err = 0; 2151 u_int nbits, normbits, mbits, shiftbits, ebits; 2152 2153 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2154 if (me == NULL) { 2155 err = ENOMEM; 2156 goto errout; 2157 } 2158 bzero(me, sizeof *me); 2159 me->me_krp = krp; 2160 me->me_q.q_type = UBS_CTXOP_MODEXP; 2161 2162 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2163 if (nbits <= 512) 2164 normbits = 512; 2165 else if (nbits <= 768) 2166 normbits = 768; 2167 else if (nbits <= 1024) 2168 normbits = 1024; 2169 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2170 normbits = 1536; 2171 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2172 normbits = 2048; 2173 else { 2174 err = E2BIG; 2175 goto errout; 2176 } 2177 2178 shiftbits = normbits - nbits; 2179 2180 me->me_modbits = nbits; 2181 me->me_shiftbits = shiftbits; 2182 me->me_normbits = normbits; 2183 2184 /* Sanity check: result bits must be >= true modulus bits. */ 2185 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2186 err = ERANGE; 2187 goto errout; 2188 } 2189 2190 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2191 &me->me_q.q_mcr, 0)) { 2192 err = ENOMEM; 2193 goto errout; 2194 } 2195 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2196 2197 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2198 &me->me_q.q_ctx, 0)) { 2199 err = ENOMEM; 2200 goto errout; 2201 } 2202 2203 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2204 if (mbits > nbits) { 2205 err = E2BIG; 2206 goto errout; 2207 } 2208 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2209 err = ENOMEM; 2210 goto errout; 2211 } 2212 ubsec_kshift_r(shiftbits, 2213 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2214 me->me_M.dma_vaddr, normbits); 2215 2216 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2217 err = ENOMEM; 2218 goto errout; 2219 } 2220 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2221 2222 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2223 if (ebits > nbits) { 2224 err = E2BIG; 2225 goto errout; 2226 } 2227 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2228 err = ENOMEM; 2229 goto errout; 2230 } 2231 ubsec_kshift_r(shiftbits, 2232 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2233 me->me_E.dma_vaddr, normbits); 2234 2235 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2236 &me->me_epb, 0)) { 2237 err = ENOMEM; 2238 goto errout; 2239 } 2240 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2241 epb->pb_addr = htole32(me->me_E.dma_paddr); 2242 epb->pb_next = 0; 2243 epb->pb_len = htole32(normbits / 8); 2244 2245 #ifdef UBSEC_DEBUG 2246 if (ubsec_debug) { 2247 printf("Epb "); 2248 ubsec_dump_pb(epb); 2249 } 2250 #endif 2251 2252 mcr->mcr_pkts = htole16(1); 2253 mcr->mcr_flags = 0; 2254 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2255 mcr->mcr_reserved = 0; 2256 mcr->mcr_pktlen = 0; 2257 2258 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2259 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2260 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2261 2262 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2263 mcr->mcr_opktbuf.pb_next = 0; 2264 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2265 2266 #ifdef DIAGNOSTIC 2267 /* Misaligned output buffer will hang the chip. */ 2268 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2269 panic("%s: modexp invalid addr 0x%x\n", 2270 device_get_nameunit(sc->sc_dev), 2271 letoh32(mcr->mcr_opktbuf.pb_addr)); 2272 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2273 panic("%s: modexp invalid len 0x%x\n", 2274 device_get_nameunit(sc->sc_dev), 2275 letoh32(mcr->mcr_opktbuf.pb_len)); 2276 #endif 2277 2278 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2279 bzero(ctx, sizeof(*ctx)); 2280 ubsec_kshift_r(shiftbits, 2281 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2282 ctx->me_N, normbits); 2283 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2284 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2285 ctx->me_E_len = htole16(nbits); 2286 ctx->me_N_len = htole16(nbits); 2287 2288 #ifdef UBSEC_DEBUG 2289 if (ubsec_debug) { 2290 ubsec_dump_mcr(mcr); 2291 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2292 } 2293 #endif 2294 2295 /* 2296 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2297 * everything else. 2298 */ 2299 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2300 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2301 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2302 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2303 2304 /* Enqueue and we're done... */ 2305 UBSEC_LOCK(sc); 2306 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2307 ubsec_feed2(sc); 2308 ubsecstats.hst_modexp++; 2309 UBSEC_UNLOCK(sc); 2310 2311 return (0); 2312 2313 errout: 2314 if (me != NULL) { 2315 if (me->me_q.q_mcr.dma_map != NULL) 2316 ubsec_dma_free(sc, &me->me_q.q_mcr); 2317 if (me->me_q.q_ctx.dma_map != NULL) { 2318 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2319 ubsec_dma_free(sc, &me->me_q.q_ctx); 2320 } 2321 if (me->me_M.dma_map != NULL) { 2322 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2323 ubsec_dma_free(sc, &me->me_M); 2324 } 2325 if (me->me_E.dma_map != NULL) { 2326 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2327 ubsec_dma_free(sc, &me->me_E); 2328 } 2329 if (me->me_C.dma_map != NULL) { 2330 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2331 ubsec_dma_free(sc, &me->me_C); 2332 } 2333 if (me->me_epb.dma_map != NULL) 2334 ubsec_dma_free(sc, &me->me_epb); 2335 free(me, M_DEVBUF); 2336 } 2337 krp->krp_status = err; 2338 crypto_kdone(krp); 2339 return (0); 2340 } 2341 2342 /* 2343 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2344 */ 2345 static int 2346 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2347 { 2348 struct ubsec_q2_modexp *me; 2349 struct ubsec_mcr *mcr; 2350 struct ubsec_ctx_modexp *ctx; 2351 struct ubsec_pktbuf *epb; 2352 int err = 0; 2353 u_int nbits, normbits, mbits, shiftbits, ebits; 2354 2355 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2356 if (me == NULL) { 2357 err = ENOMEM; 2358 goto errout; 2359 } 2360 bzero(me, sizeof *me); 2361 me->me_krp = krp; 2362 me->me_q.q_type = UBS_CTXOP_MODEXP; 2363 2364 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2365 if (nbits <= 512) 2366 normbits = 512; 2367 else if (nbits <= 768) 2368 normbits = 768; 2369 else if (nbits <= 1024) 2370 normbits = 1024; 2371 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2372 normbits = 1536; 2373 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2374 normbits = 2048; 2375 else { 2376 err = E2BIG; 2377 goto errout; 2378 } 2379 2380 shiftbits = normbits - nbits; 2381 2382 /* XXX ??? */ 2383 me->me_modbits = nbits; 2384 me->me_shiftbits = shiftbits; 2385 me->me_normbits = normbits; 2386 2387 /* Sanity check: result bits must be >= true modulus bits. */ 2388 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2389 err = ERANGE; 2390 goto errout; 2391 } 2392 2393 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2394 &me->me_q.q_mcr, 0)) { 2395 err = ENOMEM; 2396 goto errout; 2397 } 2398 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2399 2400 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2401 &me->me_q.q_ctx, 0)) { 2402 err = ENOMEM; 2403 goto errout; 2404 } 2405 2406 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2407 if (mbits > nbits) { 2408 err = E2BIG; 2409 goto errout; 2410 } 2411 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2412 err = ENOMEM; 2413 goto errout; 2414 } 2415 bzero(me->me_M.dma_vaddr, normbits / 8); 2416 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2417 me->me_M.dma_vaddr, (mbits + 7) / 8); 2418 2419 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2420 err = ENOMEM; 2421 goto errout; 2422 } 2423 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2424 2425 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2426 if (ebits > nbits) { 2427 err = E2BIG; 2428 goto errout; 2429 } 2430 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2431 err = ENOMEM; 2432 goto errout; 2433 } 2434 bzero(me->me_E.dma_vaddr, normbits / 8); 2435 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2436 me->me_E.dma_vaddr, (ebits + 7) / 8); 2437 2438 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2439 &me->me_epb, 0)) { 2440 err = ENOMEM; 2441 goto errout; 2442 } 2443 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2444 epb->pb_addr = htole32(me->me_E.dma_paddr); 2445 epb->pb_next = 0; 2446 epb->pb_len = htole32((ebits + 7) / 8); 2447 2448 #ifdef UBSEC_DEBUG 2449 if (ubsec_debug) { 2450 printf("Epb "); 2451 ubsec_dump_pb(epb); 2452 } 2453 #endif 2454 2455 mcr->mcr_pkts = htole16(1); 2456 mcr->mcr_flags = 0; 2457 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2458 mcr->mcr_reserved = 0; 2459 mcr->mcr_pktlen = 0; 2460 2461 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2462 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2463 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2464 2465 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2466 mcr->mcr_opktbuf.pb_next = 0; 2467 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2468 2469 #ifdef DIAGNOSTIC 2470 /* Misaligned output buffer will hang the chip. */ 2471 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2472 panic("%s: modexp invalid addr 0x%x\n", 2473 device_get_nameunit(sc->sc_dev), 2474 letoh32(mcr->mcr_opktbuf.pb_addr)); 2475 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2476 panic("%s: modexp invalid len 0x%x\n", 2477 device_get_nameunit(sc->sc_dev), 2478 letoh32(mcr->mcr_opktbuf.pb_len)); 2479 #endif 2480 2481 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2482 bzero(ctx, sizeof(*ctx)); 2483 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2484 (nbits + 7) / 8); 2485 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2486 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2487 ctx->me_E_len = htole16(ebits); 2488 ctx->me_N_len = htole16(nbits); 2489 2490 #ifdef UBSEC_DEBUG 2491 if (ubsec_debug) { 2492 ubsec_dump_mcr(mcr); 2493 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2494 } 2495 #endif 2496 2497 /* 2498 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2499 * everything else. 2500 */ 2501 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2502 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2503 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2504 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2505 2506 /* Enqueue and we're done... */ 2507 UBSEC_LOCK(sc); 2508 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2509 ubsec_feed2(sc); 2510 UBSEC_UNLOCK(sc); 2511 2512 return (0); 2513 2514 errout: 2515 if (me != NULL) { 2516 if (me->me_q.q_mcr.dma_map != NULL) 2517 ubsec_dma_free(sc, &me->me_q.q_mcr); 2518 if (me->me_q.q_ctx.dma_map != NULL) { 2519 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2520 ubsec_dma_free(sc, &me->me_q.q_ctx); 2521 } 2522 if (me->me_M.dma_map != NULL) { 2523 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2524 ubsec_dma_free(sc, &me->me_M); 2525 } 2526 if (me->me_E.dma_map != NULL) { 2527 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2528 ubsec_dma_free(sc, &me->me_E); 2529 } 2530 if (me->me_C.dma_map != NULL) { 2531 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2532 ubsec_dma_free(sc, &me->me_C); 2533 } 2534 if (me->me_epb.dma_map != NULL) 2535 ubsec_dma_free(sc, &me->me_epb); 2536 free(me, M_DEVBUF); 2537 } 2538 krp->krp_status = err; 2539 crypto_kdone(krp); 2540 return (0); 2541 } 2542 2543 static int 2544 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2545 { 2546 struct ubsec_q2_rsapriv *rp = NULL; 2547 struct ubsec_mcr *mcr; 2548 struct ubsec_ctx_rsapriv *ctx; 2549 int err = 0; 2550 u_int padlen, msglen; 2551 2552 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2553 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2554 if (msglen > padlen) 2555 padlen = msglen; 2556 2557 if (padlen <= 256) 2558 padlen = 256; 2559 else if (padlen <= 384) 2560 padlen = 384; 2561 else if (padlen <= 512) 2562 padlen = 512; 2563 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2564 padlen = 768; 2565 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2566 padlen = 1024; 2567 else { 2568 err = E2BIG; 2569 goto errout; 2570 } 2571 2572 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2573 err = E2BIG; 2574 goto errout; 2575 } 2576 2577 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2578 err = E2BIG; 2579 goto errout; 2580 } 2581 2582 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2583 err = E2BIG; 2584 goto errout; 2585 } 2586 2587 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2588 if (rp == NULL) 2589 return (ENOMEM); 2590 bzero(rp, sizeof *rp); 2591 rp->rpr_krp = krp; 2592 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2593 2594 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2595 &rp->rpr_q.q_mcr, 0)) { 2596 err = ENOMEM; 2597 goto errout; 2598 } 2599 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2600 2601 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2602 &rp->rpr_q.q_ctx, 0)) { 2603 err = ENOMEM; 2604 goto errout; 2605 } 2606 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2607 bzero(ctx, sizeof *ctx); 2608 2609 /* Copy in p */ 2610 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2611 &ctx->rpr_buf[0 * (padlen / 8)], 2612 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2613 2614 /* Copy in q */ 2615 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2616 &ctx->rpr_buf[1 * (padlen / 8)], 2617 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2618 2619 /* Copy in dp */ 2620 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2621 &ctx->rpr_buf[2 * (padlen / 8)], 2622 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2623 2624 /* Copy in dq */ 2625 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2626 &ctx->rpr_buf[3 * (padlen / 8)], 2627 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2628 2629 /* Copy in pinv */ 2630 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2631 &ctx->rpr_buf[4 * (padlen / 8)], 2632 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2633 2634 msglen = padlen * 2; 2635 2636 /* Copy in input message (aligned buffer/length). */ 2637 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2638 /* Is this likely? */ 2639 err = E2BIG; 2640 goto errout; 2641 } 2642 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2643 err = ENOMEM; 2644 goto errout; 2645 } 2646 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2647 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2648 rp->rpr_msgin.dma_vaddr, 2649 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2650 2651 /* Prepare space for output message (aligned buffer/length). */ 2652 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2653 /* Is this likely? */ 2654 err = E2BIG; 2655 goto errout; 2656 } 2657 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2658 err = ENOMEM; 2659 goto errout; 2660 } 2661 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2662 2663 mcr->mcr_pkts = htole16(1); 2664 mcr->mcr_flags = 0; 2665 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2666 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2667 mcr->mcr_ipktbuf.pb_next = 0; 2668 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2669 mcr->mcr_reserved = 0; 2670 mcr->mcr_pktlen = htole16(msglen); 2671 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2672 mcr->mcr_opktbuf.pb_next = 0; 2673 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2674 2675 #ifdef DIAGNOSTIC 2676 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2677 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2678 device_get_nameunit(sc->sc_dev), 2679 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2680 } 2681 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2682 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2683 device_get_nameunit(sc->sc_dev), 2684 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2685 } 2686 #endif 2687 2688 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2689 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2690 ctx->rpr_q_len = htole16(padlen); 2691 ctx->rpr_p_len = htole16(padlen); 2692 2693 /* 2694 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2695 * everything else. 2696 */ 2697 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2698 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2699 2700 /* Enqueue and we're done... */ 2701 UBSEC_LOCK(sc); 2702 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2703 ubsec_feed2(sc); 2704 ubsecstats.hst_modexpcrt++; 2705 UBSEC_UNLOCK(sc); 2706 return (0); 2707 2708 errout: 2709 if (rp != NULL) { 2710 if (rp->rpr_q.q_mcr.dma_map != NULL) 2711 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2712 if (rp->rpr_msgin.dma_map != NULL) { 2713 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2714 ubsec_dma_free(sc, &rp->rpr_msgin); 2715 } 2716 if (rp->rpr_msgout.dma_map != NULL) { 2717 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2718 ubsec_dma_free(sc, &rp->rpr_msgout); 2719 } 2720 free(rp, M_DEVBUF); 2721 } 2722 krp->krp_status = err; 2723 crypto_kdone(krp); 2724 return (0); 2725 } 2726 2727 #ifdef UBSEC_DEBUG 2728 static void 2729 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2730 { 2731 printf("addr 0x%x (0x%x) next 0x%x\n", 2732 pb->pb_addr, pb->pb_len, pb->pb_next); 2733 } 2734 2735 static void 2736 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2737 { 2738 printf("CTX (0x%x):\n", c->ctx_len); 2739 switch (letoh16(c->ctx_op)) { 2740 case UBS_CTXOP_RNGBYPASS: 2741 case UBS_CTXOP_RNGSHA1: 2742 break; 2743 case UBS_CTXOP_MODEXP: 2744 { 2745 struct ubsec_ctx_modexp *cx = (void *)c; 2746 int i, len; 2747 2748 printf(" Elen %u, Nlen %u\n", 2749 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2750 len = (cx->me_N_len + 7)/8; 2751 for (i = 0; i < len; i++) 2752 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2753 printf("\n"); 2754 break; 2755 } 2756 default: 2757 printf("unknown context: %x\n", c->ctx_op); 2758 } 2759 printf("END CTX\n"); 2760 } 2761 2762 static void 2763 ubsec_dump_mcr(struct ubsec_mcr *mcr) 2764 { 2765 volatile struct ubsec_mcr_add *ma; 2766 int i; 2767 2768 printf("MCR:\n"); 2769 printf(" pkts: %u, flags 0x%x\n", 2770 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2771 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2772 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2773 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2774 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2775 letoh16(ma->mcr_reserved)); 2776 printf(" %d: ipkt ", i); 2777 ubsec_dump_pb(&ma->mcr_ipktbuf); 2778 printf(" %d: opkt ", i); 2779 ubsec_dump_pb(&ma->mcr_opktbuf); 2780 ma++; 2781 } 2782 printf("END MCR\n"); 2783 } 2784 #endif /* UBSEC_DEBUG */ 2785 2786 /* 2787 * Return the number of significant bits of a big number. 2788 */ 2789 static int 2790 ubsec_ksigbits(struct crparam *cr) 2791 { 2792 u_int plen = (cr->crp_nbits + 7) / 8; 2793 int i, sig = plen * 8; 2794 u_int8_t c, *p = cr->crp_p; 2795 2796 for (i = plen - 1; i >= 0; i--) { 2797 c = p[i]; 2798 if (c != 0) { 2799 while ((c & 0x80) == 0) { 2800 sig--; 2801 c <<= 1; 2802 } 2803 break; 2804 } 2805 sig -= 8; 2806 } 2807 return (sig); 2808 } 2809 2810 static void 2811 ubsec_kshift_r( 2812 u_int shiftbits, 2813 u_int8_t *src, u_int srcbits, 2814 u_int8_t *dst, u_int dstbits) 2815 { 2816 u_int slen, dlen; 2817 int i, si, di, n; 2818 2819 slen = (srcbits + 7) / 8; 2820 dlen = (dstbits + 7) / 8; 2821 2822 for (i = 0; i < slen; i++) 2823 dst[i] = src[i]; 2824 for (i = 0; i < dlen - slen; i++) 2825 dst[slen + i] = 0; 2826 2827 n = shiftbits / 8; 2828 if (n != 0) { 2829 si = dlen - n - 1; 2830 di = dlen - 1; 2831 while (si >= 0) 2832 dst[di--] = dst[si--]; 2833 while (di >= 0) 2834 dst[di--] = 0; 2835 } 2836 2837 n = shiftbits % 8; 2838 if (n != 0) { 2839 for (i = dlen - 1; i > 0; i--) 2840 dst[i] = (dst[i] << n) | 2841 (dst[i - 1] >> (8 - n)); 2842 dst[0] = dst[0] << n; 2843 } 2844 } 2845 2846 static void 2847 ubsec_kshift_l( 2848 u_int shiftbits, 2849 u_int8_t *src, u_int srcbits, 2850 u_int8_t *dst, u_int dstbits) 2851 { 2852 int slen, dlen, i, n; 2853 2854 slen = (srcbits + 7) / 8; 2855 dlen = (dstbits + 7) / 8; 2856 2857 n = shiftbits / 8; 2858 for (i = 0; i < slen; i++) 2859 dst[i] = src[i + n]; 2860 for (i = 0; i < dlen - slen; i++) 2861 dst[slen + i] = 0; 2862 2863 n = shiftbits % 8; 2864 if (n != 0) { 2865 for (i = 0; i < (dlen - 1); i++) 2866 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2867 dst[dlen - 1] = dst[dlen - 1] >> n; 2868 } 2869 }
Cache object: ca1d9cd744afce07894d0bea432b4736
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