FreeBSD/Linux Kernel Cross Reference
sys/dev/ubsec/ubsec.c
1 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
2
3 /*-
4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Effort sponsored in part by the Defense Advanced Research Projects
37 * Agency (DARPA) and Air Force Research Laboratory, Air Force
38 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.29.2.2 2005/03/03 05:02:14 obrien Exp $");
43
44 /*
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
46 */
47
48 #include "opt_ubsec.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/proc.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
57 #include <sys/mbuf.h>
58 #include <sys/lock.h>
59 #include <sys/mutex.h>
60 #include <sys/sysctl.h>
61 #include <sys/endian.h>
62
63 #include <vm/vm.h>
64 #include <vm/pmap.h>
65
66 #include <machine/clock.h>
67 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <sys/bus.h>
70 #include <sys/rman.h>
71
72 #include <crypto/sha1.h>
73 #include <opencrypto/cryptodev.h>
74 #include <opencrypto/cryptosoft.h>
75 #include <sys/md5.h>
76 #include <sys/random.h>
77
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h>
80
81 /* grr, #defines for gratuitous incompatibility in queue.h */
82 #define SIMPLEQ_HEAD STAILQ_HEAD
83 #define SIMPLEQ_ENTRY STAILQ_ENTRY
84 #define SIMPLEQ_INIT STAILQ_INIT
85 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
86 #define SIMPLEQ_EMPTY STAILQ_EMPTY
87 #define SIMPLEQ_FIRST STAILQ_FIRST
88 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL
89 #define SIMPLEQ_FOREACH STAILQ_FOREACH
90 /* ditto for endian.h */
91 #define letoh16(x) le16toh(x)
92 #define letoh32(x) le32toh(x)
93
94 #ifdef UBSEC_RNDTEST
95 #include <dev/rndtest/rndtest.h>
96 #endif
97 #include <dev/ubsec/ubsecreg.h>
98 #include <dev/ubsec/ubsecvar.h>
99
100 /*
101 * Prototypes and count for the pci_device structure
102 */
103 static int ubsec_probe(device_t);
104 static int ubsec_attach(device_t);
105 static int ubsec_detach(device_t);
106 static int ubsec_suspend(device_t);
107 static int ubsec_resume(device_t);
108 static void ubsec_shutdown(device_t);
109
110 static device_method_t ubsec_methods[] = {
111 /* Device interface */
112 DEVMETHOD(device_probe, ubsec_probe),
113 DEVMETHOD(device_attach, ubsec_attach),
114 DEVMETHOD(device_detach, ubsec_detach),
115 DEVMETHOD(device_suspend, ubsec_suspend),
116 DEVMETHOD(device_resume, ubsec_resume),
117 DEVMETHOD(device_shutdown, ubsec_shutdown),
118
119 /* bus interface */
120 DEVMETHOD(bus_print_child, bus_generic_print_child),
121 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
122
123 { 0, 0 }
124 };
125 static driver_t ubsec_driver = {
126 "ubsec",
127 ubsec_methods,
128 sizeof (struct ubsec_softc)
129 };
130 static devclass_t ubsec_devclass;
131
132 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
133 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
134 #ifdef UBSEC_RNDTEST
135 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
136 #endif
137
138 static void ubsec_intr(void *);
139 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
140 static int ubsec_freesession(void *, u_int64_t);
141 static int ubsec_process(void *, struct cryptop *, int);
142 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
143 static void ubsec_feed(struct ubsec_softc *);
144 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
145 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
146 static int ubsec_feed2(struct ubsec_softc *);
147 static void ubsec_rng(void *);
148 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
149 struct ubsec_dma_alloc *, int);
150 #define ubsec_dma_sync(_dma, _flags) \
151 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
152 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
153 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
154
155 static void ubsec_reset_board(struct ubsec_softc *sc);
156 static void ubsec_init_board(struct ubsec_softc *sc);
157 static void ubsec_init_pciregs(device_t dev);
158 static void ubsec_totalreset(struct ubsec_softc *sc);
159
160 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
161
162 static int ubsec_kprocess(void*, struct cryptkop *, int);
163 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
164 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
165 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
166 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
167 static int ubsec_ksigbits(struct crparam *);
168 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
169 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
170
171 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
172
173 #ifdef UBSEC_DEBUG
174 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
175 static void ubsec_dump_mcr(struct ubsec_mcr *);
176 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
177
178 static int ubsec_debug = 0;
179 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
180 0, "control debugging msgs");
181 #endif
182
183 #define READ_REG(sc,r) \
184 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
185
186 #define WRITE_REG(sc,reg,val) \
187 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
188
189 #define SWAP32(x) (x) = htole32(ntohl((x)))
190 #define HTOLE32(x) (x) = htole32(x)
191
192 struct ubsec_stats ubsecstats;
193 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
194 ubsec_stats, "driver statistics");
195
196 static int
197 ubsec_probe(device_t dev)
198 {
199 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
200 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
201 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
202 return (BUS_PROBE_DEFAULT);
203 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
204 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
205 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
206 return (BUS_PROBE_DEFAULT);
207 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
208 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
214 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
215 ))
216 return (BUS_PROBE_DEFAULT);
217 return (ENXIO);
218 }
219
220 static const char*
221 ubsec_partname(struct ubsec_softc *sc)
222 {
223 /* XXX sprintf numbers when not decoded */
224 switch (pci_get_vendor(sc->sc_dev)) {
225 case PCI_VENDOR_BROADCOM:
226 switch (pci_get_device(sc->sc_dev)) {
227 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
228 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
229 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
230 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
231 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
232 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
233 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
234 }
235 return "Broadcom unknown-part";
236 case PCI_VENDOR_BLUESTEEL:
237 switch (pci_get_device(sc->sc_dev)) {
238 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
239 }
240 return "Bluesteel unknown-part";
241 case PCI_VENDOR_SUN:
242 switch (pci_get_device(sc->sc_dev)) {
243 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
244 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
245 }
246 return "Sun unknown-part";
247 }
248 return "Unknown-vendor unknown-part";
249 }
250
251 static void
252 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
253 {
254 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE);
255 }
256
257 static int
258 ubsec_attach(device_t dev)
259 {
260 struct ubsec_softc *sc = device_get_softc(dev);
261 struct ubsec_dma *dmap;
262 u_int32_t cmd, i;
263 int rid;
264
265 bzero(sc, sizeof (*sc));
266 sc->sc_dev = dev;
267
268 SIMPLEQ_INIT(&sc->sc_queue);
269 SIMPLEQ_INIT(&sc->sc_qchip);
270 SIMPLEQ_INIT(&sc->sc_queue2);
271 SIMPLEQ_INIT(&sc->sc_qchip2);
272 SIMPLEQ_INIT(&sc->sc_q2free);
273
274 /* XXX handle power management */
275
276 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
277
278 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
279 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
280 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
281
282 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
283 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
284 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
285 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
286
287 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
288 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
289 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
290 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
291
292 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
293 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
295 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
296 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
297 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
298 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
299 /* NB: the 5821/5822 defines some additional status bits */
300 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
301 BS_STAT_MCR2_ALLEMPTY;
302 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
303 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
304 }
305
306 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
307 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
308 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
309 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
310
311 if (!(cmd & PCIM_CMD_MEMEN)) {
312 device_printf(dev, "failed to enable memory mapping\n");
313 goto bad;
314 }
315
316 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
317 device_printf(dev, "failed to enable bus mastering\n");
318 goto bad;
319 }
320
321 /*
322 * Setup memory-mapping of PCI registers.
323 */
324 rid = BS_BAR;
325 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
326 RF_ACTIVE);
327 if (sc->sc_sr == NULL) {
328 device_printf(dev, "cannot map register space\n");
329 goto bad;
330 }
331 sc->sc_st = rman_get_bustag(sc->sc_sr);
332 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
333
334 /*
335 * Arrange interrupt line.
336 */
337 rid = 0;
338 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
339 RF_SHAREABLE|RF_ACTIVE);
340 if (sc->sc_irq == NULL) {
341 device_printf(dev, "could not map interrupt\n");
342 goto bad1;
343 }
344 /*
345 * NB: Network code assumes we are blocked with splimp()
346 * so make sure the IRQ is mapped appropriately.
347 */
348 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
349 ubsec_intr, sc, &sc->sc_ih)) {
350 device_printf(dev, "could not establish interrupt\n");
351 goto bad2;
352 }
353
354 sc->sc_cid = crypto_get_driverid(0);
355 if (sc->sc_cid < 0) {
356 device_printf(dev, "could not get crypto driver id\n");
357 goto bad3;
358 }
359
360 /*
361 * Setup DMA descriptor area.
362 */
363 if (bus_dma_tag_create(NULL, /* parent */
364 1, 0, /* alignment, bounds */
365 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
366 BUS_SPACE_MAXADDR, /* highaddr */
367 NULL, NULL, /* filter, filterarg */
368 0x3ffff, /* maxsize */
369 UBS_MAX_SCATTER, /* nsegments */
370 0xffff, /* maxsegsize */
371 BUS_DMA_ALLOCNOW, /* flags */
372 NULL, NULL, /* lockfunc, lockarg */
373 &sc->sc_dmat)) {
374 device_printf(dev, "cannot allocate DMA tag\n");
375 goto bad4;
376 }
377 SIMPLEQ_INIT(&sc->sc_freequeue);
378 dmap = sc->sc_dmaa;
379 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
380 struct ubsec_q *q;
381
382 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
383 M_DEVBUF, M_NOWAIT);
384 if (q == NULL) {
385 device_printf(dev, "cannot allocate queue buffers\n");
386 break;
387 }
388
389 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
390 &dmap->d_alloc, 0)) {
391 device_printf(dev, "cannot allocate dma buffers\n");
392 free(q, M_DEVBUF);
393 break;
394 }
395 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
396
397 q->q_dma = dmap;
398 sc->sc_queuea[i] = q;
399
400 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
401 }
402 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
403 "mcr1 operations", MTX_DEF);
404 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
405 "mcr1 free q", MTX_DEF);
406
407 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
408
409 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
410 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
411 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
412 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
413 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
414 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
415 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
416 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
417
418 /*
419 * Reset Broadcom chip
420 */
421 ubsec_reset_board(sc);
422
423 /*
424 * Init Broadcom specific PCI settings
425 */
426 ubsec_init_pciregs(dev);
427
428 /*
429 * Init Broadcom chip
430 */
431 ubsec_init_board(sc);
432
433 #ifndef UBSEC_NO_RNG
434 if (sc->sc_flags & UBS_FLAGS_RNG) {
435 sc->sc_statmask |= BS_STAT_MCR2_DONE;
436 #ifdef UBSEC_RNDTEST
437 sc->sc_rndtest = rndtest_attach(dev);
438 if (sc->sc_rndtest)
439 sc->sc_harvest = rndtest_harvest;
440 else
441 sc->sc_harvest = default_harvest;
442 #else
443 sc->sc_harvest = default_harvest;
444 #endif
445
446 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
447 &sc->sc_rng.rng_q.q_mcr, 0))
448 goto skip_rng;
449
450 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
451 &sc->sc_rng.rng_q.q_ctx, 0)) {
452 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
453 goto skip_rng;
454 }
455
456 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
457 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
459 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
460 goto skip_rng;
461 }
462
463 if (hz >= 100)
464 sc->sc_rnghz = hz / 100;
465 else
466 sc->sc_rnghz = 1;
467 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
468 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
469 skip_rng:
470 ;
471 }
472 #endif /* UBSEC_NO_RNG */
473 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
474 "mcr2 operations", MTX_DEF);
475
476 if (sc->sc_flags & UBS_FLAGS_KEY) {
477 sc->sc_statmask |= BS_STAT_MCR2_DONE;
478
479 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0,
480 ubsec_kprocess, sc);
481 #if 0
482 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0,
483 ubsec_kprocess, sc);
484 #endif
485 }
486 return (0);
487 bad4:
488 crypto_unregister_all(sc->sc_cid);
489 bad3:
490 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
491 bad2:
492 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
493 bad1:
494 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
495 bad:
496 return (ENXIO);
497 }
498
499 /*
500 * Detach a device that successfully probed.
501 */
502 static int
503 ubsec_detach(device_t dev)
504 {
505 struct ubsec_softc *sc = device_get_softc(dev);
506
507 /* XXX wait/abort active ops */
508
509 /* disable interrupts */
510 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
511 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
512
513 callout_stop(&sc->sc_rngto);
514
515 crypto_unregister_all(sc->sc_cid);
516
517 #ifdef UBSEC_RNDTEST
518 if (sc->sc_rndtest)
519 rndtest_detach(sc->sc_rndtest);
520 #endif
521
522 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
523 struct ubsec_q *q;
524
525 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
526 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
527 ubsec_dma_free(sc, &q->q_dma->d_alloc);
528 free(q, M_DEVBUF);
529 }
530 mtx_destroy(&sc->sc_mcr1lock);
531 #ifndef UBSEC_NO_RNG
532 if (sc->sc_flags & UBS_FLAGS_RNG) {
533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
534 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
535 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
536 }
537 #endif /* UBSEC_NO_RNG */
538 mtx_destroy(&sc->sc_mcr2lock);
539
540 bus_generic_detach(dev);
541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
543
544 bus_dma_tag_destroy(sc->sc_dmat);
545 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
546
547 return (0);
548 }
549
550 /*
551 * Stop all chip i/o so that the kernel's probe routines don't
552 * get confused by errant DMAs when rebooting.
553 */
554 static void
555 ubsec_shutdown(device_t dev)
556 {
557 #ifdef notyet
558 ubsec_stop(device_get_softc(dev));
559 #endif
560 }
561
562 /*
563 * Device suspend routine.
564 */
565 static int
566 ubsec_suspend(device_t dev)
567 {
568 struct ubsec_softc *sc = device_get_softc(dev);
569
570 #ifdef notyet
571 /* XXX stop the device and save PCI settings */
572 #endif
573 sc->sc_suspended = 1;
574
575 return (0);
576 }
577
578 static int
579 ubsec_resume(device_t dev)
580 {
581 struct ubsec_softc *sc = device_get_softc(dev);
582
583 #ifdef notyet
584 /* XXX retore PCI settings and start the device */
585 #endif
586 sc->sc_suspended = 0;
587 return (0);
588 }
589
590 /*
591 * UBSEC Interrupt routine
592 */
593 static void
594 ubsec_intr(void *arg)
595 {
596 struct ubsec_softc *sc = arg;
597 volatile u_int32_t stat;
598 struct ubsec_q *q;
599 struct ubsec_dma *dmap;
600 int npkts = 0, i;
601
602 stat = READ_REG(sc, BS_STAT);
603 stat &= sc->sc_statmask;
604 if (stat == 0)
605 return;
606
607 WRITE_REG(sc, BS_STAT, stat); /* IACK */
608
609 /*
610 * Check to see if we have any packets waiting for us
611 */
612 if ((stat & BS_STAT_MCR1_DONE)) {
613 mtx_lock(&sc->sc_mcr1lock);
614 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
615 q = SIMPLEQ_FIRST(&sc->sc_qchip);
616 dmap = q->q_dma;
617
618 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
619 break;
620
621 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
622
623 npkts = q->q_nstacked_mcrs;
624 sc->sc_nqchip -= 1+npkts;
625 /*
626 * search for further sc_qchip ubsec_q's that share
627 * the same MCR, and complete them too, they must be
628 * at the top.
629 */
630 for (i = 0; i < npkts; i++) {
631 if(q->q_stacked_mcr[i]) {
632 ubsec_callback(sc, q->q_stacked_mcr[i]);
633 } else {
634 break;
635 }
636 }
637 ubsec_callback(sc, q);
638 }
639 /*
640 * Don't send any more packet to chip if there has been
641 * a DMAERR.
642 */
643 if (!(stat & BS_STAT_DMAERR))
644 ubsec_feed(sc);
645 mtx_unlock(&sc->sc_mcr1lock);
646 }
647
648 /*
649 * Check to see if we have any key setups/rng's waiting for us
650 */
651 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
652 (stat & BS_STAT_MCR2_DONE)) {
653 struct ubsec_q2 *q2;
654 struct ubsec_mcr *mcr;
655
656 mtx_lock(&sc->sc_mcr2lock);
657 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
658 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
659
660 ubsec_dma_sync(&q2->q_mcr,
661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
662
663 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
664 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
665 ubsec_dma_sync(&q2->q_mcr,
666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
667 break;
668 }
669 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next);
670 ubsec_callback2(sc, q2);
671 /*
672 * Don't send any more packet to chip if there has been
673 * a DMAERR.
674 */
675 if (!(stat & BS_STAT_DMAERR))
676 ubsec_feed2(sc);
677 }
678 mtx_unlock(&sc->sc_mcr2lock);
679 }
680
681 /*
682 * Check to see if we got any DMA Error
683 */
684 if (stat & BS_STAT_DMAERR) {
685 #ifdef UBSEC_DEBUG
686 if (ubsec_debug) {
687 volatile u_int32_t a = READ_REG(sc, BS_ERR);
688
689 printf("dmaerr %s@%08x\n",
690 (a & BS_ERR_READ) ? "read" : "write",
691 a & BS_ERR_ADDR);
692 }
693 #endif /* UBSEC_DEBUG */
694 ubsecstats.hst_dmaerr++;
695 mtx_lock(&sc->sc_mcr1lock);
696 ubsec_totalreset(sc);
697 ubsec_feed(sc);
698 mtx_unlock(&sc->sc_mcr1lock);
699 }
700
701 if (sc->sc_needwakeup) { /* XXX check high watermark */
702 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
703 #ifdef UBSEC_DEBUG
704 if (ubsec_debug)
705 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
706 sc->sc_needwakeup);
707 #endif /* UBSEC_DEBUG */
708 sc->sc_needwakeup &= ~wakeup;
709 crypto_unblock(sc->sc_cid, wakeup);
710 }
711 }
712
713 /*
714 * ubsec_feed() - aggregate and post requests to chip
715 */
716 static void
717 ubsec_feed(struct ubsec_softc *sc)
718 {
719 struct ubsec_q *q, *q2;
720 int npkts, i;
721 void *v;
722 u_int32_t stat;
723
724 /*
725 * Decide how many ops to combine in a single MCR. We cannot
726 * aggregate more than UBS_MAX_AGGR because this is the number
727 * of slots defined in the data structure. Note that
728 * aggregation only happens if ops are marked batch'able.
729 * Aggregating ops reduces the number of interrupts to the host
730 * but also (potentially) increases the latency for processing
731 * completed ops as we only get an interrupt when all aggregated
732 * ops have completed.
733 */
734 if (sc->sc_nqueue == 0)
735 return;
736 if (sc->sc_nqueue > 1) {
737 npkts = 0;
738 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
739 npkts++;
740 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
741 break;
742 }
743 } else
744 npkts = 1;
745 /*
746 * Check device status before going any further.
747 */
748 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
749 if (stat & BS_STAT_DMAERR) {
750 ubsec_totalreset(sc);
751 ubsecstats.hst_dmaerr++;
752 } else
753 ubsecstats.hst_mcr1full++;
754 return;
755 }
756 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
757 ubsecstats.hst_maxqueue = sc->sc_nqueue;
758 if (npkts > UBS_MAX_AGGR)
759 npkts = UBS_MAX_AGGR;
760 if (npkts < 2) /* special case 1 op */
761 goto feed1;
762
763 ubsecstats.hst_totbatch += npkts-1;
764 #ifdef UBSEC_DEBUG
765 if (ubsec_debug)
766 printf("merging %d records\n", npkts);
767 #endif /* UBSEC_DEBUG */
768
769 q = SIMPLEQ_FIRST(&sc->sc_queue);
770 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
771 --sc->sc_nqueue;
772
773 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
774 if (q->q_dst_map != NULL)
775 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
776
777 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
778
779 for (i = 0; i < q->q_nstacked_mcrs; i++) {
780 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
781 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
782 BUS_DMASYNC_PREWRITE);
783 if (q2->q_dst_map != NULL)
784 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
785 BUS_DMASYNC_PREREAD);
786 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next);
787 --sc->sc_nqueue;
788
789 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
790 sizeof(struct ubsec_mcr_add));
791 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
792 q->q_stacked_mcr[i] = q2;
793 }
794 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
795 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
796 sc->sc_nqchip += npkts;
797 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
798 ubsecstats.hst_maxqchip = sc->sc_nqchip;
799 ubsec_dma_sync(&q->q_dma->d_alloc,
800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
801 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
802 offsetof(struct ubsec_dmachunk, d_mcr));
803 return;
804 feed1:
805 q = SIMPLEQ_FIRST(&sc->sc_queue);
806
807 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
808 if (q->q_dst_map != NULL)
809 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
810 ubsec_dma_sync(&q->q_dma->d_alloc,
811 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
812
813 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
814 offsetof(struct ubsec_dmachunk, d_mcr));
815 #ifdef UBSEC_DEBUG
816 if (ubsec_debug)
817 printf("feed1: q->chip %p %08x stat %08x\n",
818 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
819 stat);
820 #endif /* UBSEC_DEBUG */
821 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
822 --sc->sc_nqueue;
823 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
824 sc->sc_nqchip++;
825 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
826 ubsecstats.hst_maxqchip = sc->sc_nqchip;
827 return;
828 }
829
830 /*
831 * Allocate a new 'session' and return an encoded session id. 'sidp'
832 * contains our registration id, and should contain an encoded session
833 * id on successful allocation.
834 */
835 static int
836 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
837 {
838 struct cryptoini *c, *encini = NULL, *macini = NULL;
839 struct ubsec_softc *sc = arg;
840 struct ubsec_session *ses = NULL;
841 MD5_CTX md5ctx;
842 SHA1_CTX sha1ctx;
843 int i, sesn;
844
845 if (sidp == NULL || cri == NULL || sc == NULL)
846 return (EINVAL);
847
848 for (c = cri; c != NULL; c = c->cri_next) {
849 if (c->cri_alg == CRYPTO_MD5_HMAC ||
850 c->cri_alg == CRYPTO_SHA1_HMAC) {
851 if (macini)
852 return (EINVAL);
853 macini = c;
854 } else if (c->cri_alg == CRYPTO_DES_CBC ||
855 c->cri_alg == CRYPTO_3DES_CBC) {
856 if (encini)
857 return (EINVAL);
858 encini = c;
859 } else
860 return (EINVAL);
861 }
862 if (encini == NULL && macini == NULL)
863 return (EINVAL);
864
865 if (sc->sc_sessions == NULL) {
866 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
867 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
868 if (ses == NULL)
869 return (ENOMEM);
870 sesn = 0;
871 sc->sc_nsessions = 1;
872 } else {
873 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
874 if (sc->sc_sessions[sesn].ses_used == 0) {
875 ses = &sc->sc_sessions[sesn];
876 break;
877 }
878 }
879
880 if (ses == NULL) {
881 sesn = sc->sc_nsessions;
882 ses = (struct ubsec_session *)malloc((sesn + 1) *
883 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
884 if (ses == NULL)
885 return (ENOMEM);
886 bcopy(sc->sc_sessions, ses, sesn *
887 sizeof(struct ubsec_session));
888 bzero(sc->sc_sessions, sesn *
889 sizeof(struct ubsec_session));
890 free(sc->sc_sessions, M_DEVBUF);
891 sc->sc_sessions = ses;
892 ses = &sc->sc_sessions[sesn];
893 sc->sc_nsessions++;
894 }
895 }
896 bzero(ses, sizeof(struct ubsec_session));
897 ses->ses_used = 1;
898
899 if (encini) {
900 /* get an IV, network byte order */
901 /* XXX may read fewer than requested */
902 read_random(ses->ses_iv, sizeof(ses->ses_iv));
903
904 /* Go ahead and compute key in ubsec's byte order */
905 if (encini->cri_alg == CRYPTO_DES_CBC) {
906 bcopy(encini->cri_key, &ses->ses_deskey[0], 8);
907 bcopy(encini->cri_key, &ses->ses_deskey[2], 8);
908 bcopy(encini->cri_key, &ses->ses_deskey[4], 8);
909 } else
910 bcopy(encini->cri_key, ses->ses_deskey, 24);
911
912 SWAP32(ses->ses_deskey[0]);
913 SWAP32(ses->ses_deskey[1]);
914 SWAP32(ses->ses_deskey[2]);
915 SWAP32(ses->ses_deskey[3]);
916 SWAP32(ses->ses_deskey[4]);
917 SWAP32(ses->ses_deskey[5]);
918 }
919
920 if (macini) {
921 for (i = 0; i < macini->cri_klen / 8; i++)
922 macini->cri_key[i] ^= HMAC_IPAD_VAL;
923
924 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
925 MD5Init(&md5ctx);
926 MD5Update(&md5ctx, macini->cri_key,
927 macini->cri_klen / 8);
928 MD5Update(&md5ctx, hmac_ipad_buffer,
929 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
930 bcopy(md5ctx.state, ses->ses_hminner,
931 sizeof(md5ctx.state));
932 } else {
933 SHA1Init(&sha1ctx);
934 SHA1Update(&sha1ctx, macini->cri_key,
935 macini->cri_klen / 8);
936 SHA1Update(&sha1ctx, hmac_ipad_buffer,
937 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
938 bcopy(sha1ctx.h.b32, ses->ses_hminner,
939 sizeof(sha1ctx.h.b32));
940 }
941
942 for (i = 0; i < macini->cri_klen / 8; i++)
943 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
944
945 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
946 MD5Init(&md5ctx);
947 MD5Update(&md5ctx, macini->cri_key,
948 macini->cri_klen / 8);
949 MD5Update(&md5ctx, hmac_opad_buffer,
950 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
951 bcopy(md5ctx.state, ses->ses_hmouter,
952 sizeof(md5ctx.state));
953 } else {
954 SHA1Init(&sha1ctx);
955 SHA1Update(&sha1ctx, macini->cri_key,
956 macini->cri_klen / 8);
957 SHA1Update(&sha1ctx, hmac_opad_buffer,
958 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
959 bcopy(sha1ctx.h.b32, ses->ses_hmouter,
960 sizeof(sha1ctx.h.b32));
961 }
962
963 for (i = 0; i < macini->cri_klen / 8; i++)
964 macini->cri_key[i] ^= HMAC_OPAD_VAL;
965 }
966
967 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
968 return (0);
969 }
970
971 /*
972 * Deallocate a session.
973 */
974 static int
975 ubsec_freesession(void *arg, u_int64_t tid)
976 {
977 struct ubsec_softc *sc = arg;
978 int session, ret;
979 u_int32_t sid = CRYPTO_SESID2LID(tid);
980
981 if (sc == NULL)
982 return (EINVAL);
983
984 session = UBSEC_SESSION(sid);
985 if (session < sc->sc_nsessions) {
986 bzero(&sc->sc_sessions[session],
987 sizeof(sc->sc_sessions[session]));
988 ret = 0;
989 } else
990 ret = EINVAL;
991
992 return (ret);
993 }
994
995 static void
996 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
997 {
998 struct ubsec_operand *op = arg;
999
1000 KASSERT(nsegs <= UBS_MAX_SCATTER,
1001 ("Too many DMA segments returned when mapping operand"));
1002 #ifdef UBSEC_DEBUG
1003 if (ubsec_debug)
1004 printf("ubsec_op_cb: mapsize %u nsegs %d\n",
1005 (u_int) mapsize, nsegs);
1006 #endif
1007 op->mapsize = mapsize;
1008 op->nsegs = nsegs;
1009 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1010 }
1011
1012 static int
1013 ubsec_process(void *arg, struct cryptop *crp, int hint)
1014 {
1015 struct ubsec_q *q = NULL;
1016 int err = 0, i, j, nicealign;
1017 struct ubsec_softc *sc = arg;
1018 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1019 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1020 int sskip, dskip, stheend, dtheend;
1021 int16_t coffset;
1022 struct ubsec_session *ses;
1023 struct ubsec_pktctx ctx;
1024 struct ubsec_dma *dmap = NULL;
1025
1026 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1027 ubsecstats.hst_invalid++;
1028 return (EINVAL);
1029 }
1030 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1031 ubsecstats.hst_badsession++;
1032 return (EINVAL);
1033 }
1034
1035 mtx_lock(&sc->sc_freeqlock);
1036 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1037 ubsecstats.hst_queuefull++;
1038 sc->sc_needwakeup |= CRYPTO_SYMQ;
1039 mtx_unlock(&sc->sc_freeqlock);
1040 return (ERESTART);
1041 }
1042 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1043 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
1044 mtx_unlock(&sc->sc_freeqlock);
1045
1046 dmap = q->q_dma; /* Save dma pointer */
1047 bzero(q, sizeof(struct ubsec_q));
1048 bzero(&ctx, sizeof(ctx));
1049
1050 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1051 q->q_dma = dmap;
1052 ses = &sc->sc_sessions[q->q_sesn];
1053
1054 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1055 q->q_src_m = (struct mbuf *)crp->crp_buf;
1056 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1057 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1058 q->q_src_io = (struct uio *)crp->crp_buf;
1059 q->q_dst_io = (struct uio *)crp->crp_buf;
1060 } else {
1061 ubsecstats.hst_badflags++;
1062 err = EINVAL;
1063 goto errout; /* XXX we don't handle contiguous blocks! */
1064 }
1065
1066 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1067
1068 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1069 dmap->d_dma->d_mcr.mcr_flags = 0;
1070 q->q_crp = crp;
1071
1072 crd1 = crp->crp_desc;
1073 if (crd1 == NULL) {
1074 ubsecstats.hst_nodesc++;
1075 err = EINVAL;
1076 goto errout;
1077 }
1078 crd2 = crd1->crd_next;
1079
1080 if (crd2 == NULL) {
1081 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1082 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1083 maccrd = crd1;
1084 enccrd = NULL;
1085 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1086 crd1->crd_alg == CRYPTO_3DES_CBC) {
1087 maccrd = NULL;
1088 enccrd = crd1;
1089 } else {
1090 ubsecstats.hst_badalg++;
1091 err = EINVAL;
1092 goto errout;
1093 }
1094 } else {
1095 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1096 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1097 (crd2->crd_alg == CRYPTO_DES_CBC ||
1098 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1099 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1100 maccrd = crd1;
1101 enccrd = crd2;
1102 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1103 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1104 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1105 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1106 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1107 enccrd = crd1;
1108 maccrd = crd2;
1109 } else {
1110 /*
1111 * We cannot order the ubsec as requested
1112 */
1113 ubsecstats.hst_badalg++;
1114 err = EINVAL;
1115 goto errout;
1116 }
1117 }
1118
1119 if (enccrd) {
1120 encoffset = enccrd->crd_skip;
1121 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1122
1123 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1124 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1125
1126 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1127 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1128 else {
1129 ctx.pc_iv[0] = ses->ses_iv[0];
1130 ctx.pc_iv[1] = ses->ses_iv[1];
1131 }
1132
1133 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1134 if (crp->crp_flags & CRYPTO_F_IMBUF)
1135 m_copyback(q->q_src_m,
1136 enccrd->crd_inject,
1137 8, (caddr_t)ctx.pc_iv);
1138 else if (crp->crp_flags & CRYPTO_F_IOV)
1139 cuio_copyback(q->q_src_io,
1140 enccrd->crd_inject,
1141 8, (caddr_t)ctx.pc_iv);
1142 }
1143 } else {
1144 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1145
1146 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1147 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1148 else if (crp->crp_flags & CRYPTO_F_IMBUF)
1149 m_copydata(q->q_src_m, enccrd->crd_inject,
1150 8, (caddr_t)ctx.pc_iv);
1151 else if (crp->crp_flags & CRYPTO_F_IOV)
1152 cuio_copydata(q->q_src_io,
1153 enccrd->crd_inject, 8,
1154 (caddr_t)ctx.pc_iv);
1155 }
1156
1157 ctx.pc_deskey[0] = ses->ses_deskey[0];
1158 ctx.pc_deskey[1] = ses->ses_deskey[1];
1159 ctx.pc_deskey[2] = ses->ses_deskey[2];
1160 ctx.pc_deskey[3] = ses->ses_deskey[3];
1161 ctx.pc_deskey[4] = ses->ses_deskey[4];
1162 ctx.pc_deskey[5] = ses->ses_deskey[5];
1163 SWAP32(ctx.pc_iv[0]);
1164 SWAP32(ctx.pc_iv[1]);
1165 }
1166
1167 if (maccrd) {
1168 macoffset = maccrd->crd_skip;
1169
1170 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1171 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1172 else
1173 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1174
1175 for (i = 0; i < 5; i++) {
1176 ctx.pc_hminner[i] = ses->ses_hminner[i];
1177 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1178
1179 HTOLE32(ctx.pc_hminner[i]);
1180 HTOLE32(ctx.pc_hmouter[i]);
1181 }
1182 }
1183
1184 if (enccrd && maccrd) {
1185 /*
1186 * ubsec cannot handle packets where the end of encryption
1187 * and authentication are not the same, or where the
1188 * encrypted part begins before the authenticated part.
1189 */
1190 if ((encoffset + enccrd->crd_len) !=
1191 (macoffset + maccrd->crd_len)) {
1192 ubsecstats.hst_lenmismatch++;
1193 err = EINVAL;
1194 goto errout;
1195 }
1196 if (enccrd->crd_skip < maccrd->crd_skip) {
1197 ubsecstats.hst_skipmismatch++;
1198 err = EINVAL;
1199 goto errout;
1200 }
1201 sskip = maccrd->crd_skip;
1202 cpskip = dskip = enccrd->crd_skip;
1203 stheend = maccrd->crd_len;
1204 dtheend = enccrd->crd_len;
1205 coffset = enccrd->crd_skip - maccrd->crd_skip;
1206 cpoffset = cpskip + dtheend;
1207 #ifdef UBSEC_DEBUG
1208 if (ubsec_debug) {
1209 printf("mac: skip %d, len %d, inject %d\n",
1210 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1211 printf("enc: skip %d, len %d, inject %d\n",
1212 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1213 printf("src: skip %d, len %d\n", sskip, stheend);
1214 printf("dst: skip %d, len %d\n", dskip, dtheend);
1215 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1216 coffset, stheend, cpskip, cpoffset);
1217 }
1218 #endif
1219 } else {
1220 cpskip = dskip = sskip = macoffset + encoffset;
1221 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1222 cpoffset = cpskip + dtheend;
1223 coffset = 0;
1224 }
1225 ctx.pc_offset = htole16(coffset >> 2);
1226
1227 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1228 ubsecstats.hst_nomap++;
1229 err = ENOMEM;
1230 goto errout;
1231 }
1232 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1233 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1234 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1235 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1236 q->q_src_map = NULL;
1237 ubsecstats.hst_noload++;
1238 err = ENOMEM;
1239 goto errout;
1240 }
1241 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1242 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1243 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1244 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1245 q->q_src_map = NULL;
1246 ubsecstats.hst_noload++;
1247 err = ENOMEM;
1248 goto errout;
1249 }
1250 }
1251 nicealign = ubsec_dmamap_aligned(&q->q_src);
1252
1253 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1254
1255 #ifdef UBSEC_DEBUG
1256 if (ubsec_debug)
1257 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1258 #endif
1259 for (i = j = 0; i < q->q_src_nsegs; i++) {
1260 struct ubsec_pktbuf *pb;
1261 bus_size_t packl = q->q_src_segs[i].ds_len;
1262 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1263
1264 if (sskip >= packl) {
1265 sskip -= packl;
1266 continue;
1267 }
1268
1269 packl -= sskip;
1270 packp += sskip;
1271 sskip = 0;
1272
1273 if (packl > 0xfffc) {
1274 err = EIO;
1275 goto errout;
1276 }
1277
1278 if (j == 0)
1279 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1280 else
1281 pb = &dmap->d_dma->d_sbuf[j - 1];
1282
1283 pb->pb_addr = htole32(packp);
1284
1285 if (stheend) {
1286 if (packl > stheend) {
1287 pb->pb_len = htole32(stheend);
1288 stheend = 0;
1289 } else {
1290 pb->pb_len = htole32(packl);
1291 stheend -= packl;
1292 }
1293 } else
1294 pb->pb_len = htole32(packl);
1295
1296 if ((i + 1) == q->q_src_nsegs)
1297 pb->pb_next = 0;
1298 else
1299 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1300 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1301 j++;
1302 }
1303
1304 if (enccrd == NULL && maccrd != NULL) {
1305 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1306 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1307 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1308 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1309 #ifdef UBSEC_DEBUG
1310 if (ubsec_debug)
1311 printf("opkt: %x %x %x\n",
1312 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1313 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1314 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1315 #endif
1316 } else {
1317 if (crp->crp_flags & CRYPTO_F_IOV) {
1318 if (!nicealign) {
1319 ubsecstats.hst_iovmisaligned++;
1320 err = EINVAL;
1321 goto errout;
1322 }
1323 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1324 &q->q_dst_map)) {
1325 ubsecstats.hst_nomap++;
1326 err = ENOMEM;
1327 goto errout;
1328 }
1329 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1330 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1331 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1332 q->q_dst_map = NULL;
1333 ubsecstats.hst_noload++;
1334 err = ENOMEM;
1335 goto errout;
1336 }
1337 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1338 if (nicealign) {
1339 q->q_dst = q->q_src;
1340 } else {
1341 int totlen, len;
1342 struct mbuf *m, *top, **mp;
1343
1344 ubsecstats.hst_unaligned++;
1345 totlen = q->q_src_mapsize;
1346 if (q->q_src_m->m_flags & M_PKTHDR) {
1347 len = MHLEN;
1348 MGETHDR(m, M_DONTWAIT, MT_DATA);
1349 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) {
1350 m_free(m);
1351 m = NULL;
1352 }
1353 } else {
1354 len = MLEN;
1355 MGET(m, M_DONTWAIT, MT_DATA);
1356 }
1357 if (m == NULL) {
1358 ubsecstats.hst_nombuf++;
1359 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1360 goto errout;
1361 }
1362 if (totlen >= MINCLSIZE) {
1363 MCLGET(m, M_DONTWAIT);
1364 if ((m->m_flags & M_EXT) == 0) {
1365 m_free(m);
1366 ubsecstats.hst_nomcl++;
1367 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1368 goto errout;
1369 }
1370 len = MCLBYTES;
1371 }
1372 m->m_len = len;
1373 top = NULL;
1374 mp = ⊤
1375
1376 while (totlen > 0) {
1377 if (top) {
1378 MGET(m, M_DONTWAIT, MT_DATA);
1379 if (m == NULL) {
1380 m_freem(top);
1381 ubsecstats.hst_nombuf++;
1382 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1383 goto errout;
1384 }
1385 len = MLEN;
1386 }
1387 if (top && totlen >= MINCLSIZE) {
1388 MCLGET(m, M_DONTWAIT);
1389 if ((m->m_flags & M_EXT) == 0) {
1390 *mp = m;
1391 m_freem(top);
1392 ubsecstats.hst_nomcl++;
1393 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1394 goto errout;
1395 }
1396 len = MCLBYTES;
1397 }
1398 m->m_len = len = min(totlen, len);
1399 totlen -= len;
1400 *mp = m;
1401 mp = &m->m_next;
1402 }
1403 q->q_dst_m = top;
1404 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1405 cpskip, cpoffset);
1406 if (bus_dmamap_create(sc->sc_dmat,
1407 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1408 ubsecstats.hst_nomap++;
1409 err = ENOMEM;
1410 goto errout;
1411 }
1412 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1413 q->q_dst_map, q->q_dst_m,
1414 ubsec_op_cb, &q->q_dst,
1415 BUS_DMA_NOWAIT) != 0) {
1416 bus_dmamap_destroy(sc->sc_dmat,
1417 q->q_dst_map);
1418 q->q_dst_map = NULL;
1419 ubsecstats.hst_noload++;
1420 err = ENOMEM;
1421 goto errout;
1422 }
1423 }
1424 } else {
1425 ubsecstats.hst_badflags++;
1426 err = EINVAL;
1427 goto errout;
1428 }
1429
1430 #ifdef UBSEC_DEBUG
1431 if (ubsec_debug)
1432 printf("dst skip: %d\n", dskip);
1433 #endif
1434 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1435 struct ubsec_pktbuf *pb;
1436 bus_size_t packl = q->q_dst_segs[i].ds_len;
1437 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1438
1439 if (dskip >= packl) {
1440 dskip -= packl;
1441 continue;
1442 }
1443
1444 packl -= dskip;
1445 packp += dskip;
1446 dskip = 0;
1447
1448 if (packl > 0xfffc) {
1449 err = EIO;
1450 goto errout;
1451 }
1452
1453 if (j == 0)
1454 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1455 else
1456 pb = &dmap->d_dma->d_dbuf[j - 1];
1457
1458 pb->pb_addr = htole32(packp);
1459
1460 if (dtheend) {
1461 if (packl > dtheend) {
1462 pb->pb_len = htole32(dtheend);
1463 dtheend = 0;
1464 } else {
1465 pb->pb_len = htole32(packl);
1466 dtheend -= packl;
1467 }
1468 } else
1469 pb->pb_len = htole32(packl);
1470
1471 if ((i + 1) == q->q_dst_nsegs) {
1472 if (maccrd)
1473 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1474 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1475 else
1476 pb->pb_next = 0;
1477 } else
1478 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1479 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1480 j++;
1481 }
1482 }
1483
1484 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1485 offsetof(struct ubsec_dmachunk, d_ctx));
1486
1487 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1488 struct ubsec_pktctx_long *ctxl;
1489
1490 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1491 offsetof(struct ubsec_dmachunk, d_ctx));
1492
1493 /* transform small context into long context */
1494 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1495 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1496 ctxl->pc_flags = ctx.pc_flags;
1497 ctxl->pc_offset = ctx.pc_offset;
1498 for (i = 0; i < 6; i++)
1499 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1500 for (i = 0; i < 5; i++)
1501 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1502 for (i = 0; i < 5; i++)
1503 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1504 ctxl->pc_iv[0] = ctx.pc_iv[0];
1505 ctxl->pc_iv[1] = ctx.pc_iv[1];
1506 } else
1507 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1508 offsetof(struct ubsec_dmachunk, d_ctx),
1509 sizeof(struct ubsec_pktctx));
1510
1511 mtx_lock(&sc->sc_mcr1lock);
1512 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1513 sc->sc_nqueue++;
1514 ubsecstats.hst_ipackets++;
1515 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1516 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1517 ubsec_feed(sc);
1518 mtx_unlock(&sc->sc_mcr1lock);
1519 return (0);
1520
1521 errout:
1522 if (q != NULL) {
1523 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1524 m_freem(q->q_dst_m);
1525
1526 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1527 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1528 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1529 }
1530 if (q->q_src_map != NULL) {
1531 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1532 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1533 }
1534
1535 mtx_lock(&sc->sc_freeqlock);
1536 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1537 mtx_unlock(&sc->sc_freeqlock);
1538 }
1539 if (err != ERESTART) {
1540 crp->crp_etype = err;
1541 crypto_done(crp);
1542 } else {
1543 sc->sc_needwakeup |= CRYPTO_SYMQ;
1544 }
1545 return (err);
1546 }
1547
1548 static void
1549 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1550 {
1551 struct cryptop *crp = (struct cryptop *)q->q_crp;
1552 struct cryptodesc *crd;
1553 struct ubsec_dma *dmap = q->q_dma;
1554
1555 ubsecstats.hst_opackets++;
1556 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1557
1558 ubsec_dma_sync(&dmap->d_alloc,
1559 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1560 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1561 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1562 BUS_DMASYNC_POSTREAD);
1563 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1564 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1565 }
1566 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1567 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1568 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1569
1570 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1571 m_freem(q->q_src_m);
1572 crp->crp_buf = (caddr_t)q->q_dst_m;
1573 }
1574 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len;
1575
1576 /* copy out IV for future use */
1577 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1578 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1579 if (crd->crd_alg != CRYPTO_DES_CBC &&
1580 crd->crd_alg != CRYPTO_3DES_CBC)
1581 continue;
1582 if (crp->crp_flags & CRYPTO_F_IMBUF)
1583 m_copydata((struct mbuf *)crp->crp_buf,
1584 crd->crd_skip + crd->crd_len - 8, 8,
1585 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1586 else if (crp->crp_flags & CRYPTO_F_IOV) {
1587 cuio_copydata((struct uio *)crp->crp_buf,
1588 crd->crd_skip + crd->crd_len - 8, 8,
1589 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1590 }
1591 break;
1592 }
1593 }
1594
1595 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1596 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1597 crd->crd_alg != CRYPTO_SHA1_HMAC)
1598 continue;
1599 if (crp->crp_flags & CRYPTO_F_IMBUF)
1600 m_copyback((struct mbuf *)crp->crp_buf,
1601 crd->crd_inject, 12,
1602 (caddr_t)dmap->d_dma->d_macbuf);
1603 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1604 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1605 crp->crp_mac, 12);
1606 break;
1607 }
1608 mtx_lock(&sc->sc_freeqlock);
1609 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1610 mtx_unlock(&sc->sc_freeqlock);
1611 crypto_done(crp);
1612 }
1613
1614 static void
1615 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1616 {
1617 int i, j, dlen, slen;
1618 caddr_t dptr, sptr;
1619
1620 j = 0;
1621 sptr = srcm->m_data;
1622 slen = srcm->m_len;
1623 dptr = dstm->m_data;
1624 dlen = dstm->m_len;
1625
1626 while (1) {
1627 for (i = 0; i < min(slen, dlen); i++) {
1628 if (j < hoffset || j >= toffset)
1629 *dptr++ = *sptr++;
1630 slen--;
1631 dlen--;
1632 j++;
1633 }
1634 if (slen == 0) {
1635 srcm = srcm->m_next;
1636 if (srcm == NULL)
1637 return;
1638 sptr = srcm->m_data;
1639 slen = srcm->m_len;
1640 }
1641 if (dlen == 0) {
1642 dstm = dstm->m_next;
1643 if (dstm == NULL)
1644 return;
1645 dptr = dstm->m_data;
1646 dlen = dstm->m_len;
1647 }
1648 }
1649 }
1650
1651 /*
1652 * feed the key generator, must be called at splimp() or higher.
1653 */
1654 static int
1655 ubsec_feed2(struct ubsec_softc *sc)
1656 {
1657 struct ubsec_q2 *q;
1658
1659 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1660 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1661 break;
1662 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1663
1664 ubsec_dma_sync(&q->q_mcr,
1665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1666 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1667
1668 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1669 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next);
1670 --sc->sc_nqueue2;
1671 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1672 }
1673 return (0);
1674 }
1675
1676 /*
1677 * Callback for handling random numbers
1678 */
1679 static void
1680 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1681 {
1682 struct cryptkop *krp;
1683 struct ubsec_ctx_keyop *ctx;
1684
1685 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1686 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1687
1688 switch (q->q_type) {
1689 #ifndef UBSEC_NO_RNG
1690 case UBS_CTXOP_RNGBYPASS: {
1691 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1692
1693 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1694 (*sc->sc_harvest)(sc->sc_rndtest,
1695 rng->rng_buf.dma_vaddr,
1696 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1697 rng->rng_used = 0;
1698 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1699 break;
1700 }
1701 #endif
1702 case UBS_CTXOP_MODEXP: {
1703 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1704 u_int rlen, clen;
1705
1706 krp = me->me_krp;
1707 rlen = (me->me_modbits + 7) / 8;
1708 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1709
1710 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1711 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1712 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1713 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1714
1715 if (clen < rlen)
1716 krp->krp_status = E2BIG;
1717 else {
1718 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1719 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1720 (krp->krp_param[krp->krp_iparams].crp_nbits
1721 + 7) / 8);
1722 bcopy(me->me_C.dma_vaddr,
1723 krp->krp_param[krp->krp_iparams].crp_p,
1724 (me->me_modbits + 7) / 8);
1725 } else
1726 ubsec_kshift_l(me->me_shiftbits,
1727 me->me_C.dma_vaddr, me->me_normbits,
1728 krp->krp_param[krp->krp_iparams].crp_p,
1729 krp->krp_param[krp->krp_iparams].crp_nbits);
1730 }
1731
1732 crypto_kdone(krp);
1733
1734 /* bzero all potentially sensitive data */
1735 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1736 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1737 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1738 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1739
1740 /* Can't free here, so put us on the free list. */
1741 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1742 break;
1743 }
1744 case UBS_CTXOP_RSAPRIV: {
1745 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1746 u_int len;
1747
1748 krp = rp->rpr_krp;
1749 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1750 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1751
1752 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1753 bcopy(rp->rpr_msgout.dma_vaddr,
1754 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1755
1756 crypto_kdone(krp);
1757
1758 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1759 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1760 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1761
1762 /* Can't free here, so put us on the free list. */
1763 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1764 break;
1765 }
1766 default:
1767 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1768 letoh16(ctx->ctx_op));
1769 break;
1770 }
1771 }
1772
1773 #ifndef UBSEC_NO_RNG
1774 static void
1775 ubsec_rng(void *vsc)
1776 {
1777 struct ubsec_softc *sc = vsc;
1778 struct ubsec_q2_rng *rng = &sc->sc_rng;
1779 struct ubsec_mcr *mcr;
1780 struct ubsec_ctx_rngbypass *ctx;
1781
1782 mtx_lock(&sc->sc_mcr2lock);
1783 if (rng->rng_used) {
1784 mtx_unlock(&sc->sc_mcr2lock);
1785 return;
1786 }
1787 sc->sc_nqueue2++;
1788 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1789 goto out;
1790
1791 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1792 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1793
1794 mcr->mcr_pkts = htole16(1);
1795 mcr->mcr_flags = 0;
1796 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1797 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1798 mcr->mcr_ipktbuf.pb_len = 0;
1799 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1800 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1801 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1802 UBS_PKTBUF_LEN);
1803 mcr->mcr_opktbuf.pb_next = 0;
1804
1805 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1806 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1807 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1808
1809 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1810
1811 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1812 rng->rng_used = 1;
1813 ubsec_feed2(sc);
1814 ubsecstats.hst_rng++;
1815 mtx_unlock(&sc->sc_mcr2lock);
1816
1817 return;
1818
1819 out:
1820 /*
1821 * Something weird happened, generate our own call back.
1822 */
1823 sc->sc_nqueue2--;
1824 mtx_unlock(&sc->sc_mcr2lock);
1825 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1826 }
1827 #endif /* UBSEC_NO_RNG */
1828
1829 static void
1830 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1831 {
1832 bus_addr_t *paddr = (bus_addr_t*) arg;
1833 *paddr = segs->ds_addr;
1834 }
1835
1836 static int
1837 ubsec_dma_malloc(
1838 struct ubsec_softc *sc,
1839 bus_size_t size,
1840 struct ubsec_dma_alloc *dma,
1841 int mapflags
1842 )
1843 {
1844 int r;
1845
1846 /* XXX could specify sc_dmat as parent but that just adds overhead */
1847 r = bus_dma_tag_create(NULL, /* parent */
1848 1, 0, /* alignment, bounds */
1849 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1850 BUS_SPACE_MAXADDR, /* highaddr */
1851 NULL, NULL, /* filter, filterarg */
1852 size, /* maxsize */
1853 1, /* nsegments */
1854 size, /* maxsegsize */
1855 BUS_DMA_ALLOCNOW, /* flags */
1856 NULL, NULL, /* lockfunc, lockarg */
1857 &dma->dma_tag);
1858 if (r != 0) {
1859 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1860 "bus_dma_tag_create failed; error %u\n", r);
1861 goto fail_0;
1862 }
1863
1864 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1865 if (r != 0) {
1866 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1867 "bus_dmamap_create failed; error %u\n", r);
1868 goto fail_1;
1869 }
1870
1871 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1872 BUS_DMA_NOWAIT, &dma->dma_map);
1873 if (r != 0) {
1874 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1875 "bus_dmammem_alloc failed; size %zu, error %u\n",
1876 size, r);
1877 goto fail_2;
1878 }
1879
1880 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1881 size,
1882 ubsec_dmamap_cb,
1883 &dma->dma_paddr,
1884 mapflags | BUS_DMA_NOWAIT);
1885 if (r != 0) {
1886 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1887 "bus_dmamap_load failed; error %u\n", r);
1888 goto fail_3;
1889 }
1890
1891 dma->dma_size = size;
1892 return (0);
1893
1894 fail_3:
1895 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1896 fail_2:
1897 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1898 fail_1:
1899 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1900 bus_dma_tag_destroy(dma->dma_tag);
1901 fail_0:
1902 dma->dma_map = NULL;
1903 dma->dma_tag = NULL;
1904 return (r);
1905 }
1906
1907 static void
1908 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1909 {
1910 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1911 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1912 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1913 bus_dma_tag_destroy(dma->dma_tag);
1914 }
1915
1916 /*
1917 * Resets the board. Values in the regesters are left as is
1918 * from the reset (i.e. initial values are assigned elsewhere).
1919 */
1920 static void
1921 ubsec_reset_board(struct ubsec_softc *sc)
1922 {
1923 volatile u_int32_t ctrl;
1924
1925 ctrl = READ_REG(sc, BS_CTRL);
1926 ctrl |= BS_CTRL_RESET;
1927 WRITE_REG(sc, BS_CTRL, ctrl);
1928
1929 /*
1930 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1931 */
1932 DELAY(10);
1933 }
1934
1935 /*
1936 * Init Broadcom registers
1937 */
1938 static void
1939 ubsec_init_board(struct ubsec_softc *sc)
1940 {
1941 u_int32_t ctrl;
1942
1943 ctrl = READ_REG(sc, BS_CTRL);
1944 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1945 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1946
1947 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1948 ctrl |= BS_CTRL_MCR2INT;
1949 else
1950 ctrl &= ~BS_CTRL_MCR2INT;
1951
1952 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1953 ctrl &= ~BS_CTRL_SWNORM;
1954
1955 WRITE_REG(sc, BS_CTRL, ctrl);
1956 }
1957
1958 /*
1959 * Init Broadcom PCI registers
1960 */
1961 static void
1962 ubsec_init_pciregs(device_t dev)
1963 {
1964 #if 0
1965 u_int32_t misc;
1966
1967 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1968 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1969 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1970 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1971 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1972 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1973 #endif
1974
1975 /*
1976 * This will set the cache line size to 1, this will
1977 * force the BCM58xx chip just to do burst read/writes.
1978 * Cache line read/writes are to slow
1979 */
1980 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1981 }
1982
1983 /*
1984 * Clean up after a chip crash.
1985 * It is assumed that the caller in splimp()
1986 */
1987 static void
1988 ubsec_cleanchip(struct ubsec_softc *sc)
1989 {
1990 struct ubsec_q *q;
1991
1992 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1993 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1994 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
1995 ubsec_free_q(sc, q);
1996 }
1997 sc->sc_nqchip = 0;
1998 }
1999
2000 /*
2001 * free a ubsec_q
2002 * It is assumed that the caller is within splimp().
2003 */
2004 static int
2005 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2006 {
2007 struct ubsec_q *q2;
2008 struct cryptop *crp;
2009 int npkts;
2010 int i;
2011
2012 npkts = q->q_nstacked_mcrs;
2013
2014 for (i = 0; i < npkts; i++) {
2015 if(q->q_stacked_mcr[i]) {
2016 q2 = q->q_stacked_mcr[i];
2017
2018 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2019 m_freem(q2->q_dst_m);
2020
2021 crp = (struct cryptop *)q2->q_crp;
2022
2023 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2024
2025 crp->crp_etype = EFAULT;
2026 crypto_done(crp);
2027 } else {
2028 break;
2029 }
2030 }
2031
2032 /*
2033 * Free header MCR
2034 */
2035 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2036 m_freem(q->q_dst_m);
2037
2038 crp = (struct cryptop *)q->q_crp;
2039
2040 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2041
2042 crp->crp_etype = EFAULT;
2043 crypto_done(crp);
2044 return(0);
2045 }
2046
2047 /*
2048 * Routine to reset the chip and clean up.
2049 * It is assumed that the caller is in splimp()
2050 */
2051 static void
2052 ubsec_totalreset(struct ubsec_softc *sc)
2053 {
2054 ubsec_reset_board(sc);
2055 ubsec_init_board(sc);
2056 ubsec_cleanchip(sc);
2057 }
2058
2059 static int
2060 ubsec_dmamap_aligned(struct ubsec_operand *op)
2061 {
2062 int i;
2063
2064 for (i = 0; i < op->nsegs; i++) {
2065 if (op->segs[i].ds_addr & 3)
2066 return (0);
2067 if ((i != (op->nsegs - 1)) &&
2068 (op->segs[i].ds_len & 3))
2069 return (0);
2070 }
2071 return (1);
2072 }
2073
2074 static void
2075 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2076 {
2077 switch (q->q_type) {
2078 case UBS_CTXOP_MODEXP: {
2079 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2080
2081 ubsec_dma_free(sc, &me->me_q.q_mcr);
2082 ubsec_dma_free(sc, &me->me_q.q_ctx);
2083 ubsec_dma_free(sc, &me->me_M);
2084 ubsec_dma_free(sc, &me->me_E);
2085 ubsec_dma_free(sc, &me->me_C);
2086 ubsec_dma_free(sc, &me->me_epb);
2087 free(me, M_DEVBUF);
2088 break;
2089 }
2090 case UBS_CTXOP_RSAPRIV: {
2091 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2092
2093 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2094 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2095 ubsec_dma_free(sc, &rp->rpr_msgin);
2096 ubsec_dma_free(sc, &rp->rpr_msgout);
2097 free(rp, M_DEVBUF);
2098 break;
2099 }
2100 default:
2101 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2102 break;
2103 }
2104 }
2105
2106 static int
2107 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2108 {
2109 struct ubsec_softc *sc = arg;
2110 int r;
2111
2112 if (krp == NULL || krp->krp_callback == NULL)
2113 return (EINVAL);
2114
2115 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2116 struct ubsec_q2 *q;
2117
2118 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2119 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next);
2120 ubsec_kfree(sc, q);
2121 }
2122
2123 switch (krp->krp_op) {
2124 case CRK_MOD_EXP:
2125 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2126 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2127 else
2128 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2129 break;
2130 case CRK_MOD_EXP_CRT:
2131 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2132 default:
2133 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2134 krp->krp_op);
2135 krp->krp_status = EOPNOTSUPP;
2136 crypto_kdone(krp);
2137 return (0);
2138 }
2139 return (0); /* silence compiler */
2140 }
2141
2142 /*
2143 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2144 */
2145 static int
2146 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2147 {
2148 struct ubsec_q2_modexp *me;
2149 struct ubsec_mcr *mcr;
2150 struct ubsec_ctx_modexp *ctx;
2151 struct ubsec_pktbuf *epb;
2152 int err = 0;
2153 u_int nbits, normbits, mbits, shiftbits, ebits;
2154
2155 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2156 if (me == NULL) {
2157 err = ENOMEM;
2158 goto errout;
2159 }
2160 bzero(me, sizeof *me);
2161 me->me_krp = krp;
2162 me->me_q.q_type = UBS_CTXOP_MODEXP;
2163
2164 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2165 if (nbits <= 512)
2166 normbits = 512;
2167 else if (nbits <= 768)
2168 normbits = 768;
2169 else if (nbits <= 1024)
2170 normbits = 1024;
2171 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2172 normbits = 1536;
2173 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2174 normbits = 2048;
2175 else {
2176 err = E2BIG;
2177 goto errout;
2178 }
2179
2180 shiftbits = normbits - nbits;
2181
2182 me->me_modbits = nbits;
2183 me->me_shiftbits = shiftbits;
2184 me->me_normbits = normbits;
2185
2186 /* Sanity check: result bits must be >= true modulus bits. */
2187 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2188 err = ERANGE;
2189 goto errout;
2190 }
2191
2192 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2193 &me->me_q.q_mcr, 0)) {
2194 err = ENOMEM;
2195 goto errout;
2196 }
2197 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2198
2199 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2200 &me->me_q.q_ctx, 0)) {
2201 err = ENOMEM;
2202 goto errout;
2203 }
2204
2205 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2206 if (mbits > nbits) {
2207 err = E2BIG;
2208 goto errout;
2209 }
2210 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2211 err = ENOMEM;
2212 goto errout;
2213 }
2214 ubsec_kshift_r(shiftbits,
2215 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2216 me->me_M.dma_vaddr, normbits);
2217
2218 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2219 err = ENOMEM;
2220 goto errout;
2221 }
2222 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2223
2224 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2225 if (ebits > nbits) {
2226 err = E2BIG;
2227 goto errout;
2228 }
2229 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2230 err = ENOMEM;
2231 goto errout;
2232 }
2233 ubsec_kshift_r(shiftbits,
2234 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2235 me->me_E.dma_vaddr, normbits);
2236
2237 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2238 &me->me_epb, 0)) {
2239 err = ENOMEM;
2240 goto errout;
2241 }
2242 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2243 epb->pb_addr = htole32(me->me_E.dma_paddr);
2244 epb->pb_next = 0;
2245 epb->pb_len = htole32(normbits / 8);
2246
2247 #ifdef UBSEC_DEBUG
2248 if (ubsec_debug) {
2249 printf("Epb ");
2250 ubsec_dump_pb(epb);
2251 }
2252 #endif
2253
2254 mcr->mcr_pkts = htole16(1);
2255 mcr->mcr_flags = 0;
2256 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2257 mcr->mcr_reserved = 0;
2258 mcr->mcr_pktlen = 0;
2259
2260 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2261 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2262 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2263
2264 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2265 mcr->mcr_opktbuf.pb_next = 0;
2266 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2267
2268 #ifdef DIAGNOSTIC
2269 /* Misaligned output buffer will hang the chip. */
2270 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2271 panic("%s: modexp invalid addr 0x%x\n",
2272 device_get_nameunit(sc->sc_dev),
2273 letoh32(mcr->mcr_opktbuf.pb_addr));
2274 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2275 panic("%s: modexp invalid len 0x%x\n",
2276 device_get_nameunit(sc->sc_dev),
2277 letoh32(mcr->mcr_opktbuf.pb_len));
2278 #endif
2279
2280 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2281 bzero(ctx, sizeof(*ctx));
2282 ubsec_kshift_r(shiftbits,
2283 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2284 ctx->me_N, normbits);
2285 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2286 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2287 ctx->me_E_len = htole16(nbits);
2288 ctx->me_N_len = htole16(nbits);
2289
2290 #ifdef UBSEC_DEBUG
2291 if (ubsec_debug) {
2292 ubsec_dump_mcr(mcr);
2293 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2294 }
2295 #endif
2296
2297 /*
2298 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2299 * everything else.
2300 */
2301 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2302 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2303 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2304 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2305
2306 /* Enqueue and we're done... */
2307 mtx_lock(&sc->sc_mcr2lock);
2308 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2309 ubsec_feed2(sc);
2310 ubsecstats.hst_modexp++;
2311 mtx_unlock(&sc->sc_mcr2lock);
2312
2313 return (0);
2314
2315 errout:
2316 if (me != NULL) {
2317 if (me->me_q.q_mcr.dma_map != NULL)
2318 ubsec_dma_free(sc, &me->me_q.q_mcr);
2319 if (me->me_q.q_ctx.dma_map != NULL) {
2320 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2321 ubsec_dma_free(sc, &me->me_q.q_ctx);
2322 }
2323 if (me->me_M.dma_map != NULL) {
2324 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2325 ubsec_dma_free(sc, &me->me_M);
2326 }
2327 if (me->me_E.dma_map != NULL) {
2328 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2329 ubsec_dma_free(sc, &me->me_E);
2330 }
2331 if (me->me_C.dma_map != NULL) {
2332 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2333 ubsec_dma_free(sc, &me->me_C);
2334 }
2335 if (me->me_epb.dma_map != NULL)
2336 ubsec_dma_free(sc, &me->me_epb);
2337 free(me, M_DEVBUF);
2338 }
2339 krp->krp_status = err;
2340 crypto_kdone(krp);
2341 return (0);
2342 }
2343
2344 /*
2345 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2346 */
2347 static int
2348 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2349 {
2350 struct ubsec_q2_modexp *me;
2351 struct ubsec_mcr *mcr;
2352 struct ubsec_ctx_modexp *ctx;
2353 struct ubsec_pktbuf *epb;
2354 int err = 0;
2355 u_int nbits, normbits, mbits, shiftbits, ebits;
2356
2357 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2358 if (me == NULL) {
2359 err = ENOMEM;
2360 goto errout;
2361 }
2362 bzero(me, sizeof *me);
2363 me->me_krp = krp;
2364 me->me_q.q_type = UBS_CTXOP_MODEXP;
2365
2366 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2367 if (nbits <= 512)
2368 normbits = 512;
2369 else if (nbits <= 768)
2370 normbits = 768;
2371 else if (nbits <= 1024)
2372 normbits = 1024;
2373 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2374 normbits = 1536;
2375 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2376 normbits = 2048;
2377 else {
2378 err = E2BIG;
2379 goto errout;
2380 }
2381
2382 shiftbits = normbits - nbits;
2383
2384 /* XXX ??? */
2385 me->me_modbits = nbits;
2386 me->me_shiftbits = shiftbits;
2387 me->me_normbits = normbits;
2388
2389 /* Sanity check: result bits must be >= true modulus bits. */
2390 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2391 err = ERANGE;
2392 goto errout;
2393 }
2394
2395 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2396 &me->me_q.q_mcr, 0)) {
2397 err = ENOMEM;
2398 goto errout;
2399 }
2400 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2401
2402 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2403 &me->me_q.q_ctx, 0)) {
2404 err = ENOMEM;
2405 goto errout;
2406 }
2407
2408 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2409 if (mbits > nbits) {
2410 err = E2BIG;
2411 goto errout;
2412 }
2413 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2414 err = ENOMEM;
2415 goto errout;
2416 }
2417 bzero(me->me_M.dma_vaddr, normbits / 8);
2418 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2419 me->me_M.dma_vaddr, (mbits + 7) / 8);
2420
2421 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2422 err = ENOMEM;
2423 goto errout;
2424 }
2425 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2426
2427 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2428 if (ebits > nbits) {
2429 err = E2BIG;
2430 goto errout;
2431 }
2432 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2433 err = ENOMEM;
2434 goto errout;
2435 }
2436 bzero(me->me_E.dma_vaddr, normbits / 8);
2437 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2438 me->me_E.dma_vaddr, (ebits + 7) / 8);
2439
2440 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2441 &me->me_epb, 0)) {
2442 err = ENOMEM;
2443 goto errout;
2444 }
2445 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2446 epb->pb_addr = htole32(me->me_E.dma_paddr);
2447 epb->pb_next = 0;
2448 epb->pb_len = htole32((ebits + 7) / 8);
2449
2450 #ifdef UBSEC_DEBUG
2451 if (ubsec_debug) {
2452 printf("Epb ");
2453 ubsec_dump_pb(epb);
2454 }
2455 #endif
2456
2457 mcr->mcr_pkts = htole16(1);
2458 mcr->mcr_flags = 0;
2459 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2460 mcr->mcr_reserved = 0;
2461 mcr->mcr_pktlen = 0;
2462
2463 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2464 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2465 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2466
2467 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2468 mcr->mcr_opktbuf.pb_next = 0;
2469 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2470
2471 #ifdef DIAGNOSTIC
2472 /* Misaligned output buffer will hang the chip. */
2473 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2474 panic("%s: modexp invalid addr 0x%x\n",
2475 device_get_nameunit(sc->sc_dev),
2476 letoh32(mcr->mcr_opktbuf.pb_addr));
2477 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2478 panic("%s: modexp invalid len 0x%x\n",
2479 device_get_nameunit(sc->sc_dev),
2480 letoh32(mcr->mcr_opktbuf.pb_len));
2481 #endif
2482
2483 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2484 bzero(ctx, sizeof(*ctx));
2485 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2486 (nbits + 7) / 8);
2487 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2488 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2489 ctx->me_E_len = htole16(ebits);
2490 ctx->me_N_len = htole16(nbits);
2491
2492 #ifdef UBSEC_DEBUG
2493 if (ubsec_debug) {
2494 ubsec_dump_mcr(mcr);
2495 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2496 }
2497 #endif
2498
2499 /*
2500 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2501 * everything else.
2502 */
2503 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2504 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2505 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2506 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2507
2508 /* Enqueue and we're done... */
2509 mtx_lock(&sc->sc_mcr2lock);
2510 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2511 ubsec_feed2(sc);
2512 mtx_unlock(&sc->sc_mcr2lock);
2513
2514 return (0);
2515
2516 errout:
2517 if (me != NULL) {
2518 if (me->me_q.q_mcr.dma_map != NULL)
2519 ubsec_dma_free(sc, &me->me_q.q_mcr);
2520 if (me->me_q.q_ctx.dma_map != NULL) {
2521 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2522 ubsec_dma_free(sc, &me->me_q.q_ctx);
2523 }
2524 if (me->me_M.dma_map != NULL) {
2525 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2526 ubsec_dma_free(sc, &me->me_M);
2527 }
2528 if (me->me_E.dma_map != NULL) {
2529 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2530 ubsec_dma_free(sc, &me->me_E);
2531 }
2532 if (me->me_C.dma_map != NULL) {
2533 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2534 ubsec_dma_free(sc, &me->me_C);
2535 }
2536 if (me->me_epb.dma_map != NULL)
2537 ubsec_dma_free(sc, &me->me_epb);
2538 free(me, M_DEVBUF);
2539 }
2540 krp->krp_status = err;
2541 crypto_kdone(krp);
2542 return (0);
2543 }
2544
2545 static int
2546 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2547 {
2548 struct ubsec_q2_rsapriv *rp = NULL;
2549 struct ubsec_mcr *mcr;
2550 struct ubsec_ctx_rsapriv *ctx;
2551 int err = 0;
2552 u_int padlen, msglen;
2553
2554 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2555 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2556 if (msglen > padlen)
2557 padlen = msglen;
2558
2559 if (padlen <= 256)
2560 padlen = 256;
2561 else if (padlen <= 384)
2562 padlen = 384;
2563 else if (padlen <= 512)
2564 padlen = 512;
2565 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2566 padlen = 768;
2567 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2568 padlen = 1024;
2569 else {
2570 err = E2BIG;
2571 goto errout;
2572 }
2573
2574 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2575 err = E2BIG;
2576 goto errout;
2577 }
2578
2579 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2580 err = E2BIG;
2581 goto errout;
2582 }
2583
2584 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2585 err = E2BIG;
2586 goto errout;
2587 }
2588
2589 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2590 if (rp == NULL)
2591 return (ENOMEM);
2592 bzero(rp, sizeof *rp);
2593 rp->rpr_krp = krp;
2594 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2595
2596 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2597 &rp->rpr_q.q_mcr, 0)) {
2598 err = ENOMEM;
2599 goto errout;
2600 }
2601 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2602
2603 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2604 &rp->rpr_q.q_ctx, 0)) {
2605 err = ENOMEM;
2606 goto errout;
2607 }
2608 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2609 bzero(ctx, sizeof *ctx);
2610
2611 /* Copy in p */
2612 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2613 &ctx->rpr_buf[0 * (padlen / 8)],
2614 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2615
2616 /* Copy in q */
2617 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2618 &ctx->rpr_buf[1 * (padlen / 8)],
2619 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2620
2621 /* Copy in dp */
2622 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2623 &ctx->rpr_buf[2 * (padlen / 8)],
2624 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2625
2626 /* Copy in dq */
2627 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2628 &ctx->rpr_buf[3 * (padlen / 8)],
2629 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2630
2631 /* Copy in pinv */
2632 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2633 &ctx->rpr_buf[4 * (padlen / 8)],
2634 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2635
2636 msglen = padlen * 2;
2637
2638 /* Copy in input message (aligned buffer/length). */
2639 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2640 /* Is this likely? */
2641 err = E2BIG;
2642 goto errout;
2643 }
2644 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2645 err = ENOMEM;
2646 goto errout;
2647 }
2648 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2649 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2650 rp->rpr_msgin.dma_vaddr,
2651 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2652
2653 /* Prepare space for output message (aligned buffer/length). */
2654 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2655 /* Is this likely? */
2656 err = E2BIG;
2657 goto errout;
2658 }
2659 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2660 err = ENOMEM;
2661 goto errout;
2662 }
2663 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2664
2665 mcr->mcr_pkts = htole16(1);
2666 mcr->mcr_flags = 0;
2667 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2668 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2669 mcr->mcr_ipktbuf.pb_next = 0;
2670 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2671 mcr->mcr_reserved = 0;
2672 mcr->mcr_pktlen = htole16(msglen);
2673 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2674 mcr->mcr_opktbuf.pb_next = 0;
2675 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2676
2677 #ifdef DIAGNOSTIC
2678 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2679 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2680 device_get_nameunit(sc->sc_dev),
2681 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2682 }
2683 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2684 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2685 device_get_nameunit(sc->sc_dev),
2686 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2687 }
2688 #endif
2689
2690 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2691 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2692 ctx->rpr_q_len = htole16(padlen);
2693 ctx->rpr_p_len = htole16(padlen);
2694
2695 /*
2696 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2697 * everything else.
2698 */
2699 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2700 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2701
2702 /* Enqueue and we're done... */
2703 mtx_lock(&sc->sc_mcr2lock);
2704 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2705 ubsec_feed2(sc);
2706 ubsecstats.hst_modexpcrt++;
2707 mtx_unlock(&sc->sc_mcr2lock);
2708 return (0);
2709
2710 errout:
2711 if (rp != NULL) {
2712 if (rp->rpr_q.q_mcr.dma_map != NULL)
2713 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2714 if (rp->rpr_msgin.dma_map != NULL) {
2715 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2716 ubsec_dma_free(sc, &rp->rpr_msgin);
2717 }
2718 if (rp->rpr_msgout.dma_map != NULL) {
2719 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2720 ubsec_dma_free(sc, &rp->rpr_msgout);
2721 }
2722 free(rp, M_DEVBUF);
2723 }
2724 krp->krp_status = err;
2725 crypto_kdone(krp);
2726 return (0);
2727 }
2728
2729 #ifdef UBSEC_DEBUG
2730 static void
2731 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2732 {
2733 printf("addr 0x%x (0x%x) next 0x%x\n",
2734 pb->pb_addr, pb->pb_len, pb->pb_next);
2735 }
2736
2737 static void
2738 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2739 {
2740 printf("CTX (0x%x):\n", c->ctx_len);
2741 switch (letoh16(c->ctx_op)) {
2742 case UBS_CTXOP_RNGBYPASS:
2743 case UBS_CTXOP_RNGSHA1:
2744 break;
2745 case UBS_CTXOP_MODEXP:
2746 {
2747 struct ubsec_ctx_modexp *cx = (void *)c;
2748 int i, len;
2749
2750 printf(" Elen %u, Nlen %u\n",
2751 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2752 len = (cx->me_N_len + 7)/8;
2753 for (i = 0; i < len; i++)
2754 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2755 printf("\n");
2756 break;
2757 }
2758 default:
2759 printf("unknown context: %x\n", c->ctx_op);
2760 }
2761 printf("END CTX\n");
2762 }
2763
2764 static void
2765 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2766 {
2767 volatile struct ubsec_mcr_add *ma;
2768 int i;
2769
2770 printf("MCR:\n");
2771 printf(" pkts: %u, flags 0x%x\n",
2772 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2773 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2774 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2775 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2776 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2777 letoh16(ma->mcr_reserved));
2778 printf(" %d: ipkt ", i);
2779 ubsec_dump_pb(&ma->mcr_ipktbuf);
2780 printf(" %d: opkt ", i);
2781 ubsec_dump_pb(&ma->mcr_opktbuf);
2782 ma++;
2783 }
2784 printf("END MCR\n");
2785 }
2786 #endif /* UBSEC_DEBUG */
2787
2788 /*
2789 * Return the number of significant bits of a big number.
2790 */
2791 static int
2792 ubsec_ksigbits(struct crparam *cr)
2793 {
2794 u_int plen = (cr->crp_nbits + 7) / 8;
2795 int i, sig = plen * 8;
2796 u_int8_t c, *p = cr->crp_p;
2797
2798 for (i = plen - 1; i >= 0; i--) {
2799 c = p[i];
2800 if (c != 0) {
2801 while ((c & 0x80) == 0) {
2802 sig--;
2803 c <<= 1;
2804 }
2805 break;
2806 }
2807 sig -= 8;
2808 }
2809 return (sig);
2810 }
2811
2812 static void
2813 ubsec_kshift_r(
2814 u_int shiftbits,
2815 u_int8_t *src, u_int srcbits,
2816 u_int8_t *dst, u_int dstbits)
2817 {
2818 u_int slen, dlen;
2819 int i, si, di, n;
2820
2821 slen = (srcbits + 7) / 8;
2822 dlen = (dstbits + 7) / 8;
2823
2824 for (i = 0; i < slen; i++)
2825 dst[i] = src[i];
2826 for (i = 0; i < dlen - slen; i++)
2827 dst[slen + i] = 0;
2828
2829 n = shiftbits / 8;
2830 if (n != 0) {
2831 si = dlen - n - 1;
2832 di = dlen - 1;
2833 while (si >= 0)
2834 dst[di--] = dst[si--];
2835 while (di >= 0)
2836 dst[di--] = 0;
2837 }
2838
2839 n = shiftbits % 8;
2840 if (n != 0) {
2841 for (i = dlen - 1; i > 0; i--)
2842 dst[i] = (dst[i] << n) |
2843 (dst[i - 1] >> (8 - n));
2844 dst[0] = dst[0] << n;
2845 }
2846 }
2847
2848 static void
2849 ubsec_kshift_l(
2850 u_int shiftbits,
2851 u_int8_t *src, u_int srcbits,
2852 u_int8_t *dst, u_int dstbits)
2853 {
2854 int slen, dlen, i, n;
2855
2856 slen = (srcbits + 7) / 8;
2857 dlen = (dstbits + 7) / 8;
2858
2859 n = shiftbits / 8;
2860 for (i = 0; i < slen; i++)
2861 dst[i] = src[i + n];
2862 for (i = 0; i < dlen - slen; i++)
2863 dst[slen + i] = 0;
2864
2865 n = shiftbits % 8;
2866 if (n != 0) {
2867 for (i = 0; i < (dlen - 1); i++)
2868 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2869 dst[dlen - 1] = dst[dlen - 1] >> n;
2870 }
2871 }
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