FreeBSD/Linux Kernel Cross Reference
sys/dev/ubsec/ubsec.c
1 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
2
3 /*-
4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Effort sponsored in part by the Defense Advanced Research Projects
37 * Agency (DARPA) and Air Force Research Laboratory, Air Force
38 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 /*
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
46 */
47
48 #include "opt_ubsec.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/proc.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
57 #include <sys/mbuf.h>
58 #include <sys/lock.h>
59 #include <sys/mutex.h>
60 #include <sys/sysctl.h>
61 #include <sys/endian.h>
62
63 #include <vm/vm.h>
64 #include <vm/pmap.h>
65
66 #include <machine/bus.h>
67 #include <machine/resource.h>
68 #include <sys/bus.h>
69 #include <sys/rman.h>
70
71 #include <crypto/sha1.h>
72 #include <opencrypto/cryptodev.h>
73 #include <opencrypto/cryptosoft.h>
74 #include <sys/md5.h>
75 #include <sys/random.h>
76 #include <sys/kobj.h>
77
78 #include "cryptodev_if.h"
79
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pcireg.h>
82
83 /* grr, #defines for gratuitous incompatibility in queue.h */
84 #define SIMPLEQ_HEAD STAILQ_HEAD
85 #define SIMPLEQ_ENTRY STAILQ_ENTRY
86 #define SIMPLEQ_INIT STAILQ_INIT
87 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
88 #define SIMPLEQ_EMPTY STAILQ_EMPTY
89 #define SIMPLEQ_FIRST STAILQ_FIRST
90 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
91 #define SIMPLEQ_FOREACH STAILQ_FOREACH
92 /* ditto for endian.h */
93 #define letoh16(x) le16toh(x)
94 #define letoh32(x) le32toh(x)
95
96 #ifdef UBSEC_RNDTEST
97 #include <dev/rndtest/rndtest.h>
98 #endif
99 #include <dev/ubsec/ubsecreg.h>
100 #include <dev/ubsec/ubsecvar.h>
101
102 /*
103 * Prototypes and count for the pci_device structure
104 */
105 static int ubsec_probe(device_t);
106 static int ubsec_attach(device_t);
107 static int ubsec_detach(device_t);
108 static int ubsec_suspend(device_t);
109 static int ubsec_resume(device_t);
110 static void ubsec_shutdown(device_t);
111
112 static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
113 static int ubsec_freesession(device_t, u_int64_t);
114 static int ubsec_process(device_t, struct cryptop *, int);
115 static int ubsec_kprocess(device_t, struct cryptkop *, int);
116
117 static device_method_t ubsec_methods[] = {
118 /* Device interface */
119 DEVMETHOD(device_probe, ubsec_probe),
120 DEVMETHOD(device_attach, ubsec_attach),
121 DEVMETHOD(device_detach, ubsec_detach),
122 DEVMETHOD(device_suspend, ubsec_suspend),
123 DEVMETHOD(device_resume, ubsec_resume),
124 DEVMETHOD(device_shutdown, ubsec_shutdown),
125
126 /* bus interface */
127 DEVMETHOD(bus_print_child, bus_generic_print_child),
128 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
129
130 /* crypto device methods */
131 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
132 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
133 DEVMETHOD(cryptodev_process, ubsec_process),
134 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess),
135
136 { 0, 0 }
137 };
138 static driver_t ubsec_driver = {
139 "ubsec",
140 ubsec_methods,
141 sizeof (struct ubsec_softc)
142 };
143 static devclass_t ubsec_devclass;
144
145 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
146 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
147 #ifdef UBSEC_RNDTEST
148 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
149 #endif
150
151 static void ubsec_intr(void *);
152 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
153 static void ubsec_feed(struct ubsec_softc *);
154 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
155 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
156 static int ubsec_feed2(struct ubsec_softc *);
157 static void ubsec_rng(void *);
158 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
159 struct ubsec_dma_alloc *, int);
160 #define ubsec_dma_sync(_dma, _flags) \
161 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
162 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
163 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
164
165 static void ubsec_reset_board(struct ubsec_softc *sc);
166 static void ubsec_init_board(struct ubsec_softc *sc);
167 static void ubsec_init_pciregs(device_t dev);
168 static void ubsec_totalreset(struct ubsec_softc *sc);
169
170 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
171
172 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
173 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
174 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
175 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
176 static int ubsec_ksigbits(struct crparam *);
177 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
178 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
179
180 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
181
182 #ifdef UBSEC_DEBUG
183 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
184 static void ubsec_dump_mcr(struct ubsec_mcr *);
185 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
186
187 static int ubsec_debug = 0;
188 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
189 0, "control debugging msgs");
190 #endif
191
192 #define READ_REG(sc,r) \
193 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
194
195 #define WRITE_REG(sc,reg,val) \
196 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
197
198 #define SWAP32(x) (x) = htole32(ntohl((x)))
199 #define HTOLE32(x) (x) = htole32(x)
200
201 struct ubsec_stats ubsecstats;
202 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
203 ubsec_stats, "driver statistics");
204
205 static int
206 ubsec_probe(device_t dev)
207 {
208 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
209 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
210 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
211 return (BUS_PROBE_DEFAULT);
212 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
213 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
214 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
215 return (BUS_PROBE_DEFAULT);
216 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
217 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
221 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
222 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
223 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
224 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825
225 ))
226 return (BUS_PROBE_DEFAULT);
227 return (ENXIO);
228 }
229
230 static const char*
231 ubsec_partname(struct ubsec_softc *sc)
232 {
233 /* XXX sprintf numbers when not decoded */
234 switch (pci_get_vendor(sc->sc_dev)) {
235 case PCI_VENDOR_BROADCOM:
236 switch (pci_get_device(sc->sc_dev)) {
237 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
238 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
239 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
240 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
241 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
242 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
243 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
244 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825";
245 }
246 return "Broadcom unknown-part";
247 case PCI_VENDOR_BLUESTEEL:
248 switch (pci_get_device(sc->sc_dev)) {
249 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
250 }
251 return "Bluesteel unknown-part";
252 case PCI_VENDOR_SUN:
253 switch (pci_get_device(sc->sc_dev)) {
254 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
255 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
256 }
257 return "Sun unknown-part";
258 }
259 return "Unknown-vendor unknown-part";
260 }
261
262 static void
263 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
264 {
265 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE);
266 }
267
268 static int
269 ubsec_attach(device_t dev)
270 {
271 struct ubsec_softc *sc = device_get_softc(dev);
272 struct ubsec_dma *dmap;
273 u_int32_t cmd, i;
274 int rid;
275
276 bzero(sc, sizeof (*sc));
277 sc->sc_dev = dev;
278
279 SIMPLEQ_INIT(&sc->sc_queue);
280 SIMPLEQ_INIT(&sc->sc_qchip);
281 SIMPLEQ_INIT(&sc->sc_queue2);
282 SIMPLEQ_INIT(&sc->sc_qchip2);
283 SIMPLEQ_INIT(&sc->sc_q2free);
284
285 /* XXX handle power management */
286
287 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
288
289 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
290 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
291 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
292
293 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
294 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
295 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
296 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
297
298 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
299 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
300 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
301 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
302
303 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
304 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
305 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
306 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
307 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) ||
308 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
309 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
310 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
311 /* NB: the 5821/5822 defines some additional status bits */
312 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
313 BS_STAT_MCR2_ALLEMPTY;
314 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
315 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
316 }
317
318 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
319 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
320 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
321 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
322
323 if (!(cmd & PCIM_CMD_MEMEN)) {
324 device_printf(dev, "failed to enable memory mapping\n");
325 goto bad;
326 }
327
328 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
329 device_printf(dev, "failed to enable bus mastering\n");
330 goto bad;
331 }
332
333 /*
334 * Setup memory-mapping of PCI registers.
335 */
336 rid = BS_BAR;
337 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
338 RF_ACTIVE);
339 if (sc->sc_sr == NULL) {
340 device_printf(dev, "cannot map register space\n");
341 goto bad;
342 }
343 sc->sc_st = rman_get_bustag(sc->sc_sr);
344 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
345
346 /*
347 * Arrange interrupt line.
348 */
349 rid = 0;
350 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
351 RF_SHAREABLE|RF_ACTIVE);
352 if (sc->sc_irq == NULL) {
353 device_printf(dev, "could not map interrupt\n");
354 goto bad1;
355 }
356 /*
357 * NB: Network code assumes we are blocked with splimp()
358 * so make sure the IRQ is mapped appropriately.
359 */
360 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
361 NULL, ubsec_intr, sc, &sc->sc_ih)) {
362 device_printf(dev, "could not establish interrupt\n");
363 goto bad2;
364 }
365
366 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
367 if (sc->sc_cid < 0) {
368 device_printf(dev, "could not get crypto driver id\n");
369 goto bad3;
370 }
371
372 /*
373 * Setup DMA descriptor area.
374 */
375 if (bus_dma_tag_create(NULL, /* parent */
376 1, 0, /* alignment, bounds */
377 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
378 BUS_SPACE_MAXADDR, /* highaddr */
379 NULL, NULL, /* filter, filterarg */
380 0x3ffff, /* maxsize */
381 UBS_MAX_SCATTER, /* nsegments */
382 0xffff, /* maxsegsize */
383 BUS_DMA_ALLOCNOW, /* flags */
384 NULL, NULL, /* lockfunc, lockarg */
385 &sc->sc_dmat)) {
386 device_printf(dev, "cannot allocate DMA tag\n");
387 goto bad4;
388 }
389 SIMPLEQ_INIT(&sc->sc_freequeue);
390 dmap = sc->sc_dmaa;
391 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
392 struct ubsec_q *q;
393
394 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
395 M_DEVBUF, M_NOWAIT);
396 if (q == NULL) {
397 device_printf(dev, "cannot allocate queue buffers\n");
398 break;
399 }
400
401 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
402 &dmap->d_alloc, 0)) {
403 device_printf(dev, "cannot allocate dma buffers\n");
404 free(q, M_DEVBUF);
405 break;
406 }
407 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
408
409 q->q_dma = dmap;
410 sc->sc_queuea[i] = q;
411
412 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
413 }
414 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
415 "mcr1 operations", MTX_DEF);
416 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
417 "mcr1 free q", MTX_DEF);
418
419 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
420
421 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
422 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
423 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
424 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
425
426 /*
427 * Reset Broadcom chip
428 */
429 ubsec_reset_board(sc);
430
431 /*
432 * Init Broadcom specific PCI settings
433 */
434 ubsec_init_pciregs(dev);
435
436 /*
437 * Init Broadcom chip
438 */
439 ubsec_init_board(sc);
440
441 #ifndef UBSEC_NO_RNG
442 if (sc->sc_flags & UBS_FLAGS_RNG) {
443 sc->sc_statmask |= BS_STAT_MCR2_DONE;
444 #ifdef UBSEC_RNDTEST
445 sc->sc_rndtest = rndtest_attach(dev);
446 if (sc->sc_rndtest)
447 sc->sc_harvest = rndtest_harvest;
448 else
449 sc->sc_harvest = default_harvest;
450 #else
451 sc->sc_harvest = default_harvest;
452 #endif
453
454 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
455 &sc->sc_rng.rng_q.q_mcr, 0))
456 goto skip_rng;
457
458 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
459 &sc->sc_rng.rng_q.q_ctx, 0)) {
460 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
461 goto skip_rng;
462 }
463
464 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
465 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
466 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
467 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
468 goto skip_rng;
469 }
470
471 if (hz >= 100)
472 sc->sc_rnghz = hz / 100;
473 else
474 sc->sc_rnghz = 1;
475 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
476 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
477 skip_rng:
478 ;
479 }
480 #endif /* UBSEC_NO_RNG */
481 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
482 "mcr2 operations", MTX_DEF);
483
484 if (sc->sc_flags & UBS_FLAGS_KEY) {
485 sc->sc_statmask |= BS_STAT_MCR2_DONE;
486
487 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
488 #if 0
489 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
490 #endif
491 }
492 return (0);
493 bad4:
494 crypto_unregister_all(sc->sc_cid);
495 bad3:
496 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
497 bad2:
498 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
499 bad1:
500 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
501 bad:
502 return (ENXIO);
503 }
504
505 /*
506 * Detach a device that successfully probed.
507 */
508 static int
509 ubsec_detach(device_t dev)
510 {
511 struct ubsec_softc *sc = device_get_softc(dev);
512
513 /* XXX wait/abort active ops */
514
515 /* disable interrupts */
516 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
517 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
518
519 callout_stop(&sc->sc_rngto);
520
521 crypto_unregister_all(sc->sc_cid);
522
523 #ifdef UBSEC_RNDTEST
524 if (sc->sc_rndtest)
525 rndtest_detach(sc->sc_rndtest);
526 #endif
527
528 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
529 struct ubsec_q *q;
530
531 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
532 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
533 ubsec_dma_free(sc, &q->q_dma->d_alloc);
534 free(q, M_DEVBUF);
535 }
536 mtx_destroy(&sc->sc_mcr1lock);
537 mtx_destroy(&sc->sc_freeqlock);
538 #ifndef UBSEC_NO_RNG
539 if (sc->sc_flags & UBS_FLAGS_RNG) {
540 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
541 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
542 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
543 }
544 #endif /* UBSEC_NO_RNG */
545 mtx_destroy(&sc->sc_mcr2lock);
546
547 bus_generic_detach(dev);
548 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
550
551 bus_dma_tag_destroy(sc->sc_dmat);
552 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
553
554 return (0);
555 }
556
557 /*
558 * Stop all chip i/o so that the kernel's probe routines don't
559 * get confused by errant DMAs when rebooting.
560 */
561 static void
562 ubsec_shutdown(device_t dev)
563 {
564 #ifdef notyet
565 ubsec_stop(device_get_softc(dev));
566 #endif
567 }
568
569 /*
570 * Device suspend routine.
571 */
572 static int
573 ubsec_suspend(device_t dev)
574 {
575 struct ubsec_softc *sc = device_get_softc(dev);
576
577 #ifdef notyet
578 /* XXX stop the device and save PCI settings */
579 #endif
580 sc->sc_suspended = 1;
581
582 return (0);
583 }
584
585 static int
586 ubsec_resume(device_t dev)
587 {
588 struct ubsec_softc *sc = device_get_softc(dev);
589
590 #ifdef notyet
591 /* XXX retore PCI settings and start the device */
592 #endif
593 sc->sc_suspended = 0;
594 return (0);
595 }
596
597 /*
598 * UBSEC Interrupt routine
599 */
600 static void
601 ubsec_intr(void *arg)
602 {
603 struct ubsec_softc *sc = arg;
604 volatile u_int32_t stat;
605 struct ubsec_q *q;
606 struct ubsec_dma *dmap;
607 int npkts = 0, i;
608
609 stat = READ_REG(sc, BS_STAT);
610 stat &= sc->sc_statmask;
611 if (stat == 0)
612 return;
613
614 WRITE_REG(sc, BS_STAT, stat); /* IACK */
615
616 /*
617 * Check to see if we have any packets waiting for us
618 */
619 if ((stat & BS_STAT_MCR1_DONE)) {
620 mtx_lock(&sc->sc_mcr1lock);
621 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
622 q = SIMPLEQ_FIRST(&sc->sc_qchip);
623 dmap = q->q_dma;
624
625 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
626 break;
627
628 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
629
630 npkts = q->q_nstacked_mcrs;
631 sc->sc_nqchip -= 1+npkts;
632 /*
633 * search for further sc_qchip ubsec_q's that share
634 * the same MCR, and complete them too, they must be
635 * at the top.
636 */
637 for (i = 0; i < npkts; i++) {
638 if(q->q_stacked_mcr[i]) {
639 ubsec_callback(sc, q->q_stacked_mcr[i]);
640 } else {
641 break;
642 }
643 }
644 ubsec_callback(sc, q);
645 }
646 /*
647 * Don't send any more packet to chip if there has been
648 * a DMAERR.
649 */
650 if (!(stat & BS_STAT_DMAERR))
651 ubsec_feed(sc);
652 mtx_unlock(&sc->sc_mcr1lock);
653 }
654
655 /*
656 * Check to see if we have any key setups/rng's waiting for us
657 */
658 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
659 (stat & BS_STAT_MCR2_DONE)) {
660 struct ubsec_q2 *q2;
661 struct ubsec_mcr *mcr;
662
663 mtx_lock(&sc->sc_mcr2lock);
664 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
665 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
666
667 ubsec_dma_sync(&q2->q_mcr,
668 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
669
670 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
671 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
672 ubsec_dma_sync(&q2->q_mcr,
673 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
674 break;
675 }
676 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
677 ubsec_callback2(sc, q2);
678 /*
679 * Don't send any more packet to chip if there has been
680 * a DMAERR.
681 */
682 if (!(stat & BS_STAT_DMAERR))
683 ubsec_feed2(sc);
684 }
685 mtx_unlock(&sc->sc_mcr2lock);
686 }
687
688 /*
689 * Check to see if we got any DMA Error
690 */
691 if (stat & BS_STAT_DMAERR) {
692 #ifdef UBSEC_DEBUG
693 if (ubsec_debug) {
694 volatile u_int32_t a = READ_REG(sc, BS_ERR);
695
696 printf("dmaerr %s@%08x\n",
697 (a & BS_ERR_READ) ? "read" : "write",
698 a & BS_ERR_ADDR);
699 }
700 #endif /* UBSEC_DEBUG */
701 ubsecstats.hst_dmaerr++;
702 mtx_lock(&sc->sc_mcr1lock);
703 ubsec_totalreset(sc);
704 ubsec_feed(sc);
705 mtx_unlock(&sc->sc_mcr1lock);
706 }
707
708 if (sc->sc_needwakeup) { /* XXX check high watermark */
709 int wakeup;
710
711 mtx_lock(&sc->sc_freeqlock);
712 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
713 #ifdef UBSEC_DEBUG
714 if (ubsec_debug)
715 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
716 sc->sc_needwakeup);
717 #endif /* UBSEC_DEBUG */
718 sc->sc_needwakeup &= ~wakeup;
719 mtx_unlock(&sc->sc_freeqlock);
720 crypto_unblock(sc->sc_cid, wakeup);
721 }
722 }
723
724 /*
725 * ubsec_feed() - aggregate and post requests to chip
726 */
727 static void
728 ubsec_feed(struct ubsec_softc *sc)
729 {
730 struct ubsec_q *q, *q2;
731 int npkts, i;
732 void *v;
733 u_int32_t stat;
734
735 /*
736 * Decide how many ops to combine in a single MCR. We cannot
737 * aggregate more than UBS_MAX_AGGR because this is the number
738 * of slots defined in the data structure. Note that
739 * aggregation only happens if ops are marked batch'able.
740 * Aggregating ops reduces the number of interrupts to the host
741 * but also (potentially) increases the latency for processing
742 * completed ops as we only get an interrupt when all aggregated
743 * ops have completed.
744 */
745 if (sc->sc_nqueue == 0)
746 return;
747 if (sc->sc_nqueue > 1) {
748 npkts = 0;
749 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
750 npkts++;
751 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
752 break;
753 }
754 } else
755 npkts = 1;
756 /*
757 * Check device status before going any further.
758 */
759 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
760 if (stat & BS_STAT_DMAERR) {
761 ubsec_totalreset(sc);
762 ubsecstats.hst_dmaerr++;
763 } else
764 ubsecstats.hst_mcr1full++;
765 return;
766 }
767 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
768 ubsecstats.hst_maxqueue = sc->sc_nqueue;
769 if (npkts > UBS_MAX_AGGR)
770 npkts = UBS_MAX_AGGR;
771 if (npkts < 2) /* special case 1 op */
772 goto feed1;
773
774 ubsecstats.hst_totbatch += npkts-1;
775 #ifdef UBSEC_DEBUG
776 if (ubsec_debug)
777 printf("merging %d records\n", npkts);
778 #endif /* UBSEC_DEBUG */
779
780 q = SIMPLEQ_FIRST(&sc->sc_queue);
781 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
782 --sc->sc_nqueue;
783
784 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
785 if (q->q_dst_map != NULL)
786 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
787
788 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
789
790 for (i = 0; i < q->q_nstacked_mcrs; i++) {
791 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
792 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
793 BUS_DMASYNC_PREWRITE);
794 if (q2->q_dst_map != NULL)
795 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
796 BUS_DMASYNC_PREREAD);
797 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
798 --sc->sc_nqueue;
799
800 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
801 sizeof(struct ubsec_mcr_add));
802 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
803 q->q_stacked_mcr[i] = q2;
804 }
805 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
806 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
807 sc->sc_nqchip += npkts;
808 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
809 ubsecstats.hst_maxqchip = sc->sc_nqchip;
810 ubsec_dma_sync(&q->q_dma->d_alloc,
811 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
812 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
813 offsetof(struct ubsec_dmachunk, d_mcr));
814 return;
815 feed1:
816 q = SIMPLEQ_FIRST(&sc->sc_queue);
817
818 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
819 if (q->q_dst_map != NULL)
820 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
821 ubsec_dma_sync(&q->q_dma->d_alloc,
822 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
823
824 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
825 offsetof(struct ubsec_dmachunk, d_mcr));
826 #ifdef UBSEC_DEBUG
827 if (ubsec_debug)
828 printf("feed1: q->chip %p %08x stat %08x\n",
829 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
830 stat);
831 #endif /* UBSEC_DEBUG */
832 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
833 --sc->sc_nqueue;
834 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
835 sc->sc_nqchip++;
836 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
837 ubsecstats.hst_maxqchip = sc->sc_nqchip;
838 return;
839 }
840
841 static void
842 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
843 {
844
845 /* Go ahead and compute key in ubsec's byte order */
846 if (algo == CRYPTO_DES_CBC) {
847 bcopy(key, &ses->ses_deskey[0], 8);
848 bcopy(key, &ses->ses_deskey[2], 8);
849 bcopy(key, &ses->ses_deskey[4], 8);
850 } else
851 bcopy(key, ses->ses_deskey, 24);
852
853 SWAP32(ses->ses_deskey[0]);
854 SWAP32(ses->ses_deskey[1]);
855 SWAP32(ses->ses_deskey[2]);
856 SWAP32(ses->ses_deskey[3]);
857 SWAP32(ses->ses_deskey[4]);
858 SWAP32(ses->ses_deskey[5]);
859 }
860
861 static void
862 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
863 {
864 MD5_CTX md5ctx;
865 SHA1_CTX sha1ctx;
866 int i;
867
868 for (i = 0; i < klen; i++)
869 key[i] ^= HMAC_IPAD_VAL;
870
871 if (algo == CRYPTO_MD5_HMAC) {
872 MD5Init(&md5ctx);
873 MD5Update(&md5ctx, key, klen);
874 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
875 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
876 } else {
877 SHA1Init(&sha1ctx);
878 SHA1Update(&sha1ctx, key, klen);
879 SHA1Update(&sha1ctx, hmac_ipad_buffer,
880 SHA1_HMAC_BLOCK_LEN - klen);
881 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
882 }
883
884 for (i = 0; i < klen; i++)
885 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
886
887 if (algo == CRYPTO_MD5_HMAC) {
888 MD5Init(&md5ctx);
889 MD5Update(&md5ctx, key, klen);
890 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
891 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
892 } else {
893 SHA1Init(&sha1ctx);
894 SHA1Update(&sha1ctx, key, klen);
895 SHA1Update(&sha1ctx, hmac_opad_buffer,
896 SHA1_HMAC_BLOCK_LEN - klen);
897 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
898 }
899
900 for (i = 0; i < klen; i++)
901 key[i] ^= HMAC_OPAD_VAL;
902 }
903
904 /*
905 * Allocate a new 'session' and return an encoded session id. 'sidp'
906 * contains our registration id, and should contain an encoded session
907 * id on successful allocation.
908 */
909 static int
910 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
911 {
912 struct ubsec_softc *sc = device_get_softc(dev);
913 struct cryptoini *c, *encini = NULL, *macini = NULL;
914 struct ubsec_session *ses = NULL;
915 int sesn;
916
917 if (sidp == NULL || cri == NULL || sc == NULL)
918 return (EINVAL);
919
920 for (c = cri; c != NULL; c = c->cri_next) {
921 if (c->cri_alg == CRYPTO_MD5_HMAC ||
922 c->cri_alg == CRYPTO_SHA1_HMAC) {
923 if (macini)
924 return (EINVAL);
925 macini = c;
926 } else if (c->cri_alg == CRYPTO_DES_CBC ||
927 c->cri_alg == CRYPTO_3DES_CBC) {
928 if (encini)
929 return (EINVAL);
930 encini = c;
931 } else
932 return (EINVAL);
933 }
934 if (encini == NULL && macini == NULL)
935 return (EINVAL);
936
937 if (sc->sc_sessions == NULL) {
938 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
939 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
940 if (ses == NULL)
941 return (ENOMEM);
942 sesn = 0;
943 sc->sc_nsessions = 1;
944 } else {
945 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
946 if (sc->sc_sessions[sesn].ses_used == 0) {
947 ses = &sc->sc_sessions[sesn];
948 break;
949 }
950 }
951
952 if (ses == NULL) {
953 sesn = sc->sc_nsessions;
954 ses = (struct ubsec_session *)malloc((sesn + 1) *
955 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
956 if (ses == NULL)
957 return (ENOMEM);
958 bcopy(sc->sc_sessions, ses, sesn *
959 sizeof(struct ubsec_session));
960 bzero(sc->sc_sessions, sesn *
961 sizeof(struct ubsec_session));
962 free(sc->sc_sessions, M_DEVBUF);
963 sc->sc_sessions = ses;
964 ses = &sc->sc_sessions[sesn];
965 sc->sc_nsessions++;
966 }
967 }
968 bzero(ses, sizeof(struct ubsec_session));
969 ses->ses_used = 1;
970
971 if (encini) {
972 /* get an IV, network byte order */
973 /* XXX may read fewer than requested */
974 read_random(ses->ses_iv, sizeof(ses->ses_iv));
975
976 if (encini->cri_key != NULL) {
977 ubsec_setup_enckey(ses, encini->cri_alg,
978 encini->cri_key);
979 }
980 }
981
982 if (macini) {
983 ses->ses_mlen = macini->cri_mlen;
984 if (ses->ses_mlen == 0) {
985 if (macini->cri_alg == CRYPTO_MD5_HMAC)
986 ses->ses_mlen = MD5_HASH_LEN;
987 else
988 ses->ses_mlen = SHA1_HASH_LEN;
989 }
990
991 if (macini->cri_key != NULL) {
992 ubsec_setup_mackey(ses, macini->cri_alg,
993 macini->cri_key, macini->cri_klen / 8);
994 }
995 }
996
997 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
998 return (0);
999 }
1000
1001 /*
1002 * Deallocate a session.
1003 */
1004 static int
1005 ubsec_freesession(device_t dev, u_int64_t tid)
1006 {
1007 struct ubsec_softc *sc = device_get_softc(dev);
1008 int session, ret;
1009 u_int32_t sid = CRYPTO_SESID2LID(tid);
1010
1011 if (sc == NULL)
1012 return (EINVAL);
1013
1014 session = UBSEC_SESSION(sid);
1015 if (session < sc->sc_nsessions) {
1016 bzero(&sc->sc_sessions[session],
1017 sizeof(sc->sc_sessions[session]));
1018 ret = 0;
1019 } else
1020 ret = EINVAL;
1021
1022 return (ret);
1023 }
1024
1025 static void
1026 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1027 {
1028 struct ubsec_operand *op = arg;
1029
1030 KASSERT(nsegs <= UBS_MAX_SCATTER,
1031 ("Too many DMA segments returned when mapping operand"));
1032 #ifdef UBSEC_DEBUG
1033 if (ubsec_debug)
1034 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1035 (u_int) mapsize, nsegs, error);
1036 #endif
1037 if (error != 0)
1038 return;
1039 op->mapsize = mapsize;
1040 op->nsegs = nsegs;
1041 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1042 }
1043
1044 static int
1045 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1046 {
1047 struct ubsec_softc *sc = device_get_softc(dev);
1048 struct ubsec_q *q = NULL;
1049 int err = 0, i, j, nicealign;
1050 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1051 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1052 int sskip, dskip, stheend, dtheend;
1053 int16_t coffset;
1054 struct ubsec_session *ses;
1055 struct ubsec_pktctx ctx;
1056 struct ubsec_dma *dmap = NULL;
1057
1058 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1059 ubsecstats.hst_invalid++;
1060 return (EINVAL);
1061 }
1062 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1063 ubsecstats.hst_badsession++;
1064 return (EINVAL);
1065 }
1066
1067 mtx_lock(&sc->sc_freeqlock);
1068 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1069 ubsecstats.hst_queuefull++;
1070 sc->sc_needwakeup |= CRYPTO_SYMQ;
1071 mtx_unlock(&sc->sc_freeqlock);
1072 return (ERESTART);
1073 }
1074 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1075 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1076 mtx_unlock(&sc->sc_freeqlock);
1077
1078 dmap = q->q_dma; /* Save dma pointer */
1079 bzero(q, sizeof(struct ubsec_q));
1080 bzero(&ctx, sizeof(ctx));
1081
1082 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1083 q->q_dma = dmap;
1084 ses = &sc->sc_sessions[q->q_sesn];
1085
1086 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1087 q->q_src_m = (struct mbuf *)crp->crp_buf;
1088 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1089 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1090 q->q_src_io = (struct uio *)crp->crp_buf;
1091 q->q_dst_io = (struct uio *)crp->crp_buf;
1092 } else {
1093 ubsecstats.hst_badflags++;
1094 err = EINVAL;
1095 goto errout; /* XXX we don't handle contiguous blocks! */
1096 }
1097
1098 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1099
1100 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1101 dmap->d_dma->d_mcr.mcr_flags = 0;
1102 q->q_crp = crp;
1103
1104 crd1 = crp->crp_desc;
1105 if (crd1 == NULL) {
1106 ubsecstats.hst_nodesc++;
1107 err = EINVAL;
1108 goto errout;
1109 }
1110 crd2 = crd1->crd_next;
1111
1112 if (crd2 == NULL) {
1113 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1114 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1115 maccrd = crd1;
1116 enccrd = NULL;
1117 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1118 crd1->crd_alg == CRYPTO_3DES_CBC) {
1119 maccrd = NULL;
1120 enccrd = crd1;
1121 } else {
1122 ubsecstats.hst_badalg++;
1123 err = EINVAL;
1124 goto errout;
1125 }
1126 } else {
1127 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1128 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1129 (crd2->crd_alg == CRYPTO_DES_CBC ||
1130 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1131 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1132 maccrd = crd1;
1133 enccrd = crd2;
1134 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1135 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1136 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1137 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1138 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1139 enccrd = crd1;
1140 maccrd = crd2;
1141 } else {
1142 /*
1143 * We cannot order the ubsec as requested
1144 */
1145 ubsecstats.hst_badalg++;
1146 err = EINVAL;
1147 goto errout;
1148 }
1149 }
1150
1151 if (enccrd) {
1152 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1153 ubsec_setup_enckey(ses, enccrd->crd_alg,
1154 enccrd->crd_key);
1155 }
1156
1157 encoffset = enccrd->crd_skip;
1158 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1159
1160 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1161 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1162
1163 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1164 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1165 else {
1166 ctx.pc_iv[0] = ses->ses_iv[0];
1167 ctx.pc_iv[1] = ses->ses_iv[1];
1168 }
1169
1170 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1171 crypto_copyback(crp->crp_flags, crp->crp_buf,
1172 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1173 }
1174 } else {
1175 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1176
1177 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1178 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1179 else {
1180 crypto_copydata(crp->crp_flags, crp->crp_buf,
1181 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1182 }
1183 }
1184
1185 ctx.pc_deskey[0] = ses->ses_deskey[0];
1186 ctx.pc_deskey[1] = ses->ses_deskey[1];
1187 ctx.pc_deskey[2] = ses->ses_deskey[2];
1188 ctx.pc_deskey[3] = ses->ses_deskey[3];
1189 ctx.pc_deskey[4] = ses->ses_deskey[4];
1190 ctx.pc_deskey[5] = ses->ses_deskey[5];
1191 SWAP32(ctx.pc_iv[0]);
1192 SWAP32(ctx.pc_iv[1]);
1193 }
1194
1195 if (maccrd) {
1196 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1197 ubsec_setup_mackey(ses, maccrd->crd_alg,
1198 maccrd->crd_key, maccrd->crd_klen / 8);
1199 }
1200
1201 macoffset = maccrd->crd_skip;
1202
1203 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1204 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1205 else
1206 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1207
1208 for (i = 0; i < 5; i++) {
1209 ctx.pc_hminner[i] = ses->ses_hminner[i];
1210 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1211
1212 HTOLE32(ctx.pc_hminner[i]);
1213 HTOLE32(ctx.pc_hmouter[i]);
1214 }
1215 }
1216
1217 if (enccrd && maccrd) {
1218 /*
1219 * ubsec cannot handle packets where the end of encryption
1220 * and authentication are not the same, or where the
1221 * encrypted part begins before the authenticated part.
1222 */
1223 if ((encoffset + enccrd->crd_len) !=
1224 (macoffset + maccrd->crd_len)) {
1225 ubsecstats.hst_lenmismatch++;
1226 err = EINVAL;
1227 goto errout;
1228 }
1229 if (enccrd->crd_skip < maccrd->crd_skip) {
1230 ubsecstats.hst_skipmismatch++;
1231 err = EINVAL;
1232 goto errout;
1233 }
1234 sskip = maccrd->crd_skip;
1235 cpskip = dskip = enccrd->crd_skip;
1236 stheend = maccrd->crd_len;
1237 dtheend = enccrd->crd_len;
1238 coffset = enccrd->crd_skip - maccrd->crd_skip;
1239 cpoffset = cpskip + dtheend;
1240 #ifdef UBSEC_DEBUG
1241 if (ubsec_debug) {
1242 printf("mac: skip %d, len %d, inject %d\n",
1243 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1244 printf("enc: skip %d, len %d, inject %d\n",
1245 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1246 printf("src: skip %d, len %d\n", sskip, stheend);
1247 printf("dst: skip %d, len %d\n", dskip, dtheend);
1248 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1249 coffset, stheend, cpskip, cpoffset);
1250 }
1251 #endif
1252 } else {
1253 cpskip = dskip = sskip = macoffset + encoffset;
1254 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1255 cpoffset = cpskip + dtheend;
1256 coffset = 0;
1257 }
1258 ctx.pc_offset = htole16(coffset >> 2);
1259
1260 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1261 ubsecstats.hst_nomap++;
1262 err = ENOMEM;
1263 goto errout;
1264 }
1265 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1266 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1267 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1268 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1269 q->q_src_map = NULL;
1270 ubsecstats.hst_noload++;
1271 err = ENOMEM;
1272 goto errout;
1273 }
1274 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1275 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1276 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1277 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1278 q->q_src_map = NULL;
1279 ubsecstats.hst_noload++;
1280 err = ENOMEM;
1281 goto errout;
1282 }
1283 }
1284 nicealign = ubsec_dmamap_aligned(&q->q_src);
1285
1286 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1287
1288 #ifdef UBSEC_DEBUG
1289 if (ubsec_debug)
1290 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1291 #endif
1292 for (i = j = 0; i < q->q_src_nsegs; i++) {
1293 struct ubsec_pktbuf *pb;
1294 bus_size_t packl = q->q_src_segs[i].ds_len;
1295 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1296
1297 if (sskip >= packl) {
1298 sskip -= packl;
1299 continue;
1300 }
1301
1302 packl -= sskip;
1303 packp += sskip;
1304 sskip = 0;
1305
1306 if (packl > 0xfffc) {
1307 err = EIO;
1308 goto errout;
1309 }
1310
1311 if (j == 0)
1312 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1313 else
1314 pb = &dmap->d_dma->d_sbuf[j - 1];
1315
1316 pb->pb_addr = htole32(packp);
1317
1318 if (stheend) {
1319 if (packl > stheend) {
1320 pb->pb_len = htole32(stheend);
1321 stheend = 0;
1322 } else {
1323 pb->pb_len = htole32(packl);
1324 stheend -= packl;
1325 }
1326 } else
1327 pb->pb_len = htole32(packl);
1328
1329 if ((i + 1) == q->q_src_nsegs)
1330 pb->pb_next = 0;
1331 else
1332 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1333 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1334 j++;
1335 }
1336
1337 if (enccrd == NULL && maccrd != NULL) {
1338 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1339 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1340 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1341 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1342 #ifdef UBSEC_DEBUG
1343 if (ubsec_debug)
1344 printf("opkt: %x %x %x\n",
1345 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1346 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1347 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1348 #endif
1349 } else {
1350 if (crp->crp_flags & CRYPTO_F_IOV) {
1351 if (!nicealign) {
1352 ubsecstats.hst_iovmisaligned++;
1353 err = EINVAL;
1354 goto errout;
1355 }
1356 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1357 &q->q_dst_map)) {
1358 ubsecstats.hst_nomap++;
1359 err = ENOMEM;
1360 goto errout;
1361 }
1362 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1363 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1364 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1365 q->q_dst_map = NULL;
1366 ubsecstats.hst_noload++;
1367 err = ENOMEM;
1368 goto errout;
1369 }
1370 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1371 if (nicealign) {
1372 q->q_dst = q->q_src;
1373 } else {
1374 int totlen, len;
1375 struct mbuf *m, *top, **mp;
1376
1377 ubsecstats.hst_unaligned++;
1378 totlen = q->q_src_mapsize;
1379 if (totlen >= MINCLSIZE) {
1380 m = m_getcl(M_DONTWAIT, MT_DATA,
1381 q->q_src_m->m_flags & M_PKTHDR);
1382 len = MCLBYTES;
1383 } else if (q->q_src_m->m_flags & M_PKTHDR) {
1384 m = m_gethdr(M_DONTWAIT, MT_DATA);
1385 len = MHLEN;
1386 } else {
1387 m = m_get(M_DONTWAIT, MT_DATA);
1388 len = MLEN;
1389 }
1390 if (m && q->q_src_m->m_flags & M_PKTHDR &&
1391 !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) {
1392 m_free(m);
1393 m = NULL;
1394 }
1395 if (m == NULL) {
1396 ubsecstats.hst_nombuf++;
1397 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1398 goto errout;
1399 }
1400 m->m_len = len = min(totlen, len);
1401 totlen -= len;
1402 top = m;
1403 mp = ⊤
1404
1405 while (totlen > 0) {
1406 if (totlen >= MINCLSIZE) {
1407 m = m_getcl(M_DONTWAIT,
1408 MT_DATA, 0);
1409 len = MCLBYTES;
1410 } else {
1411 m = m_get(M_DONTWAIT, MT_DATA);
1412 len = MLEN;
1413 }
1414 if (m == NULL) {
1415 m_freem(top);
1416 ubsecstats.hst_nombuf++;
1417 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1418 goto errout;
1419 }
1420 m->m_len = len = min(totlen, len);
1421 totlen -= len;
1422 *mp = m;
1423 mp = &m->m_next;
1424 }
1425 q->q_dst_m = top;
1426 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1427 cpskip, cpoffset);
1428 if (bus_dmamap_create(sc->sc_dmat,
1429 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1430 ubsecstats.hst_nomap++;
1431 err = ENOMEM;
1432 goto errout;
1433 }
1434 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1435 q->q_dst_map, q->q_dst_m,
1436 ubsec_op_cb, &q->q_dst,
1437 BUS_DMA_NOWAIT) != 0) {
1438 bus_dmamap_destroy(sc->sc_dmat,
1439 q->q_dst_map);
1440 q->q_dst_map = NULL;
1441 ubsecstats.hst_noload++;
1442 err = ENOMEM;
1443 goto errout;
1444 }
1445 }
1446 } else {
1447 ubsecstats.hst_badflags++;
1448 err = EINVAL;
1449 goto errout;
1450 }
1451
1452 #ifdef UBSEC_DEBUG
1453 if (ubsec_debug)
1454 printf("dst skip: %d\n", dskip);
1455 #endif
1456 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1457 struct ubsec_pktbuf *pb;
1458 bus_size_t packl = q->q_dst_segs[i].ds_len;
1459 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1460
1461 if (dskip >= packl) {
1462 dskip -= packl;
1463 continue;
1464 }
1465
1466 packl -= dskip;
1467 packp += dskip;
1468 dskip = 0;
1469
1470 if (packl > 0xfffc) {
1471 err = EIO;
1472 goto errout;
1473 }
1474
1475 if (j == 0)
1476 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1477 else
1478 pb = &dmap->d_dma->d_dbuf[j - 1];
1479
1480 pb->pb_addr = htole32(packp);
1481
1482 if (dtheend) {
1483 if (packl > dtheend) {
1484 pb->pb_len = htole32(dtheend);
1485 dtheend = 0;
1486 } else {
1487 pb->pb_len = htole32(packl);
1488 dtheend -= packl;
1489 }
1490 } else
1491 pb->pb_len = htole32(packl);
1492
1493 if ((i + 1) == q->q_dst_nsegs) {
1494 if (maccrd)
1495 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1496 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1497 else
1498 pb->pb_next = 0;
1499 } else
1500 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1501 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1502 j++;
1503 }
1504 }
1505
1506 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1507 offsetof(struct ubsec_dmachunk, d_ctx));
1508
1509 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1510 struct ubsec_pktctx_long *ctxl;
1511
1512 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1513 offsetof(struct ubsec_dmachunk, d_ctx));
1514
1515 /* transform small context into long context */
1516 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1517 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1518 ctxl->pc_flags = ctx.pc_flags;
1519 ctxl->pc_offset = ctx.pc_offset;
1520 for (i = 0; i < 6; i++)
1521 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1522 for (i = 0; i < 5; i++)
1523 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1524 for (i = 0; i < 5; i++)
1525 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1526 ctxl->pc_iv[0] = ctx.pc_iv[0];
1527 ctxl->pc_iv[1] = ctx.pc_iv[1];
1528 } else
1529 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1530 offsetof(struct ubsec_dmachunk, d_ctx),
1531 sizeof(struct ubsec_pktctx));
1532
1533 mtx_lock(&sc->sc_mcr1lock);
1534 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1535 sc->sc_nqueue++;
1536 ubsecstats.hst_ipackets++;
1537 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1538 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1539 ubsec_feed(sc);
1540 mtx_unlock(&sc->sc_mcr1lock);
1541 return (0);
1542
1543 errout:
1544 if (q != NULL) {
1545 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1546 m_freem(q->q_dst_m);
1547
1548 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1549 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1550 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1551 }
1552 if (q->q_src_map != NULL) {
1553 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1554 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1555 }
1556 }
1557 if (q != NULL || err == ERESTART) {
1558 mtx_lock(&sc->sc_freeqlock);
1559 if (q != NULL)
1560 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1561 if (err == ERESTART)
1562 sc->sc_needwakeup |= CRYPTO_SYMQ;
1563 mtx_unlock(&sc->sc_freeqlock);
1564 }
1565 if (err != ERESTART) {
1566 crp->crp_etype = err;
1567 crypto_done(crp);
1568 }
1569 return (err);
1570 }
1571
1572 static void
1573 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1574 {
1575 struct cryptop *crp = (struct cryptop *)q->q_crp;
1576 struct cryptodesc *crd;
1577 struct ubsec_dma *dmap = q->q_dma;
1578
1579 ubsecstats.hst_opackets++;
1580 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1581
1582 ubsec_dma_sync(&dmap->d_alloc,
1583 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1584 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1585 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1586 BUS_DMASYNC_POSTREAD);
1587 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1588 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1589 }
1590 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1591 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1592 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1593
1594 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1595 m_freem(q->q_src_m);
1596 crp->crp_buf = (caddr_t)q->q_dst_m;
1597 }
1598
1599 /* copy out IV for future use */
1600 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1601 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1602 if (crd->crd_alg != CRYPTO_DES_CBC &&
1603 crd->crd_alg != CRYPTO_3DES_CBC)
1604 continue;
1605 crypto_copydata(crp->crp_flags, crp->crp_buf,
1606 crd->crd_skip + crd->crd_len - 8, 8,
1607 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1608 break;
1609 }
1610 }
1611
1612 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1613 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1614 crd->crd_alg != CRYPTO_SHA1_HMAC)
1615 continue;
1616 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1617 sc->sc_sessions[q->q_sesn].ses_mlen,
1618 (caddr_t)dmap->d_dma->d_macbuf);
1619 break;
1620 }
1621 mtx_lock(&sc->sc_freeqlock);
1622 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1623 mtx_unlock(&sc->sc_freeqlock);
1624 crypto_done(crp);
1625 }
1626
1627 static void
1628 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1629 {
1630 int i, j, dlen, slen;
1631 caddr_t dptr, sptr;
1632
1633 j = 0;
1634 sptr = srcm->m_data;
1635 slen = srcm->m_len;
1636 dptr = dstm->m_data;
1637 dlen = dstm->m_len;
1638
1639 while (1) {
1640 for (i = 0; i < min(slen, dlen); i++) {
1641 if (j < hoffset || j >= toffset)
1642 *dptr++ = *sptr++;
1643 slen--;
1644 dlen--;
1645 j++;
1646 }
1647 if (slen == 0) {
1648 srcm = srcm->m_next;
1649 if (srcm == NULL)
1650 return;
1651 sptr = srcm->m_data;
1652 slen = srcm->m_len;
1653 }
1654 if (dlen == 0) {
1655 dstm = dstm->m_next;
1656 if (dstm == NULL)
1657 return;
1658 dptr = dstm->m_data;
1659 dlen = dstm->m_len;
1660 }
1661 }
1662 }
1663
1664 /*
1665 * feed the key generator, must be called at splimp() or higher.
1666 */
1667 static int
1668 ubsec_feed2(struct ubsec_softc *sc)
1669 {
1670 struct ubsec_q2 *q;
1671
1672 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1673 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1674 break;
1675 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1676
1677 ubsec_dma_sync(&q->q_mcr,
1678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1679 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1680
1681 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1682 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1683 --sc->sc_nqueue2;
1684 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1685 }
1686 return (0);
1687 }
1688
1689 /*
1690 * Callback for handling random numbers
1691 */
1692 static void
1693 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1694 {
1695 struct cryptkop *krp;
1696 struct ubsec_ctx_keyop *ctx;
1697
1698 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1699 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1700
1701 switch (q->q_type) {
1702 #ifndef UBSEC_NO_RNG
1703 case UBS_CTXOP_RNGBYPASS: {
1704 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1705
1706 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1707 (*sc->sc_harvest)(sc->sc_rndtest,
1708 rng->rng_buf.dma_vaddr,
1709 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1710 rng->rng_used = 0;
1711 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1712 break;
1713 }
1714 #endif
1715 case UBS_CTXOP_MODEXP: {
1716 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1717 u_int rlen, clen;
1718
1719 krp = me->me_krp;
1720 rlen = (me->me_modbits + 7) / 8;
1721 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1722
1723 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1724 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1725 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1726 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1727
1728 if (clen < rlen)
1729 krp->krp_status = E2BIG;
1730 else {
1731 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1732 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1733 (krp->krp_param[krp->krp_iparams].crp_nbits
1734 + 7) / 8);
1735 bcopy(me->me_C.dma_vaddr,
1736 krp->krp_param[krp->krp_iparams].crp_p,
1737 (me->me_modbits + 7) / 8);
1738 } else
1739 ubsec_kshift_l(me->me_shiftbits,
1740 me->me_C.dma_vaddr, me->me_normbits,
1741 krp->krp_param[krp->krp_iparams].crp_p,
1742 krp->krp_param[krp->krp_iparams].crp_nbits);
1743 }
1744
1745 crypto_kdone(krp);
1746
1747 /* bzero all potentially sensitive data */
1748 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1749 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1750 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1751 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1752
1753 /* Can't free here, so put us on the free list. */
1754 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1755 break;
1756 }
1757 case UBS_CTXOP_RSAPRIV: {
1758 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1759 u_int len;
1760
1761 krp = rp->rpr_krp;
1762 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1763 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1764
1765 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1766 bcopy(rp->rpr_msgout.dma_vaddr,
1767 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1768
1769 crypto_kdone(krp);
1770
1771 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1772 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1773 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1774
1775 /* Can't free here, so put us on the free list. */
1776 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1777 break;
1778 }
1779 default:
1780 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1781 letoh16(ctx->ctx_op));
1782 break;
1783 }
1784 }
1785
1786 #ifndef UBSEC_NO_RNG
1787 static void
1788 ubsec_rng(void *vsc)
1789 {
1790 struct ubsec_softc *sc = vsc;
1791 struct ubsec_q2_rng *rng = &sc->sc_rng;
1792 struct ubsec_mcr *mcr;
1793 struct ubsec_ctx_rngbypass *ctx;
1794
1795 mtx_lock(&sc->sc_mcr2lock);
1796 if (rng->rng_used) {
1797 mtx_unlock(&sc->sc_mcr2lock);
1798 return;
1799 }
1800 sc->sc_nqueue2++;
1801 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1802 goto out;
1803
1804 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1805 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1806
1807 mcr->mcr_pkts = htole16(1);
1808 mcr->mcr_flags = 0;
1809 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1810 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1811 mcr->mcr_ipktbuf.pb_len = 0;
1812 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1813 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1814 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1815 UBS_PKTBUF_LEN);
1816 mcr->mcr_opktbuf.pb_next = 0;
1817
1818 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1819 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1820 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1821
1822 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1823
1824 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1825 rng->rng_used = 1;
1826 ubsec_feed2(sc);
1827 ubsecstats.hst_rng++;
1828 mtx_unlock(&sc->sc_mcr2lock);
1829
1830 return;
1831
1832 out:
1833 /*
1834 * Something weird happened, generate our own call back.
1835 */
1836 sc->sc_nqueue2--;
1837 mtx_unlock(&sc->sc_mcr2lock);
1838 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1839 }
1840 #endif /* UBSEC_NO_RNG */
1841
1842 static void
1843 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1844 {
1845 bus_addr_t *paddr = (bus_addr_t*) arg;
1846 *paddr = segs->ds_addr;
1847 }
1848
1849 static int
1850 ubsec_dma_malloc(
1851 struct ubsec_softc *sc,
1852 bus_size_t size,
1853 struct ubsec_dma_alloc *dma,
1854 int mapflags
1855 )
1856 {
1857 int r;
1858
1859 /* XXX could specify sc_dmat as parent but that just adds overhead */
1860 r = bus_dma_tag_create(NULL, /* parent */
1861 1, 0, /* alignment, bounds */
1862 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1863 BUS_SPACE_MAXADDR, /* highaddr */
1864 NULL, NULL, /* filter, filterarg */
1865 size, /* maxsize */
1866 1, /* nsegments */
1867 size, /* maxsegsize */
1868 BUS_DMA_ALLOCNOW, /* flags */
1869 NULL, NULL, /* lockfunc, lockarg */
1870 &dma->dma_tag);
1871 if (r != 0) {
1872 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1873 "bus_dma_tag_create failed; error %u\n", r);
1874 goto fail_0;
1875 }
1876
1877 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1878 if (r != 0) {
1879 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1880 "bus_dmamap_create failed; error %u\n", r);
1881 goto fail_1;
1882 }
1883
1884 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1885 BUS_DMA_NOWAIT, &dma->dma_map);
1886 if (r != 0) {
1887 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1888 "bus_dmammem_alloc failed; size %zu, error %u\n",
1889 size, r);
1890 goto fail_2;
1891 }
1892
1893 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1894 size,
1895 ubsec_dmamap_cb,
1896 &dma->dma_paddr,
1897 mapflags | BUS_DMA_NOWAIT);
1898 if (r != 0) {
1899 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1900 "bus_dmamap_load failed; error %u\n", r);
1901 goto fail_3;
1902 }
1903
1904 dma->dma_size = size;
1905 return (0);
1906
1907 fail_3:
1908 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1909 fail_2:
1910 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1911 fail_1:
1912 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1913 bus_dma_tag_destroy(dma->dma_tag);
1914 fail_0:
1915 dma->dma_map = NULL;
1916 dma->dma_tag = NULL;
1917 return (r);
1918 }
1919
1920 static void
1921 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1922 {
1923 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1924 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1925 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1926 bus_dma_tag_destroy(dma->dma_tag);
1927 }
1928
1929 /*
1930 * Resets the board. Values in the regesters are left as is
1931 * from the reset (i.e. initial values are assigned elsewhere).
1932 */
1933 static void
1934 ubsec_reset_board(struct ubsec_softc *sc)
1935 {
1936 volatile u_int32_t ctrl;
1937
1938 ctrl = READ_REG(sc, BS_CTRL);
1939 ctrl |= BS_CTRL_RESET;
1940 WRITE_REG(sc, BS_CTRL, ctrl);
1941
1942 /*
1943 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1944 */
1945 DELAY(10);
1946 }
1947
1948 /*
1949 * Init Broadcom registers
1950 */
1951 static void
1952 ubsec_init_board(struct ubsec_softc *sc)
1953 {
1954 u_int32_t ctrl;
1955
1956 ctrl = READ_REG(sc, BS_CTRL);
1957 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1958 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1959
1960 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1961 ctrl |= BS_CTRL_MCR2INT;
1962 else
1963 ctrl &= ~BS_CTRL_MCR2INT;
1964
1965 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1966 ctrl &= ~BS_CTRL_SWNORM;
1967
1968 WRITE_REG(sc, BS_CTRL, ctrl);
1969 }
1970
1971 /*
1972 * Init Broadcom PCI registers
1973 */
1974 static void
1975 ubsec_init_pciregs(device_t dev)
1976 {
1977 #if 0
1978 u_int32_t misc;
1979
1980 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1981 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1982 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1983 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1984 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1985 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1986 #endif
1987
1988 /*
1989 * This will set the cache line size to 1, this will
1990 * force the BCM58xx chip just to do burst read/writes.
1991 * Cache line read/writes are to slow
1992 */
1993 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1994 }
1995
1996 /*
1997 * Clean up after a chip crash.
1998 * It is assumed that the caller in splimp()
1999 */
2000 static void
2001 ubsec_cleanchip(struct ubsec_softc *sc)
2002 {
2003 struct ubsec_q *q;
2004
2005 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2006 q = SIMPLEQ_FIRST(&sc->sc_qchip);
2007 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
2008 ubsec_free_q(sc, q);
2009 }
2010 sc->sc_nqchip = 0;
2011 }
2012
2013 /*
2014 * free a ubsec_q
2015 * It is assumed that the caller is within splimp().
2016 */
2017 static int
2018 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2019 {
2020 struct ubsec_q *q2;
2021 struct cryptop *crp;
2022 int npkts;
2023 int i;
2024
2025 npkts = q->q_nstacked_mcrs;
2026
2027 for (i = 0; i < npkts; i++) {
2028 if(q->q_stacked_mcr[i]) {
2029 q2 = q->q_stacked_mcr[i];
2030
2031 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2032 m_freem(q2->q_dst_m);
2033
2034 crp = (struct cryptop *)q2->q_crp;
2035
2036 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2037
2038 crp->crp_etype = EFAULT;
2039 crypto_done(crp);
2040 } else {
2041 break;
2042 }
2043 }
2044
2045 /*
2046 * Free header MCR
2047 */
2048 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2049 m_freem(q->q_dst_m);
2050
2051 crp = (struct cryptop *)q->q_crp;
2052
2053 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2054
2055 crp->crp_etype = EFAULT;
2056 crypto_done(crp);
2057 return(0);
2058 }
2059
2060 /*
2061 * Routine to reset the chip and clean up.
2062 * It is assumed that the caller is in splimp()
2063 */
2064 static void
2065 ubsec_totalreset(struct ubsec_softc *sc)
2066 {
2067 ubsec_reset_board(sc);
2068 ubsec_init_board(sc);
2069 ubsec_cleanchip(sc);
2070 }
2071
2072 static int
2073 ubsec_dmamap_aligned(struct ubsec_operand *op)
2074 {
2075 int i;
2076
2077 for (i = 0; i < op->nsegs; i++) {
2078 if (op->segs[i].ds_addr & 3)
2079 return (0);
2080 if ((i != (op->nsegs - 1)) &&
2081 (op->segs[i].ds_len & 3))
2082 return (0);
2083 }
2084 return (1);
2085 }
2086
2087 static void
2088 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2089 {
2090 switch (q->q_type) {
2091 case UBS_CTXOP_MODEXP: {
2092 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2093
2094 ubsec_dma_free(sc, &me->me_q.q_mcr);
2095 ubsec_dma_free(sc, &me->me_q.q_ctx);
2096 ubsec_dma_free(sc, &me->me_M);
2097 ubsec_dma_free(sc, &me->me_E);
2098 ubsec_dma_free(sc, &me->me_C);
2099 ubsec_dma_free(sc, &me->me_epb);
2100 free(me, M_DEVBUF);
2101 break;
2102 }
2103 case UBS_CTXOP_RSAPRIV: {
2104 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2105
2106 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2107 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2108 ubsec_dma_free(sc, &rp->rpr_msgin);
2109 ubsec_dma_free(sc, &rp->rpr_msgout);
2110 free(rp, M_DEVBUF);
2111 break;
2112 }
2113 default:
2114 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2115 break;
2116 }
2117 }
2118
2119 static int
2120 ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint)
2121 {
2122 struct ubsec_softc *sc = device_get_softc(dev);
2123 int r;
2124
2125 if (krp == NULL || krp->krp_callback == NULL)
2126 return (EINVAL);
2127
2128 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2129 struct ubsec_q2 *q;
2130
2131 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2132 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2133 ubsec_kfree(sc, q);
2134 }
2135
2136 switch (krp->krp_op) {
2137 case CRK_MOD_EXP:
2138 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2139 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2140 else
2141 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2142 break;
2143 case CRK_MOD_EXP_CRT:
2144 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2145 default:
2146 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2147 krp->krp_op);
2148 krp->krp_status = EOPNOTSUPP;
2149 crypto_kdone(krp);
2150 return (0);
2151 }
2152 return (0); /* silence compiler */
2153 }
2154
2155 /*
2156 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2157 */
2158 static int
2159 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2160 {
2161 struct ubsec_q2_modexp *me;
2162 struct ubsec_mcr *mcr;
2163 struct ubsec_ctx_modexp *ctx;
2164 struct ubsec_pktbuf *epb;
2165 int err = 0;
2166 u_int nbits, normbits, mbits, shiftbits, ebits;
2167
2168 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2169 if (me == NULL) {
2170 err = ENOMEM;
2171 goto errout;
2172 }
2173 bzero(me, sizeof *me);
2174 me->me_krp = krp;
2175 me->me_q.q_type = UBS_CTXOP_MODEXP;
2176
2177 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2178 if (nbits <= 512)
2179 normbits = 512;
2180 else if (nbits <= 768)
2181 normbits = 768;
2182 else if (nbits <= 1024)
2183 normbits = 1024;
2184 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2185 normbits = 1536;
2186 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2187 normbits = 2048;
2188 else {
2189 err = E2BIG;
2190 goto errout;
2191 }
2192
2193 shiftbits = normbits - nbits;
2194
2195 me->me_modbits = nbits;
2196 me->me_shiftbits = shiftbits;
2197 me->me_normbits = normbits;
2198
2199 /* Sanity check: result bits must be >= true modulus bits. */
2200 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2201 err = ERANGE;
2202 goto errout;
2203 }
2204
2205 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2206 &me->me_q.q_mcr, 0)) {
2207 err = ENOMEM;
2208 goto errout;
2209 }
2210 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2211
2212 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2213 &me->me_q.q_ctx, 0)) {
2214 err = ENOMEM;
2215 goto errout;
2216 }
2217
2218 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2219 if (mbits > nbits) {
2220 err = E2BIG;
2221 goto errout;
2222 }
2223 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2224 err = ENOMEM;
2225 goto errout;
2226 }
2227 ubsec_kshift_r(shiftbits,
2228 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2229 me->me_M.dma_vaddr, normbits);
2230
2231 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2232 err = ENOMEM;
2233 goto errout;
2234 }
2235 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2236
2237 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2238 if (ebits > nbits) {
2239 err = E2BIG;
2240 goto errout;
2241 }
2242 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2243 err = ENOMEM;
2244 goto errout;
2245 }
2246 ubsec_kshift_r(shiftbits,
2247 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2248 me->me_E.dma_vaddr, normbits);
2249
2250 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2251 &me->me_epb, 0)) {
2252 err = ENOMEM;
2253 goto errout;
2254 }
2255 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2256 epb->pb_addr = htole32(me->me_E.dma_paddr);
2257 epb->pb_next = 0;
2258 epb->pb_len = htole32(normbits / 8);
2259
2260 #ifdef UBSEC_DEBUG
2261 if (ubsec_debug) {
2262 printf("Epb ");
2263 ubsec_dump_pb(epb);
2264 }
2265 #endif
2266
2267 mcr->mcr_pkts = htole16(1);
2268 mcr->mcr_flags = 0;
2269 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2270 mcr->mcr_reserved = 0;
2271 mcr->mcr_pktlen = 0;
2272
2273 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2274 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2275 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2276
2277 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2278 mcr->mcr_opktbuf.pb_next = 0;
2279 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2280
2281 #ifdef DIAGNOSTIC
2282 /* Misaligned output buffer will hang the chip. */
2283 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2284 panic("%s: modexp invalid addr 0x%x\n",
2285 device_get_nameunit(sc->sc_dev),
2286 letoh32(mcr->mcr_opktbuf.pb_addr));
2287 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2288 panic("%s: modexp invalid len 0x%x\n",
2289 device_get_nameunit(sc->sc_dev),
2290 letoh32(mcr->mcr_opktbuf.pb_len));
2291 #endif
2292
2293 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2294 bzero(ctx, sizeof(*ctx));
2295 ubsec_kshift_r(shiftbits,
2296 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2297 ctx->me_N, normbits);
2298 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2299 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2300 ctx->me_E_len = htole16(nbits);
2301 ctx->me_N_len = htole16(nbits);
2302
2303 #ifdef UBSEC_DEBUG
2304 if (ubsec_debug) {
2305 ubsec_dump_mcr(mcr);
2306 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2307 }
2308 #endif
2309
2310 /*
2311 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2312 * everything else.
2313 */
2314 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2315 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2316 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2317 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2318
2319 /* Enqueue and we're done... */
2320 mtx_lock(&sc->sc_mcr2lock);
2321 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2322 ubsec_feed2(sc);
2323 ubsecstats.hst_modexp++;
2324 mtx_unlock(&sc->sc_mcr2lock);
2325
2326 return (0);
2327
2328 errout:
2329 if (me != NULL) {
2330 if (me->me_q.q_mcr.dma_map != NULL)
2331 ubsec_dma_free(sc, &me->me_q.q_mcr);
2332 if (me->me_q.q_ctx.dma_map != NULL) {
2333 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2334 ubsec_dma_free(sc, &me->me_q.q_ctx);
2335 }
2336 if (me->me_M.dma_map != NULL) {
2337 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2338 ubsec_dma_free(sc, &me->me_M);
2339 }
2340 if (me->me_E.dma_map != NULL) {
2341 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2342 ubsec_dma_free(sc, &me->me_E);
2343 }
2344 if (me->me_C.dma_map != NULL) {
2345 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2346 ubsec_dma_free(sc, &me->me_C);
2347 }
2348 if (me->me_epb.dma_map != NULL)
2349 ubsec_dma_free(sc, &me->me_epb);
2350 free(me, M_DEVBUF);
2351 }
2352 krp->krp_status = err;
2353 crypto_kdone(krp);
2354 return (0);
2355 }
2356
2357 /*
2358 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2359 */
2360 static int
2361 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2362 {
2363 struct ubsec_q2_modexp *me;
2364 struct ubsec_mcr *mcr;
2365 struct ubsec_ctx_modexp *ctx;
2366 struct ubsec_pktbuf *epb;
2367 int err = 0;
2368 u_int nbits, normbits, mbits, shiftbits, ebits;
2369
2370 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2371 if (me == NULL) {
2372 err = ENOMEM;
2373 goto errout;
2374 }
2375 bzero(me, sizeof *me);
2376 me->me_krp = krp;
2377 me->me_q.q_type = UBS_CTXOP_MODEXP;
2378
2379 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2380 if (nbits <= 512)
2381 normbits = 512;
2382 else if (nbits <= 768)
2383 normbits = 768;
2384 else if (nbits <= 1024)
2385 normbits = 1024;
2386 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2387 normbits = 1536;
2388 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2389 normbits = 2048;
2390 else {
2391 err = E2BIG;
2392 goto errout;
2393 }
2394
2395 shiftbits = normbits - nbits;
2396
2397 /* XXX ??? */
2398 me->me_modbits = nbits;
2399 me->me_shiftbits = shiftbits;
2400 me->me_normbits = normbits;
2401
2402 /* Sanity check: result bits must be >= true modulus bits. */
2403 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2404 err = ERANGE;
2405 goto errout;
2406 }
2407
2408 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2409 &me->me_q.q_mcr, 0)) {
2410 err = ENOMEM;
2411 goto errout;
2412 }
2413 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2414
2415 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2416 &me->me_q.q_ctx, 0)) {
2417 err = ENOMEM;
2418 goto errout;
2419 }
2420
2421 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2422 if (mbits > nbits) {
2423 err = E2BIG;
2424 goto errout;
2425 }
2426 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2427 err = ENOMEM;
2428 goto errout;
2429 }
2430 bzero(me->me_M.dma_vaddr, normbits / 8);
2431 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2432 me->me_M.dma_vaddr, (mbits + 7) / 8);
2433
2434 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2435 err = ENOMEM;
2436 goto errout;
2437 }
2438 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2439
2440 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2441 if (ebits > nbits) {
2442 err = E2BIG;
2443 goto errout;
2444 }
2445 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2446 err = ENOMEM;
2447 goto errout;
2448 }
2449 bzero(me->me_E.dma_vaddr, normbits / 8);
2450 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2451 me->me_E.dma_vaddr, (ebits + 7) / 8);
2452
2453 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2454 &me->me_epb, 0)) {
2455 err = ENOMEM;
2456 goto errout;
2457 }
2458 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2459 epb->pb_addr = htole32(me->me_E.dma_paddr);
2460 epb->pb_next = 0;
2461 epb->pb_len = htole32((ebits + 7) / 8);
2462
2463 #ifdef UBSEC_DEBUG
2464 if (ubsec_debug) {
2465 printf("Epb ");
2466 ubsec_dump_pb(epb);
2467 }
2468 #endif
2469
2470 mcr->mcr_pkts = htole16(1);
2471 mcr->mcr_flags = 0;
2472 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2473 mcr->mcr_reserved = 0;
2474 mcr->mcr_pktlen = 0;
2475
2476 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2477 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2478 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2479
2480 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2481 mcr->mcr_opktbuf.pb_next = 0;
2482 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2483
2484 #ifdef DIAGNOSTIC
2485 /* Misaligned output buffer will hang the chip. */
2486 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2487 panic("%s: modexp invalid addr 0x%x\n",
2488 device_get_nameunit(sc->sc_dev),
2489 letoh32(mcr->mcr_opktbuf.pb_addr));
2490 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2491 panic("%s: modexp invalid len 0x%x\n",
2492 device_get_nameunit(sc->sc_dev),
2493 letoh32(mcr->mcr_opktbuf.pb_len));
2494 #endif
2495
2496 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2497 bzero(ctx, sizeof(*ctx));
2498 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2499 (nbits + 7) / 8);
2500 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2501 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2502 ctx->me_E_len = htole16(ebits);
2503 ctx->me_N_len = htole16(nbits);
2504
2505 #ifdef UBSEC_DEBUG
2506 if (ubsec_debug) {
2507 ubsec_dump_mcr(mcr);
2508 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2509 }
2510 #endif
2511
2512 /*
2513 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2514 * everything else.
2515 */
2516 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2517 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2518 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2519 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2520
2521 /* Enqueue and we're done... */
2522 mtx_lock(&sc->sc_mcr2lock);
2523 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2524 ubsec_feed2(sc);
2525 mtx_unlock(&sc->sc_mcr2lock);
2526
2527 return (0);
2528
2529 errout:
2530 if (me != NULL) {
2531 if (me->me_q.q_mcr.dma_map != NULL)
2532 ubsec_dma_free(sc, &me->me_q.q_mcr);
2533 if (me->me_q.q_ctx.dma_map != NULL) {
2534 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2535 ubsec_dma_free(sc, &me->me_q.q_ctx);
2536 }
2537 if (me->me_M.dma_map != NULL) {
2538 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2539 ubsec_dma_free(sc, &me->me_M);
2540 }
2541 if (me->me_E.dma_map != NULL) {
2542 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2543 ubsec_dma_free(sc, &me->me_E);
2544 }
2545 if (me->me_C.dma_map != NULL) {
2546 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2547 ubsec_dma_free(sc, &me->me_C);
2548 }
2549 if (me->me_epb.dma_map != NULL)
2550 ubsec_dma_free(sc, &me->me_epb);
2551 free(me, M_DEVBUF);
2552 }
2553 krp->krp_status = err;
2554 crypto_kdone(krp);
2555 return (0);
2556 }
2557
2558 static int
2559 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2560 {
2561 struct ubsec_q2_rsapriv *rp = NULL;
2562 struct ubsec_mcr *mcr;
2563 struct ubsec_ctx_rsapriv *ctx;
2564 int err = 0;
2565 u_int padlen, msglen;
2566
2567 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2568 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2569 if (msglen > padlen)
2570 padlen = msglen;
2571
2572 if (padlen <= 256)
2573 padlen = 256;
2574 else if (padlen <= 384)
2575 padlen = 384;
2576 else if (padlen <= 512)
2577 padlen = 512;
2578 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2579 padlen = 768;
2580 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2581 padlen = 1024;
2582 else {
2583 err = E2BIG;
2584 goto errout;
2585 }
2586
2587 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2588 err = E2BIG;
2589 goto errout;
2590 }
2591
2592 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2593 err = E2BIG;
2594 goto errout;
2595 }
2596
2597 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2598 err = E2BIG;
2599 goto errout;
2600 }
2601
2602 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2603 if (rp == NULL)
2604 return (ENOMEM);
2605 bzero(rp, sizeof *rp);
2606 rp->rpr_krp = krp;
2607 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2608
2609 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2610 &rp->rpr_q.q_mcr, 0)) {
2611 err = ENOMEM;
2612 goto errout;
2613 }
2614 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2615
2616 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2617 &rp->rpr_q.q_ctx, 0)) {
2618 err = ENOMEM;
2619 goto errout;
2620 }
2621 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2622 bzero(ctx, sizeof *ctx);
2623
2624 /* Copy in p */
2625 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2626 &ctx->rpr_buf[0 * (padlen / 8)],
2627 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2628
2629 /* Copy in q */
2630 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2631 &ctx->rpr_buf[1 * (padlen / 8)],
2632 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2633
2634 /* Copy in dp */
2635 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2636 &ctx->rpr_buf[2 * (padlen / 8)],
2637 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2638
2639 /* Copy in dq */
2640 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2641 &ctx->rpr_buf[3 * (padlen / 8)],
2642 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2643
2644 /* Copy in pinv */
2645 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2646 &ctx->rpr_buf[4 * (padlen / 8)],
2647 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2648
2649 msglen = padlen * 2;
2650
2651 /* Copy in input message (aligned buffer/length). */
2652 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2653 /* Is this likely? */
2654 err = E2BIG;
2655 goto errout;
2656 }
2657 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2658 err = ENOMEM;
2659 goto errout;
2660 }
2661 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2662 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2663 rp->rpr_msgin.dma_vaddr,
2664 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2665
2666 /* Prepare space for output message (aligned buffer/length). */
2667 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2668 /* Is this likely? */
2669 err = E2BIG;
2670 goto errout;
2671 }
2672 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2673 err = ENOMEM;
2674 goto errout;
2675 }
2676 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2677
2678 mcr->mcr_pkts = htole16(1);
2679 mcr->mcr_flags = 0;
2680 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2681 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2682 mcr->mcr_ipktbuf.pb_next = 0;
2683 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2684 mcr->mcr_reserved = 0;
2685 mcr->mcr_pktlen = htole16(msglen);
2686 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2687 mcr->mcr_opktbuf.pb_next = 0;
2688 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2689
2690 #ifdef DIAGNOSTIC
2691 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2692 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2693 device_get_nameunit(sc->sc_dev),
2694 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2695 }
2696 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2697 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2698 device_get_nameunit(sc->sc_dev),
2699 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2700 }
2701 #endif
2702
2703 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2704 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2705 ctx->rpr_q_len = htole16(padlen);
2706 ctx->rpr_p_len = htole16(padlen);
2707
2708 /*
2709 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2710 * everything else.
2711 */
2712 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2713 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2714
2715 /* Enqueue and we're done... */
2716 mtx_lock(&sc->sc_mcr2lock);
2717 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2718 ubsec_feed2(sc);
2719 ubsecstats.hst_modexpcrt++;
2720 mtx_unlock(&sc->sc_mcr2lock);
2721 return (0);
2722
2723 errout:
2724 if (rp != NULL) {
2725 if (rp->rpr_q.q_mcr.dma_map != NULL)
2726 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2727 if (rp->rpr_msgin.dma_map != NULL) {
2728 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2729 ubsec_dma_free(sc, &rp->rpr_msgin);
2730 }
2731 if (rp->rpr_msgout.dma_map != NULL) {
2732 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2733 ubsec_dma_free(sc, &rp->rpr_msgout);
2734 }
2735 free(rp, M_DEVBUF);
2736 }
2737 krp->krp_status = err;
2738 crypto_kdone(krp);
2739 return (0);
2740 }
2741
2742 #ifdef UBSEC_DEBUG
2743 static void
2744 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2745 {
2746 printf("addr 0x%x (0x%x) next 0x%x\n",
2747 pb->pb_addr, pb->pb_len, pb->pb_next);
2748 }
2749
2750 static void
2751 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2752 {
2753 printf("CTX (0x%x):\n", c->ctx_len);
2754 switch (letoh16(c->ctx_op)) {
2755 case UBS_CTXOP_RNGBYPASS:
2756 case UBS_CTXOP_RNGSHA1:
2757 break;
2758 case UBS_CTXOP_MODEXP:
2759 {
2760 struct ubsec_ctx_modexp *cx = (void *)c;
2761 int i, len;
2762
2763 printf(" Elen %u, Nlen %u\n",
2764 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2765 len = (cx->me_N_len + 7)/8;
2766 for (i = 0; i < len; i++)
2767 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2768 printf("\n");
2769 break;
2770 }
2771 default:
2772 printf("unknown context: %x\n", c->ctx_op);
2773 }
2774 printf("END CTX\n");
2775 }
2776
2777 static void
2778 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2779 {
2780 volatile struct ubsec_mcr_add *ma;
2781 int i;
2782
2783 printf("MCR:\n");
2784 printf(" pkts: %u, flags 0x%x\n",
2785 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2786 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2787 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2788 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2789 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2790 letoh16(ma->mcr_reserved));
2791 printf(" %d: ipkt ", i);
2792 ubsec_dump_pb(&ma->mcr_ipktbuf);
2793 printf(" %d: opkt ", i);
2794 ubsec_dump_pb(&ma->mcr_opktbuf);
2795 ma++;
2796 }
2797 printf("END MCR\n");
2798 }
2799 #endif /* UBSEC_DEBUG */
2800
2801 /*
2802 * Return the number of significant bits of a big number.
2803 */
2804 static int
2805 ubsec_ksigbits(struct crparam *cr)
2806 {
2807 u_int plen = (cr->crp_nbits + 7) / 8;
2808 int i, sig = plen * 8;
2809 u_int8_t c, *p = cr->crp_p;
2810
2811 for (i = plen - 1; i >= 0; i--) {
2812 c = p[i];
2813 if (c != 0) {
2814 while ((c & 0x80) == 0) {
2815 sig--;
2816 c <<= 1;
2817 }
2818 break;
2819 }
2820 sig -= 8;
2821 }
2822 return (sig);
2823 }
2824
2825 static void
2826 ubsec_kshift_r(
2827 u_int shiftbits,
2828 u_int8_t *src, u_int srcbits,
2829 u_int8_t *dst, u_int dstbits)
2830 {
2831 u_int slen, dlen;
2832 int i, si, di, n;
2833
2834 slen = (srcbits + 7) / 8;
2835 dlen = (dstbits + 7) / 8;
2836
2837 for (i = 0; i < slen; i++)
2838 dst[i] = src[i];
2839 for (i = 0; i < dlen - slen; i++)
2840 dst[slen + i] = 0;
2841
2842 n = shiftbits / 8;
2843 if (n != 0) {
2844 si = dlen - n - 1;
2845 di = dlen - 1;
2846 while (si >= 0)
2847 dst[di--] = dst[si--];
2848 while (di >= 0)
2849 dst[di--] = 0;
2850 }
2851
2852 n = shiftbits % 8;
2853 if (n != 0) {
2854 for (i = dlen - 1; i > 0; i--)
2855 dst[i] = (dst[i] << n) |
2856 (dst[i - 1] >> (8 - n));
2857 dst[0] = dst[0] << n;
2858 }
2859 }
2860
2861 static void
2862 ubsec_kshift_l(
2863 u_int shiftbits,
2864 u_int8_t *src, u_int srcbits,
2865 u_int8_t *dst, u_int dstbits)
2866 {
2867 int slen, dlen, i, n;
2868
2869 slen = (srcbits + 7) / 8;
2870 dlen = (dstbits + 7) / 8;
2871
2872 n = shiftbits / 8;
2873 for (i = 0; i < slen; i++)
2874 dst[i] = src[i + n];
2875 for (i = 0; i < dlen - slen; i++)
2876 dst[slen + i] = 0;
2877
2878 n = shiftbits % 8;
2879 if (n != 0) {
2880 for (i = 0; i < (dlen - 1); i++)
2881 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2882 dst[dlen - 1] = dst[dlen - 1] >> n;
2883 }
2884 }
Cache object: 76dce057f6c0f3a9cb7545f39f5a4509
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