The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ubsec/ubsecvar.h

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    1 /* $FreeBSD$ */
    2 /*      $OpenBSD: ubsecvar.h,v 1.35 2002/09/24 18:33:26 jason Exp $     */
    3 
    4 /*-
    5  * SPDX-License-Identifier: BSD-3-Clause
    6  *
    7  * Copyright (c) 2000 Theo de Raadt
    8  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  *
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. The name of the author may not be used to endorse or promote products
   20  *    derived from this software without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * Effort sponsored in part by the Defense Advanced Research Projects
   34  * Agency (DARPA) and Air Force Research Laboratory, Air Force
   35  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
   36  *
   37  */
   38 
   39 /* Maximum queue length */
   40 #ifndef UBS_MAX_NQUEUE
   41 #define UBS_MAX_NQUEUE          60
   42 #endif
   43 
   44 #define UBS_MAX_SCATTER         64      /* Maximum scatter/gather depth */
   45 
   46 #ifndef UBS_MAX_AGGR
   47 #define UBS_MAX_AGGR            5       /* Maximum aggregation count */
   48 #endif
   49 
   50 #define UBS_DEF_RTY             0xff    /* PCI Retry Timeout */
   51 #define UBS_DEF_TOUT            0xff    /* PCI TRDY Timeout */
   52 #define UBS_DEF_CACHELINE       0x01    /* Cache Line setting */
   53 
   54 #ifdef _KERNEL
   55 
   56 struct ubsec_dma_alloc {
   57         u_int32_t               dma_paddr;
   58         caddr_t                 dma_vaddr;
   59         bus_dma_tag_t           dma_tag;
   60         bus_dmamap_t            dma_map;
   61         bus_dma_segment_t       dma_seg;
   62         bus_size_t              dma_size;
   63         int                     dma_nseg;
   64 };
   65 
   66 struct ubsec_q2 {
   67         SIMPLEQ_ENTRY(ubsec_q2)         q_next;
   68         struct ubsec_dma_alloc          q_mcr;
   69         struct ubsec_dma_alloc          q_ctx;
   70         u_int                           q_type;
   71 };
   72 
   73 struct ubsec_q2_rng {
   74         struct ubsec_q2                 rng_q;
   75         struct ubsec_dma_alloc          rng_buf;
   76         int                             rng_used;
   77 };
   78 
   79 /* C = (M ^ E) mod N */
   80 #define UBS_MODEXP_PAR_M        0
   81 #define UBS_MODEXP_PAR_E        1
   82 #define UBS_MODEXP_PAR_N        2
   83 #define UBS_MODEXP_PAR_C        3
   84 struct ubsec_q2_modexp {
   85         struct ubsec_q2                 me_q;
   86         struct cryptkop *               me_krp;
   87         struct ubsec_dma_alloc          me_M;
   88         struct ubsec_dma_alloc          me_E;
   89         struct ubsec_dma_alloc          me_C;
   90         struct ubsec_dma_alloc          me_epb;
   91         int                             me_modbits;
   92         int                             me_shiftbits;
   93         int                             me_normbits;
   94 };
   95 
   96 #define UBS_RSAPRIV_PAR_P       0
   97 #define UBS_RSAPRIV_PAR_Q       1
   98 #define UBS_RSAPRIV_PAR_DP      2
   99 #define UBS_RSAPRIV_PAR_DQ      3
  100 #define UBS_RSAPRIV_PAR_PINV    4
  101 #define UBS_RSAPRIV_PAR_MSGIN   5
  102 #define UBS_RSAPRIV_PAR_MSGOUT  6
  103 struct ubsec_q2_rsapriv {
  104         struct ubsec_q2                 rpr_q;
  105         struct cryptkop *               rpr_krp;
  106         struct ubsec_dma_alloc          rpr_msgin;
  107         struct ubsec_dma_alloc          rpr_msgout;
  108 };
  109 
  110 #define UBSEC_RNG_BUFSIZ        16              /* measured in 32bit words */
  111 
  112 struct ubsec_dmachunk {
  113         struct ubsec_mcr        d_mcr;
  114         struct ubsec_mcr_add    d_mcradd[UBS_MAX_AGGR-1];
  115         struct ubsec_pktbuf     d_sbuf[UBS_MAX_SCATTER-1];
  116         struct ubsec_pktbuf     d_dbuf[UBS_MAX_SCATTER-1];
  117         u_int32_t               d_macbuf[5];
  118         union {
  119                 struct ubsec_pktctx_long        ctxl;
  120                 struct ubsec_pktctx             ctx;
  121         } d_ctx;
  122 };
  123 
  124 struct ubsec_dma {
  125         SIMPLEQ_ENTRY(ubsec_dma)        d_next;
  126         struct ubsec_dmachunk           *d_dma;
  127         struct ubsec_dma_alloc          d_alloc;
  128 };
  129 
  130 #define UBS_FLAGS_KEY           0x01            /* has key accelerator */
  131 #define UBS_FLAGS_LONGCTX       0x02            /* uses long ipsec ctx */
  132 #define UBS_FLAGS_BIGKEY        0x04            /* 2048bit keys */
  133 #define UBS_FLAGS_HWNORM        0x08            /* hardware normalization */
  134 #define UBS_FLAGS_RNG           0x10            /* hardware rng */
  135 
  136 struct ubsec_operand {
  137         union {
  138                 struct mbuf *m;
  139                 struct uio *io;
  140         } u;
  141         bus_dmamap_t            map;
  142         bus_size_t              mapsize;
  143         int                     nsegs;
  144         bus_dma_segment_t       segs[UBS_MAX_SCATTER];
  145 };
  146 
  147 struct ubsec_q {
  148         SIMPLEQ_ENTRY(ubsec_q)          q_next;
  149         int                             q_nstacked_mcrs;
  150         struct ubsec_q                  *q_stacked_mcr[UBS_MAX_AGGR-1];
  151         struct cryptop                  *q_crp;
  152         struct ubsec_dma                *q_dma;
  153 
  154         struct ubsec_operand            q_src;
  155         struct ubsec_operand            q_dst;
  156 
  157         int                             q_flags;
  158 };
  159 
  160 #define q_src_m         q_src.u.m
  161 #define q_src_io        q_src.u.io
  162 #define q_src_map       q_src.map
  163 #define q_src_nsegs     q_src.nsegs
  164 #define q_src_segs      q_src.segs
  165 #define q_src_mapsize   q_src.mapsize
  166 
  167 #define q_dst_m         q_dst.u.m
  168 #define q_dst_io        q_dst.u.io
  169 #define q_dst_map       q_dst.map
  170 #define q_dst_nsegs     q_dst.nsegs
  171 #define q_dst_segs      q_dst.segs
  172 #define q_dst_mapsize   q_dst.mapsize
  173 
  174 struct rndstate_test;
  175 
  176 struct ubsec_softc {
  177         device_t                sc_dev;         /* device backpointer */
  178         struct resource         *sc_irq;
  179         void                    *sc_ih;         /* interrupt handler cookie */
  180         bus_space_handle_t      sc_sh;          /* memory handle */
  181         bus_space_tag_t         sc_st;          /* memory tag */
  182         struct resource         *sc_sr;         /* memory resource */
  183         bus_dma_tag_t           sc_dmat;        /* dma tag */
  184         int                     sc_flags;       /* device specific flags */
  185         int                     sc_suspended;
  186         int                     sc_needwakeup;  /* notify crypto layer */
  187         u_int32_t               sc_statmask;    /* interrupt status mask */
  188         int32_t                 sc_cid;         /* crypto tag */
  189         struct mtx              sc_mcr1lock;    /* mcr1 operation lock */
  190         SIMPLEQ_HEAD(,ubsec_q)  sc_queue;       /* packet queue, mcr1 */
  191         int                     sc_nqueue;      /* count enqueued, mcr1 */
  192         SIMPLEQ_HEAD(,ubsec_q)  sc_qchip;       /* on chip, mcr1 */
  193         int                     sc_nqchip;      /* count on chip, mcr1 */
  194         struct mtx              sc_freeqlock;   /* freequeue lock */
  195         SIMPLEQ_HEAD(,ubsec_q)  sc_freequeue;   /* list of free queue elements */
  196         struct mtx              sc_mcr2lock;    /* mcr2 operation lock */
  197         SIMPLEQ_HEAD(,ubsec_q2) sc_queue2;      /* packet queue, mcr2 */
  198         int                     sc_nqueue2;     /* count enqueued, mcr2 */
  199         SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2;      /* on chip, mcr2 */
  200         struct callout          sc_rngto;       /* rng timeout */
  201         int                     sc_rnghz;       /* rng poll time */
  202         struct ubsec_q2_rng     sc_rng;
  203         struct rndtest_state    *sc_rndtest;    /* RNG test state */
  204         void                    (*sc_harvest)(struct rndtest_state *,
  205                                         void *, u_int);
  206         struct ubsec_dma        sc_dmaa[UBS_MAX_NQUEUE];
  207         struct ubsec_q          *sc_queuea[UBS_MAX_NQUEUE];
  208         SIMPLEQ_HEAD(,ubsec_q2) sc_q2free;      /* free list */
  209 };
  210 
  211 #define UBSEC_QFLAGS_COPYOUTIV          0x1
  212 
  213 struct ubsec_session {
  214         u_int32_t       ses_deskey[6];          /* 3DES key */
  215         u_int32_t       ses_mlen;               /* hmac length */
  216         u_int32_t       ses_hminner[5];         /* hmac inner state */
  217         u_int32_t       ses_hmouter[5];         /* hmac outer state */
  218         u_int32_t       ses_iv[2];              /* [3]DES iv */
  219 };
  220 #endif /* _KERNEL */
  221 
  222 struct ubsec_stats {
  223         u_int64_t hst_ibytes;
  224         u_int64_t hst_obytes;
  225         u_int32_t hst_ipackets;
  226         u_int32_t hst_opackets;
  227         u_int32_t hst_invalid;          /* invalid argument */
  228         u_int32_t hst_badsession;       /* invalid session id */
  229         u_int32_t hst_badflags;         /* flags indicate !(mbuf | uio) */
  230         u_int32_t hst_nodesc;           /* op submitted w/o descriptors */
  231         u_int32_t hst_badalg;           /* unsupported algorithm */
  232         u_int32_t hst_nomem;
  233         u_int32_t hst_queuefull;
  234         u_int32_t hst_dmaerr;
  235         u_int32_t hst_mcrerr;
  236         u_int32_t hst_nodmafree;
  237         u_int32_t hst_lenmismatch;      /* enc/auth lengths different */
  238         u_int32_t hst_skipmismatch;     /* enc part begins before auth part */
  239         u_int32_t hst_iovmisaligned;    /* iov op not aligned */
  240         u_int32_t hst_noirq;            /* IRQ for no reason */
  241         u_int32_t hst_unaligned;        /* unaligned src caused copy */
  242         u_int32_t hst_nomap;            /* bus_dmamap_create failed */
  243         u_int32_t hst_noload;           /* bus_dmamap_load_* failed */
  244         u_int32_t hst_nombuf;           /* MGET* failed */
  245         u_int32_t hst_nomcl;            /* MCLGET* failed */
  246         u_int32_t hst_totbatch;         /* ops submitted w/o interrupt */
  247         u_int32_t hst_maxbatch;         /* max ops submitted together */
  248         u_int32_t hst_maxqueue;         /* max ops queued for submission */
  249         u_int32_t hst_maxqchip;         /* max mcr1 ops out for processing */
  250         u_int32_t hst_mcr1full;         /* MCR1 too busy to take ops */
  251         u_int32_t hst_rng;              /* RNG requests */
  252         u_int32_t hst_modexp;           /* MOD EXP requests */
  253         u_int32_t hst_modexpcrt;        /* MOD EXP CRT requests */
  254 };

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