The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ubsec/ubsecvar.h

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    1 /* $FreeBSD: releng/6.0/sys/dev/ubsec/ubsecvar.h 139749 2005-01-06 01:43:34Z imp $ */
    2 /*      $OpenBSD: ubsecvar.h,v 1.35 2002/09/24 18:33:26 jason Exp $     */
    3 
    4 /*-
    5  * Copyright (c) 2000 Theo de Raadt
    6  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  *
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   30  *
   31  * Effort sponsored in part by the Defense Advanced Research Projects
   32  * Agency (DARPA) and Air Force Research Laboratory, Air Force
   33  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
   34  *
   35  */
   36 
   37 /* Maximum queue length */
   38 #ifndef UBS_MAX_NQUEUE
   39 #define UBS_MAX_NQUEUE          60
   40 #endif
   41 
   42 #define UBS_MAX_SCATTER         64      /* Maximum scatter/gather depth */
   43 
   44 #ifndef UBS_MAX_AGGR
   45 #define UBS_MAX_AGGR            5       /* Maximum aggregation count */
   46 #endif
   47 
   48 #define UBSEC_CARD(sid)         (((sid) & 0xf0000000) >> 28)
   49 #define UBSEC_SESSION(sid)      ( (sid) & 0x0fffffff)
   50 #define UBSEC_SID(crd, sesn)    (((crd) << 28) | ((sesn) & 0x0fffffff))
   51 
   52 #define UBS_DEF_RTY             0xff    /* PCI Retry Timeout */
   53 #define UBS_DEF_TOUT            0xff    /* PCI TRDY Timeout */
   54 #define UBS_DEF_CACHELINE       0x01    /* Cache Line setting */
   55 
   56 #ifdef _KERNEL
   57 
   58 struct ubsec_dma_alloc {
   59         u_int32_t               dma_paddr;
   60         caddr_t                 dma_vaddr;
   61         bus_dma_tag_t           dma_tag;
   62         bus_dmamap_t            dma_map;
   63         bus_dma_segment_t       dma_seg;
   64         bus_size_t              dma_size;
   65         int                     dma_nseg;
   66 };
   67 
   68 struct ubsec_q2 {
   69         SIMPLEQ_ENTRY(ubsec_q2)         q_next;
   70         struct ubsec_dma_alloc          q_mcr;
   71         struct ubsec_dma_alloc          q_ctx;
   72         u_int                           q_type;
   73 };
   74 
   75 struct ubsec_q2_rng {
   76         struct ubsec_q2                 rng_q;
   77         struct ubsec_dma_alloc          rng_buf;
   78         int                             rng_used;
   79 };
   80 
   81 /* C = (M ^ E) mod N */
   82 #define UBS_MODEXP_PAR_M        0
   83 #define UBS_MODEXP_PAR_E        1
   84 #define UBS_MODEXP_PAR_N        2
   85 #define UBS_MODEXP_PAR_C        3
   86 struct ubsec_q2_modexp {
   87         struct ubsec_q2                 me_q;
   88         struct cryptkop *               me_krp;
   89         struct ubsec_dma_alloc          me_M;
   90         struct ubsec_dma_alloc          me_E;
   91         struct ubsec_dma_alloc          me_C;
   92         struct ubsec_dma_alloc          me_epb;
   93         int                             me_modbits;
   94         int                             me_shiftbits;
   95         int                             me_normbits;
   96 };
   97 
   98 #define UBS_RSAPRIV_PAR_P       0
   99 #define UBS_RSAPRIV_PAR_Q       1
  100 #define UBS_RSAPRIV_PAR_DP      2
  101 #define UBS_RSAPRIV_PAR_DQ      3
  102 #define UBS_RSAPRIV_PAR_PINV    4
  103 #define UBS_RSAPRIV_PAR_MSGIN   5
  104 #define UBS_RSAPRIV_PAR_MSGOUT  6
  105 struct ubsec_q2_rsapriv {
  106         struct ubsec_q2                 rpr_q;
  107         struct cryptkop *               rpr_krp;
  108         struct ubsec_dma_alloc          rpr_msgin;
  109         struct ubsec_dma_alloc          rpr_msgout;
  110 };
  111 
  112 #define UBSEC_RNG_BUFSIZ        16              /* measured in 32bit words */
  113 
  114 struct ubsec_dmachunk {
  115         struct ubsec_mcr        d_mcr;
  116         struct ubsec_mcr_add    d_mcradd[UBS_MAX_AGGR-1];
  117         struct ubsec_pktbuf     d_sbuf[UBS_MAX_SCATTER-1];
  118         struct ubsec_pktbuf     d_dbuf[UBS_MAX_SCATTER-1];
  119         u_int32_t               d_macbuf[5];
  120         union {
  121                 struct ubsec_pktctx_long        ctxl;
  122                 struct ubsec_pktctx             ctx;
  123         } d_ctx;
  124 };
  125 
  126 struct ubsec_dma {
  127         SIMPLEQ_ENTRY(ubsec_dma)        d_next;
  128         struct ubsec_dmachunk           *d_dma;
  129         struct ubsec_dma_alloc          d_alloc;
  130 };
  131 
  132 #define UBS_FLAGS_KEY           0x01            /* has key accelerator */
  133 #define UBS_FLAGS_LONGCTX       0x02            /* uses long ipsec ctx */
  134 #define UBS_FLAGS_BIGKEY        0x04            /* 2048bit keys */
  135 #define UBS_FLAGS_HWNORM        0x08            /* hardware normalization */
  136 #define UBS_FLAGS_RNG           0x10            /* hardware rng */
  137 
  138 struct ubsec_operand {
  139         union {
  140                 struct mbuf *m;
  141                 struct uio *io;
  142         } u;
  143         bus_dmamap_t            map;
  144         bus_size_t              mapsize;
  145         int                     nsegs;
  146         bus_dma_segment_t       segs[UBS_MAX_SCATTER];
  147 };
  148 
  149 struct ubsec_q {
  150         SIMPLEQ_ENTRY(ubsec_q)          q_next;
  151         int                             q_nstacked_mcrs;
  152         struct ubsec_q                  *q_stacked_mcr[UBS_MAX_AGGR-1];
  153         struct cryptop                  *q_crp;
  154         struct ubsec_dma                *q_dma;
  155 
  156         struct ubsec_operand            q_src;
  157         struct ubsec_operand            q_dst;
  158 
  159         int                             q_sesn;
  160         int                             q_flags;
  161 };
  162 
  163 #define q_src_m         q_src.u.m
  164 #define q_src_io        q_src.u.io
  165 #define q_src_map       q_src.map
  166 #define q_src_nsegs     q_src.nsegs
  167 #define q_src_segs      q_src.segs
  168 #define q_src_mapsize   q_src.mapsize
  169 
  170 #define q_dst_m         q_dst.u.m
  171 #define q_dst_io        q_dst.u.io
  172 #define q_dst_map       q_dst.map
  173 #define q_dst_nsegs     q_dst.nsegs
  174 #define q_dst_segs      q_dst.segs
  175 #define q_dst_mapsize   q_dst.mapsize
  176 
  177 struct rndstate_test;
  178 
  179 struct ubsec_softc {
  180         device_t                sc_dev;         /* device backpointer */
  181         struct resource         *sc_irq;
  182         void                    *sc_ih;         /* interrupt handler cookie */
  183         bus_space_handle_t      sc_sh;          /* memory handle */
  184         bus_space_tag_t         sc_st;          /* memory tag */
  185         struct resource         *sc_sr;         /* memory resource */
  186         bus_dma_tag_t           sc_dmat;        /* dma tag */
  187         int                     sc_flags;       /* device specific flags */
  188         int                     sc_suspended;
  189         int                     sc_needwakeup;  /* notify crypto layer */
  190         u_int32_t               sc_statmask;    /* interrupt status mask */
  191         int32_t                 sc_cid;         /* crypto tag */
  192         struct mtx              sc_mcr1lock;    /* mcr1 operation lock */
  193         SIMPLEQ_HEAD(,ubsec_q)  sc_queue;       /* packet queue, mcr1 */
  194         int                     sc_nqueue;      /* count enqueued, mcr1 */
  195         SIMPLEQ_HEAD(,ubsec_q)  sc_qchip;       /* on chip, mcr1 */
  196         int                     sc_nqchip;      /* count on chip, mcr1 */
  197         struct mtx              sc_freeqlock;   /* freequeue lock */
  198         SIMPLEQ_HEAD(,ubsec_q)  sc_freequeue;   /* list of free queue elements */
  199         struct mtx              sc_mcr2lock;    /* mcr2 operation lock */
  200         SIMPLEQ_HEAD(,ubsec_q2) sc_queue2;      /* packet queue, mcr2 */
  201         int                     sc_nqueue2;     /* count enqueued, mcr2 */
  202         SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2;      /* on chip, mcr2 */
  203         int                     sc_nsessions;   /* # of sessions */
  204         struct ubsec_session    *sc_sessions;   /* sessions */
  205         struct callout          sc_rngto;       /* rng timeout */
  206         int                     sc_rnghz;       /* rng poll time */
  207         struct ubsec_q2_rng     sc_rng;
  208         struct rndtest_state    *sc_rndtest;    /* RNG test state */
  209         void                    (*sc_harvest)(struct rndtest_state *,
  210                                         void *, u_int);
  211         struct ubsec_dma        sc_dmaa[UBS_MAX_NQUEUE];
  212         struct ubsec_q          *sc_queuea[UBS_MAX_NQUEUE];
  213         SIMPLEQ_HEAD(,ubsec_q2) sc_q2free;      /* free list */
  214 };
  215 
  216 #define UBSEC_QFLAGS_COPYOUTIV          0x1
  217 
  218 struct ubsec_session {
  219         u_int32_t       ses_used;
  220         u_int32_t       ses_deskey[6];          /* 3DES key */
  221         u_int32_t       ses_hminner[5];         /* hmac inner state */
  222         u_int32_t       ses_hmouter[5];         /* hmac outer state */
  223         u_int32_t       ses_iv[2];              /* [3]DES iv */
  224 };
  225 #endif /* _KERNEL */
  226 
  227 struct ubsec_stats {
  228         u_int64_t hst_ibytes;
  229         u_int64_t hst_obytes;
  230         u_int32_t hst_ipackets;
  231         u_int32_t hst_opackets;
  232         u_int32_t hst_invalid;          /* invalid argument */
  233         u_int32_t hst_badsession;       /* invalid session id */
  234         u_int32_t hst_badflags;         /* flags indicate !(mbuf | uio) */
  235         u_int32_t hst_nodesc;           /* op submitted w/o descriptors */
  236         u_int32_t hst_badalg;           /* unsupported algorithm */
  237         u_int32_t hst_nomem;
  238         u_int32_t hst_queuefull;
  239         u_int32_t hst_dmaerr;
  240         u_int32_t hst_mcrerr;
  241         u_int32_t hst_nodmafree;
  242         u_int32_t hst_lenmismatch;      /* enc/auth lengths different */
  243         u_int32_t hst_skipmismatch;     /* enc part begins before auth part */
  244         u_int32_t hst_iovmisaligned;    /* iov op not aligned */
  245         u_int32_t hst_noirq;            /* IRQ for no reason */
  246         u_int32_t hst_unaligned;        /* unaligned src caused copy */
  247         u_int32_t hst_nomap;            /* bus_dmamap_create failed */
  248         u_int32_t hst_noload;           /* bus_dmamap_load_* failed */
  249         u_int32_t hst_nombuf;           /* MGET* failed */
  250         u_int32_t hst_nomcl;            /* MCLGET* failed */
  251         u_int32_t hst_totbatch;         /* ops submitted w/o interrupt */
  252         u_int32_t hst_maxbatch;         /* max ops submitted together */
  253         u_int32_t hst_maxqueue;         /* max ops queued for submission */
  254         u_int32_t hst_maxqchip;         /* max mcr1 ops out for processing */
  255         u_int32_t hst_mcr1full;         /* MCR1 too busy to take ops */
  256         u_int32_t hst_rng;              /* RNG requests */
  257         u_int32_t hst_modexp;           /* MOD EXP requests */
  258         u_int32_t hst_modexpcrt;        /* MOD EXP CRT requests */
  259 };

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