Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/controller/dwc_otgreg.h
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1 /* $FreeBSD$ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 5 * 6 * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _DWC_OTGREG_H_ 31 #define _DWC_OTGREG_H_ 32 33 #define DOTG_GOTGCTL 0x0000 34 #define DOTG_GOTGINT 0x0004 35 #define DOTG_GAHBCFG 0x0008 36 #define DOTG_GUSBCFG 0x000C 37 #define DOTG_GRSTCTL 0x0010 38 #define DOTG_GINTSTS 0x0014 39 #define DOTG_GINTMSK 0x0018 40 #define DOTG_GRXSTSRD 0x001C 41 #define DOTG_GRXSTSRH 0x001C 42 #define DOTG_GRXSTSPD 0x0020 43 #define DOTG_GRXSTSPH 0x0020 44 #define DOTG_GRXFSIZ 0x0024 45 #define DOTG_GNPTXFSIZ 0x0028 46 #define DOTG_GNPTXSTS 0x002C 47 #define DOTG_GI2CCTL 0x0030 48 #define DOTG_GPVNDCTL 0x0034 49 #define DOTG_GGPIO 0x0038 50 #define DOTG_GUID 0x003C 51 #define DOTG_GSNPSID 0x0040 52 #define DOTG_GSNPSID_REV_2_80a 0x4f54280a /* RPi model B/RPi2 */ 53 #define DOTG_GSNPSID_REV_3_10a 0x4f54310a /* ODROID-C1 */ 54 #define DOTG_GHWCFG1 0x0044 55 #define DOTG_GHWCFG2 0x0048 56 #define DOTG_GHWCFG3 0x004C 57 #define DOTG_GHWCFG4 0x0050 58 #define DOTG_GLPMCFG 0x0054 59 #define DOTG_GPWRDN 0x0058 60 #define DOTG_GDFIFOCFG 0x005C 61 #define DOTG_GADPCTL 0x0060 62 63 #define DOTG_HPTXFSIZ 0x0100 64 /* start from 0x104, but fifo0 not exists */ 65 #define DOTG_DPTXFSIZ(fifo) (0x0100 + (4*(fifo))) 66 #define DOTG_DIEPTXF(fifo) (0x0100 + (4*(fifo))) 67 68 #define DOTG_HCFG 0x0400 69 #define DOTG_HFIR 0x0404 70 #define DOTG_HFNUM 0x0408 71 #define DOTG_HPTXSTS 0x0410 72 #define DOTG_HAINT 0x0414 73 #define DOTG_HAINTMSK 0x0418 74 #define DOTG_HPRT 0x0440 75 76 #define DOTG_HCCHAR(ch) (0x0500 + (32*(ch))) 77 #define DOTG_HCSPLT(ch) (0x0504 + (32*(ch))) 78 #define DOTG_HCINT(ch) (0x0508 + (32*(ch))) 79 #define DOTG_HCINTMSK(ch) (0x050C + (32*(ch))) 80 #define DOTG_HCTSIZ(ch) (0x0510 + (32*(ch))) 81 #define DOTG_HCDMA(ch) (0x0514 + (32*(ch))) 82 #define DOTG_HCDMAI(ch) (0x0514 + (32*(ch))) 83 #define DOTG_HCDMAO(ch) (0x0514 + (32*(ch))) 84 #define DOTG_HCDMAB(ch) (0x051C + (32*(ch))) 85 86 /* Device Mode */ 87 #define DOTG_DCFG 0x0800 88 #define DOTG_DCTL 0x0804 89 #define DOTG_DSTS 0x0808 90 #define DOTG_DIEPMSK 0x0810 91 #define DOTG_DOEPMSK 0x0814 92 #define DOTG_DAINT 0x0818 93 #define DOTG_DAINTMSK 0x081C 94 #define DOTG_DTKNQR1 0x0820 95 #define DOTG_DTKNQR2 0x0824 96 #define DOTG_DVBUSDIS 0x0828 97 #define DOTG_DVBUSPULSE 0x082C 98 #define DOTG_DTHRCTL 0x0830 99 #define DOTG_DTKNQR4 0x0834 100 #define DOTG_DIEPEMPMSK 0x0834 101 #define DOTG_DEACHINT 0x0838 102 #define DOTG_DEACHINTMSK 0x083C 103 #define DOTG_DIEPEACHINTMSK(ch) (0x0840 + (4*(ch))) 104 #define DOTG_DOEPEACHINTMSK(ch) (0x0880 + (4*(ch))) 105 106 #define DOTG_DIEPCTL(ep) (0x0900 + (32*(ep))) 107 #define DOTG_DIEPINT(ep) (0x0908 + (32*(ep))) 108 #define DOTG_DIEPTSIZ(ep) (0x0910 + (32*(ep))) 109 #define DOTG_DIEPDMA(ep) (0x0914 + (32*(ep))) 110 #define DOTG_DTXFSTS(ep) (0x0918 + (32*(ep))) 111 #define DOTG_DIEPDMAB(ep) (0x091c + (32*(ep))) 112 113 #define DOTG_DOEPCTL(ep) (0x0B00 + (32*(ep))) 114 #define DOTG_DOEPFN(ep) (0x0B04 + (32*(ep))) 115 #define DOTG_DOEPINT(ep) (0x0B08 + (32*(ep))) 116 #define DOTG_DOEPTSIZ(ep) (0x0B10 + (32*(ep))) 117 #define DOTG_DOEPDMA(ep) (0x0B14 + (32*(ep))) 118 #define DOTG_DOEPDMAB(ep) (0x0B1c + (32*(ep))) 119 /* End Device Mode */ 120 121 /* Host Mode 122 #define DOTG_CTL_STATUS 0x0800 123 #define DOTG_DMA0_INB_CHN0 0x0818 124 #define DOTG_DMA0_INB_CHN1 0x0820 125 #define DOTG_DMA0_INB_CHN2 0x0828 126 #define DOTG_DVBUSDIS 0x0828 127 #define DOTG_DVBUSPULSE 0x082c 128 #define DOTG_DMA0_INB_CHN3 0x0830 129 #define DOTG_DMA0_INB_CHN4 0x0838 130 #define DOTG_DMA0_INB_CHN5 0x0840 131 #define DOTG_DMA0_INB_CHN6 0x0848 132 #define DOTG_DMA0_INB_CHN7 0x0850 133 #define DOTG_DMA0_OUTB_CHN0 0x0858 134 #define DOTG_DMA0_OUTB_CHN1 0x0860 135 #define DOTG_DMA0_OUTB_CHN2 0x0868 136 #define DOTG_DMA0_OUTB_CHN3 0x0870 137 #define DOTG_DMA0_OUTB_CHN4 0x0878 138 #define DOTG_DMA0_OUTB_CHN5 0x0880 139 #define DOTG_DMA0_OUTB_CHN6 0x0888 140 #define DOTG_DMA0_OUTB_CHN7 0x0890 141 End Host Mode */ 142 143 /* Power and clock gating CSR */ 144 145 #define DOTG_PCGCCTL 0x0E00 146 147 /* FIFO access registers (PIO-mode) */ 148 149 #define DOTG_DFIFO(n) (0x1000 + (0x1000 * (n))) 150 151 #define GOTGCTL_CHIRP_ON (1<<27) 152 #define GOTGCTL_BSESVLD (1<<19) 153 #define GOTGCTL_ASESVLD (1<<18) 154 #define GOTGCTL_DBNCTIME (1<<17) 155 #define GOTGCTL_CONIDSTS (1<<16) 156 #define GOTGCTL_DEVHNPEN (1<<11) 157 #define GOTGCTL_HSTSETHNPEN (1<<10) 158 #define GOTGCTL_HNPREQ (1<<9) 159 #define GOTGCTL_HSTNEGSCS (1<<8) 160 #define GOTGCTL_SESREQ (1<<1) 161 #define GOTGCTL_SESREQSCS (1<<0) 162 163 #define GOTGCTL_DBNCEDONE (1<<19) 164 #define GOTGCTL_ADEVTOUTCHG (1<<18) 165 #define GOTGCTL_HSTNEGDET (1<<17) 166 #define GOTGCTL_HSTNEGSUCSTSCHG (1<<9) 167 #define GOTGCTL_SESREQSUCSTSCHG (1<<8) 168 #define GOTGCTL_SESENDDET (1<<2) 169 170 #define GAHBCFG_PTXFEMPLVL (1<<8) 171 #define GAHBCFG_NPTXFEMPLVL (1<<7) 172 #define GAHBCFG_DMAEN (1<<5) 173 #define GAHBCFG_HBSTLEN_MASK 0x0000001e 174 #define GAHBCFG_HBSTLEN_SHIFT 1 175 #define GAHBCFG_GLBLINTRMSK (1<<0) 176 177 #define GUSBCFG_CORRUPTTXPACKET (1<<31) 178 #define GUSBCFG_FORCEDEVMODE (1<<30) 179 #define GUSBCFG_FORCEHOSTMODE (1<<29) 180 #define GUSBCFG_NO_PULLUP (1<<27) 181 #define GUSBCFG_IC_USB_CAP (1<<26) 182 #define GUSBCFG_TERMSELDLPULSE (1<<22) 183 #define GUSBCFG_ULPIEXTVBUSINDICATOR (1<<21) 184 #define GUSBCFG_ULPIEXTVBUSDRV (1<<20) 185 #define GUSBCFG_ULPICLKSUSM (1<<19) 186 #define GUSBCFG_ULPIAUTORES (1<<18) 187 #define GUSBCFG_ULPIFSLS (1<<17) 188 #define GUSBCFG_OTGI2CSEL (1<<16) 189 #define GUSBCFG_PHYLPWRCLKSEL (1<<15) 190 #define GUSBCFG_USBTRDTIM_MASK 0x00003c00 191 #define GUSBCFG_USBTRDTIM_SHIFT 10 192 #define GUSBCFG_TRD_TIM_SET(x) (((x) & 15) << 10) 193 #define GUSBCFG_HNPCAP (1<<9) 194 #define GUSBCFG_SRPCAP (1<<8) 195 #define GUSBCFG_DDRSEL (1<<7) 196 #define GUSBCFG_PHYSEL (1<<6) 197 #define GUSBCFG_FSINTF (1<<5) 198 #define GUSBCFG_ULPI_UTMI_SEL (1<<4) 199 #define GUSBCFG_PHYIF (1<<3) 200 #define GUSBCFG_TOUTCAL_MASK 0x00000007 201 #define GUSBCFG_TOUTCAL_SHIFT 0 202 203 /* STM32F4 */ 204 #define DOTG_GGPIO_NOVBUSSENS (1 << 21) 205 #define DOTG_GGPIO_SOFOUTEN (1 << 20) 206 #define DOTG_GGPIO_VBUSBSEN (1 << 19) 207 #define DOTG_GGPIO_VBUSASEN (1 << 18) 208 #define DOTG_GGPIO_I2CPADEN (1 << 17) 209 #define DOTG_GGPIO_PWRDWN (1 << 16) 210 211 #define GRSTCTL_AHBIDLE (1<<31) 212 #define GRSTCTL_DMAREQ (1<<30) 213 #define GRSTCTL_TXFNUM_MASK 0x000007c0 214 #define GRSTCTL_TXFNUM_SHIFT 6 215 #define GRSTCTL_TXFIFO(n) (((n) & 31) << 6) 216 #define GRSTCTL_TXFFLSH (1<<5) 217 #define GRSTCTL_RXFFLSH (1<<4) 218 #define GRSTCTL_INTKNQFLSH (1<<3) 219 #define GRSTCTL_FRMCNTRRST (1<<2) 220 #define GRSTCTL_HSFTRST (1<<1) 221 #define GRSTCTL_CSFTRST (1<<0) 222 223 #define GINTSTS_WKUPINT (1<<31) 224 #define GINTSTS_SESSREQINT (1<<30) 225 #define GINTSTS_DISCONNINT (1<<29) 226 #define GINTSTS_CONIDSTSCHNG (1<<28) 227 #define GINTSTS_LPM (1<<27) 228 #define GINTSTS_PTXFEMP (1<<26) 229 #define GINTSTS_HCHINT (1<<25) 230 #define GINTSTS_PRTINT (1<<24) 231 #define GINTSTS_RESETDET (1<<23) 232 #define GINTSTS_FETSUSP (1<<22) 233 #define GINTSTS_INCOMPLP (1<<21) 234 #define GINTSTS_INCOMPISOIN (1<<20) 235 #define GINTSTS_OEPINT (1<<19) 236 #define GINTSTS_IEPINT (1<<18) 237 #define GINTSTS_EPMIS (1<<17) 238 #define GINTSTS_RESTORE_DONE (1<<16) 239 #define GINTSTS_EOPF (1<<15) 240 #define GINTSTS_ISOOUTDROP (1<<14) 241 #define GINTSTS_ENUMDONE (1<<13) 242 #define GINTSTS_USBRST (1<<12) 243 #define GINTSTS_USBSUSP (1<<11) 244 #define GINTSTS_ERLYSUSP (1<<10) 245 #define GINTSTS_I2CINT (1<<9) 246 #define GINTSTS_ULPICKINT (1<<8) 247 #define GINTSTS_GOUTNAKEFF (1<<7) 248 #define GINTSTS_GINNAKEFF (1<<6) 249 #define GINTSTS_NPTXFEMP (1<<5) 250 #define GINTSTS_RXFLVL (1<<4) 251 #define GINTSTS_SOF (1<<3) 252 #define GINTSTS_OTGINT (1<<2) 253 #define GINTSTS_MODEMIS (1<<1) 254 #define GINTSTS_CURMOD (1<<0) 255 256 #define GINTMSK_WKUPINTMSK (1<<31) 257 #define GINTMSK_SESSREQINTMSK (1<<30) 258 #define GINTMSK_DISCONNINTMSK (1<<29) 259 #define GINTMSK_CONIDSTSCHNGMSK (1<<28) 260 #define GINTMSK_PTXFEMPMSK (1<<26) 261 #define GINTMSK_HCHINTMSK (1<<25) 262 #define GINTMSK_PRTINTMSK (1<<24) 263 #define GINTMSK_FETSUSPMSK (1<<22) 264 #define GINTMSK_INCOMPLPMSK (1<<21) 265 #define GINTMSK_INCOMPISOINMSK (1<<20) 266 #define GINTMSK_OEPINTMSK (1<<19) 267 #define GINTMSK_IEPINTMSK (1<<18) 268 #define GINTMSK_EPMISMSK (1<<17) 269 #define GINTMSK_EOPFMSK (1<<15) 270 #define GINTMSK_ISOOUTDROPMSK (1<<14) 271 #define GINTMSK_ENUMDONEMSK (1<<13) 272 #define GINTMSK_USBRSTMSK (1<<12) 273 #define GINTMSK_USBSUSPMSK (1<<11) 274 #define GINTMSK_ERLYSUSPMSK (1<<10) 275 #define GINTMSK_I2CINTMSK (1<<9) 276 #define GINTMSK_ULPICKINTMSK (1<<8) 277 #define GINTMSK_GOUTNAKEFFMSK (1<<7) 278 #define GINTMSK_GINNAKEFFMSK (1<<6) 279 #define GINTMSK_NPTXFEMPMSK (1<<5) 280 #define GINTMSK_RXFLVLMSK (1<<4) 281 #define GINTMSK_SOFMSK (1<<3) 282 #define GINTMSK_OTGINTMSK (1<<2) 283 #define GINTMSK_MODEMISMSK (1<<1) 284 #define GINTMSK_CURMODMSK (1<<0) 285 286 #define GRXSTSRH_PKTSTS_MASK 0x001e0000 287 #define GRXSTSRH_PKTSTS_SHIFT 17 288 #define GRXSTSRH_DPID_MASK 0x00018000 289 #define GRXSTSRH_DPID_SHIFT 15 290 #define GRXSTSRH_BCNT_MASK 0x00007ff0 291 #define GRXSTSRH_BCNT_SHIFT 4 292 #define GRXSTSRH_CHNUM_MASK 0x0000000f 293 #define GRXSTSRH_CHNUM_SHIFT 0 294 295 #define GRXSTSRD_FN_MASK 0x01e00000 296 #define GRXSTSRD_FN_GET(x) (((x) >> 21) & 15) 297 #define GRXSTSRD_FN_SHIFT 21 298 #define GRXSTSRD_PKTSTS_MASK 0x001e0000 299 #define GRXSTSRD_PKTSTS_SHIFT 17 300 #define GRXSTSRH_IN_DATA (2<<17) 301 #define GRXSTSRH_IN_COMPLETE (3<<17) 302 #define GRXSTSRH_DT_ERROR (5<<17) 303 #define GRXSTSRH_HALTED (7<<17) 304 #define GRXSTSRD_GLOB_OUT_NAK (1<<17) 305 #define GRXSTSRD_OUT_DATA (2<<17) 306 #define GRXSTSRD_OUT_COMPLETE (3<<17) 307 #define GRXSTSRD_STP_COMPLETE (4<<17) 308 #define GRXSTSRD_STP_DATA (6<<17) 309 #define GRXSTSRD_DPID_MASK 0x00018000 310 #define GRXSTSRD_DPID_SHIFT 15 311 #define GRXSTSRD_DPID_DATA0 (0<<15) 312 #define GRXSTSRD_DPID_DATA1 (2<<15) 313 #define GRXSTSRD_DPID_DATA2 (1<<15) 314 #define GRXSTSRD_DPID_MDATA (3<<15) 315 #define GRXSTSRD_BCNT_MASK 0x00007ff0 316 #define GRXSTSRD_BCNT_GET(x) (((x) >> 4) & 0x7FF) 317 #define GRXSTSRD_BCNT_SHIFT 4 318 #define GRXSTSRD_CHNUM_MASK 0x0000000f 319 #define GRXSTSRD_CHNUM_GET(x) ((x) & 15) 320 #define GRXSTSRD_CHNUM_SHIFT 0 321 322 #define GRXFSIZ_RXFDEP_MASK 0x0000ffff 323 #define GRXFSIZ_RXFDEP_SHIFT 0 324 325 #define GNPTXFSIZ_NPTXFDEP_MASK 0xffff0000 326 #define GNPTXFSIZ_NPTXFDEP_SHIFT 0 327 #define GNPTXFSIZ_NPTXFSTADDR_MASK 0x0000ffff 328 #define GNPTXFSIZ_NPTXFSTADDR_SHIFT 16 329 330 #define GNPTXSTS_NPTXQTOP_SHIFT 24 331 #define GNPTXSTS_NPTXQTOP_MASK 0x7f000000 332 #define GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 333 #define GNPTXSTS_NPTXQSPCAVAIL_MASK 0x00ff0000 334 #define GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 335 #define GNPTXSTS_NPTXFSPCAVAIL_MASK 0x0000ffff 336 337 #define GI2CCTL_BSYDNE_SC (1<<31) 338 #define GI2CCTL_RW (1<<30) 339 #define GI2CCTL_I2CDATSE0 (1<<28) 340 #define GI2CCTL_I2CDEVADR_SHIFT 26 341 #define GI2CCTL_I2CDEVADR_MASK 0x0c000000 342 #define GI2CCTL_I2CSUSPCTL (1<<25) 343 #define GI2CCTL_ACK (1<<24) 344 #define GI2CCTL_I2CEN (1<<23) 345 #define GI2CCTL_ADDR_SHIFT 16 346 #define GI2CCTL_ADDR_MASK 0x007f0000 347 #define GI2CCTL_REGADDR_SHIFT 8 348 #define GI2CCTL_REGADDR_MASK 0x0000ff00 349 #define GI2CCTL_RWDATA_SHIFT 0 350 #define GI2CCTL_RWDATA_MASK 0x000000ff 351 352 #define GPVNDCTL_DISULPIDRVR (1<<31) 353 #define GPVNDCTL_VSTSDONE (1<<27) 354 #define GPVNDCTL_VSTSBSY (1<<26) 355 #define GPVNDCTL_NEWREGREQ (1<<25) 356 #define GPVNDCTL_REGWR (1<<22) 357 #define GPVNDCTL_REGADDR_SHIFT 16 358 #define GPVNDCTL_REGADDR_MASK 0x003f0000 359 #define GPVNDCTL_VCTRL_SHIFT 8 360 #define GPVNDCTL_VCTRL_MASK 0x0000ff00 361 #define GPVNDCTL_REGDATA_SHIFT 0 362 #define GPVNDCTL_REGDATA_MASK 0x000000ff 363 364 #define GGPIO_GPO_SHIFT 16 365 #define GGPIO_GPO_MASK 0xffff0000 366 #define GGPIO_GPI_SHIFT 0 367 #define GGPIO_GPI_MASK 0x0000ffff 368 369 #define GHWCFG1_GET_DIR(x, n) (((x) >> (2 * (n))) & 3) 370 #define GHWCFG1_BIDIR 0 371 #define GHWCFG1_IN 1 372 #define GHWCFG1_OUT 2 373 374 #define GHWCFG2_TKNQDEPTH_SHIFT 26 375 #define GHWCFG2_TKNQDEPTH_MASK 0x7c000000 376 #define GHWCFG2_PTXQDEPTH_SHIFT 24 377 #define GHWCFG2_PTXQDEPTH_MASK 0x03000000 378 #define GHWCFG2_NPTXQDEPTH_SHIFT 22 379 #define GHWCFG2_NPTXQDEPTH_MASK 0x00c00000 380 #define GHWCFG2_MPI (1<<20) 381 #define GHWCFG2_DYNFIFOSIZING (1<<19) 382 #define GHWCFG2_PERIOSUPPORT (1<<18) 383 #define GHWCFG2_NUMHSTCHNL_SHIFT 14 384 #define GHWCFG2_NUMHSTCHNL_MASK 0x0003c000 385 #define GHWCFG2_NUMHSTCHNL_GET(x) ((((x) >> 14) & 15) + 1) 386 #define GHWCFG2_NUMDEVEPS_SHIFT 10 387 #define GHWCFG2_NUMDEVEPS_MASK 0x00003c00 388 #define GHWCFG2_NUMDEVEPS_GET(x) ((((x) >> 10) & 15) + 1) 389 #define GHWCFG2_FSPHYTYPE_SHIFT 8 390 #define GHWCFG2_FSPHYTYPE_MASK 0x00000300 391 #define GHWCFG2_HSPHYTYPE_SHIFT 6 392 #define GHWCFG2_HSPHYTYPE_MASK 0x000000c0 393 #define GHWCFG2_SINGPNT (1<<5) 394 #define GHWCFG2_OTGARCH_SHIFT 3 395 #define GHWCFG2_OTGARCH_MASK 0x00000018 396 #define GHWCFG2_OTGMODE_SHIFT 0 397 #define GHWCFG2_OTGMODE_MASK 0x00000007 398 399 #define GHWCFG3_DFIFODEPTH_SHIFT 16 400 #define GHWCFG3_DFIFODEPTH_MASK 0xffff0000 401 #define GHWCFG3_DFIFODEPTH_GET(x) ((x) >> 16) 402 #define GHWCFG3_RSTTYPE (1<<11) 403 #define GHWCFG3_OPTFEATURE (1<<10) 404 #define GHWCFG3_VNDCTLSUPT (1<<9) 405 #define GHWCFG3_I2CINTSEL (1<<8) 406 #define GHWCFG3_OTGEN (1<<7) 407 #define GHWCFG3_PKTSIZEWIDTH_SHIFT 4 408 #define GHWCFG3_PKTSIZEWIDTH_MASK 0x00000070 409 #define GHWCFG3_PKTSIZE_GET(x) (0x10<<(((x) >> 4) & 7)) 410 #define GHWCFG3_XFERSIZEWIDTH_SHIFT 0 411 #define GHWCFG3_XFERSIZEWIDTH_MASK 0x0000000f 412 #define GHWCFG3_XFRRSIZE_GET(x) (0x400<<(((x) >> 0) & 15)) 413 414 #define GHWCFG4_NUM_IN_EP_GET(x) ((((x) >> 26) & 15) + 1) 415 #define GHWCFG4_SESSENDFLTR (1<<24) 416 #define GHWCFG4_BVALIDFLTR (1<<23) 417 #define GHWCFG4_AVALIDFLTR (1<<22) 418 #define GHWCFG4_VBUSVALIDFLTR (1<<21) 419 #define GHWCFG4_IDDGFLTR (1<<20) 420 #define GHWCFG4_NUMCTLEPS_SHIFT 16 421 #define GHWCFG4_NUMCTLEPS_MASK 0x000f0000 422 #define GHWCFG4_NUMCTLEPS_GET(x) (((x) >> 16) & 15) 423 #define GHWCFG4_PHYDATAWIDTH_SHIFT 14 424 #define GHWCFG4_PHYDATAWIDTH_MASK 0x0000c000 425 #define GHWCFG4_AHBFREQ (1<<5) 426 #define GHWCFG4_ENABLEPWROPT (1<<4) 427 #define GHWCFG4_NUMDEVPERIOEPS_SHIFT 0 428 #define GHWCFG4_NUMDEVPERIOEPS_MASK 0x0000000f 429 #define GHWCFG4_NUMDEVPERIOEPS_GET(x) (((x) >> 0) & 15) 430 431 #define GLPMCFG_HSIC_CONN (1<<30) 432 433 #define GPWRDN_BVALID (1<<22) 434 #define GPWRDN_IDDIG (1<<21) 435 #define GPWRDN_CONNDET_INT (1<<14) 436 #define GPWRDN_CONNDET (1<<13) 437 #define GPWRDN_DISCONN_INT (1<<12) 438 #define GPWRDN_DISCONN (1<<11) 439 #define GPWRDN_RESETDET_INT (1<<10) 440 #define GPWRDN_RESETDET (1<<9) 441 #define GPWRDN_LINESTATE_INT (1<<8) 442 #define GPWRDN_LINESTATE (1<<7) 443 #define GPWRDN_DISABLE_VBUS (1<<6) 444 #define GPWRDN_POWER_DOWN (1<<5) 445 #define GPWRDN_POWER_DOWN_RST (1<<4) 446 #define GPWRDN_POWER_DOWN_CLAMP (1<<3) 447 #define GPWRDN_RESTORE (1<<2) 448 #define GPWRDN_PMU_ACTIVE (1<<1) 449 #define GPWRDN_PMU_IRQ_SEL (1<<0) 450 451 #define HPTXFSIZ_PTXFSIZE_SHIFT 16 452 #define HPTXFSIZ_PTXFSIZE_MASK 0xffff0000 453 #define HPTXFSIZ_PTXFSTADDR_SHIFT 0 454 #define HPTXFSIZ_PTXFSTADDR_MASK 0x0000ffff 455 456 #define DPTXFSIZN_DPTXFSIZE_SHIFT 16 457 #define DPTXFSIZN_DPTXFSIZE_MASK 0xffff0000 458 #define DPTXFSIZN_PTXFSTADDR_SHIFT 0 459 #define DPTXFSIZN_PTXFSTADDR_MASK 0x0000ffff 460 461 #define DIEPTXFN_INEPNTXFDEP_SHIFT 16 462 #define DIEPTXFN_INEPNTXFDEP_MASK 0xffff0000 463 #define DIEPTXFN_INEPNTXFSTADDR_SHIFT 0 464 #define DIEPTXFN_INEPNTXFSTADDR_MASK 0x0000ffff 465 466 #define HCFG_MODECHANGERDY (1<<31) 467 #define HCFG_PERSCHEDENABLE (1<<26) 468 #define HCFG_FLENTRIES_SHIFT 24 469 #define HCFG_FLENTRIES_MASK 0x03000000 470 #define HCFG_FLENTRIES_8 (0) 471 #define HCFG_FLENTRIES_16 (1) 472 #define HCFG_FLENTRIES_32 (2) 473 #define HCFG_FLENTRIES_64 (3) 474 #define HCFG_MULTISEGDMA (1<<23) 475 #define HCFG_32KHZSUSPEND (1<<7) 476 #define HCFG_FSLSSUPP (1<<2) 477 #define HCFG_FSLSPCLKSEL_SHIFT 0 478 #define HCFG_FSLSPCLKSEL_MASK 0x00000003 479 480 #define HFIR_RELOADCTRL (1<<16) 481 #define HFIR_FRINT_SHIFT 0 482 #define HFIR_FRINT_MASK 0x0000ffff 483 484 #define HFNUM_FRREM_SHIFT 16 485 #define HFNUM_FRREM_MASK 0xffff0000 486 #define HFNUM_FRNUM_SHIFT 0 487 #define HFNUM_FRNUM_MASK 0x0000ffff 488 489 #define HPTXSTS_ODD (1<<31) 490 #define HPTXSTS_CHAN_SHIFT 27 491 #define HPTXSTS_CHAN_MASK 0x78000000 492 #define HPTXSTS_TOKEN_SHIFT 25 493 #define HPTXSTS_TOKEN_MASK 0x06000000 494 #define HPTXSTS_TOKEN_ZL 0 495 #define HPTXSTS_TOKEN_PING 1 496 #define HPTXSTS_TOKEN_DISABLE 2 497 #define HPTXSTS_TERMINATE (1<<24) 498 #define HPTXSTS_PTXQSPCAVAIL_SHIFT 16 499 #define HPTXSTS_PTXQSPCAVAIL_MASK 0x00ff0000 500 #define HPTXSTS_PTXFSPCAVAIL_SHIFT 0 501 #define HPTXSTS_PTXFSPCAVAIL_MASK 0x0000ffff 502 503 #define HAINT_HAINT_SHIFT 0 504 #define HAINT_HAINT_MASK 0x0000ffff 505 #define HAINTMSK_HAINTMSK_SHIFT 0 506 #define HAINTMSK_HAINTMSK_MASK 0x0000ffff 507 508 #define HPRT_PRTSPD_SHIFT 17 509 #define HPRT_PRTSPD_MASK 0x00060000 510 #define HPRT_PRTSPD_HIGH 0 511 #define HPRT_PRTSPD_FULL 1 512 #define HPRT_PRTSPD_LOW 2 513 #define HPRT_PRTSPD_MASK 0x00060000 514 #define HPRT_PRTTSTCTL_SHIFT 13 515 #define HPRT_PRTTSTCTL_MASK 0x0001e000 516 #define HPRT_PRTPWR (1<<12) 517 #define HPRT_PRTLNSTS_SHIFT 10 518 #define HPRT_PRTLNSTS_MASK 0x00000c00 519 #define HPRT_PRTRST (1<<8) 520 #define HPRT_PRTSUSP (1<<7) 521 #define HPRT_PRTRES (1<<6) 522 #define HPRT_PRTOVRCURRCHNG (1<<5) 523 #define HPRT_PRTOVRCURRACT (1<<4) 524 #define HPRT_PRTENCHNG (1<<3) 525 #define HPRT_PRTENA (1<<2) 526 #define HPRT_PRTCONNDET (1<<1) 527 #define HPRT_PRTCONNSTS (1<<0) 528 529 #define HCCHAR_CHENA (1<<31) 530 #define HCCHAR_CHDIS (1<<30) 531 #define HCCHAR_ODDFRM (1<<29) 532 #define HCCHAR_DEVADDR_SHIFT 22 533 #define HCCHAR_DEVADDR_MASK 0x1fc00000 534 #define HCCHAR_MC_SHIFT 20 535 #define HCCHAR_MC_MASK 0x00300000 536 #define HCCHAR_EPTYPE_SHIFT 18 537 #define HCCHAR_EPTYPE_MASK 0x000c0000 538 #define HCCHAR_LSPDDEV (1<<17) 539 #define HCCHAR_EPDIR (1<<15) 540 #define HCCHAR_EPDIR_IN (1<<15) 541 #define HCCHAR_EPDIR_OUT 0 542 #define HCCHAR_EPNUM_SHIFT 11 543 #define HCCHAR_EPNUM_MASK 0x00007800 544 #define HCCHAR_MPS_SHIFT 0 545 #define HCCHAR_MPS_MASK 0x000007ff 546 547 #define HCSPLT_SPLTENA (1<<31) 548 #define HCSPLT_COMPSPLT (1<<16) 549 #define HCSPLT_XACTPOS_SHIFT 14 550 #define HCSPLT_XACTPOS_MASK 0x0000c000 551 #define HCSPLT_XACTPOS_MIDDLE 0 552 #define HCSPLT_XACTPOS_LAST 1 553 #define HCSPLT_XACTPOS_BEGIN 2 554 #define HCSPLT_XACTPOS_ALL 3 555 #define HCSPLT_XACTLEN_BURST 1023 /* bytes */ 556 #define HCSPLT_HUBADDR_SHIFT 7 557 #define HCSPLT_HUBADDR_MASK 0x00003f80 558 #define HCSPLT_PRTADDR_SHIFT 0 559 #define HCSPLT_PRTADDR_MASK 0x0000007f 560 561 #define HCINT_ERRORS \ 562 (HCINT_BBLERR | HCINT_XACTERR) 563 #define HCINT_RETRY \ 564 (HCINT_DATATGLERR | HCINT_FRMOVRUN | HCINT_NAK) 565 #define HCINT_DEFAULT_MASK \ 566 (HCINT_STALL | HCINT_BBLERR | \ 567 HCINT_XACTERR | HCINT_NAK | HCINT_ACK | HCINT_NYET | \ 568 HCINT_CHHLTD | HCINT_FRMOVRUN | \ 569 HCINT_DATATGLERR) 570 #define HCINT_HCH_DONE_MASK \ 571 (HCINT_ACK | HCINT_RETRY | HCINT_NYET | \ 572 HCINT_ERRORS | HCINT_STALL | HCINT_SOFTWARE_ONLY) 573 574 #define HCINT_SOFTWARE_ONLY (1<<20) /* BSD only */ 575 #define HCINT_DATATGLERR (1<<10) 576 #define HCINT_FRMOVRUN (1<<9) 577 #define HCINT_BBLERR (1<<8) 578 #define HCINT_XACTERR (1<<7) 579 #define HCINT_NYET (1<<6) 580 #define HCINT_ACK (1<<5) 581 #define HCINT_NAK (1<<4) 582 #define HCINT_STALL (1<<3) 583 #define HCINT_AHBERR (1<<2) 584 #define HCINT_CHHLTD (1<<1) 585 #define HCINT_XFERCOMPL (1<<0) 586 587 #define HCINTMSK_DATATGLERRMSK (1<<10) 588 #define HCINTMSK_FRMOVRUNMSK (1<<9) 589 #define HCINTMSK_BBLERRMSK (1<<8) 590 #define HCINTMSK_XACTERRMSK (1<<7) 591 #define HCINTMSK_NYETMSK (1<<6) 592 #define HCINTMSK_ACKMSK (1<<5) 593 #define HCINTMSK_NAKMSK (1<<4) 594 #define HCINTMSK_STALLMSK (1<<3) 595 #define HCINTMSK_AHBERRMSK (1<<2) 596 #define HCINTMSK_CHHLTDMSK (1<<1) 597 #define HCINTMSK_XFERCOMPLMSK (1<<0) 598 599 #define HCTSIZ_DOPNG (1<<31) 600 #define HCTSIZ_PID_SHIFT 29 601 #define HCTSIZ_PID_MASK 0x60000000 602 #define HCTSIZ_PID_DATA0 0 603 #define HCTSIZ_PID_DATA2 1 604 #define HCTSIZ_PID_DATA1 2 605 #define HCTSIZ_PID_MDATA 3 606 #define HCTSIZ_PID_SETUP 3 607 #define HCTSIZ_PKTCNT_SHIFT 19 608 #define HCTSIZ_PKTCNT_MASK 0x1ff80000 609 #define HCTSIZ_XFERSIZE_SHIFT 0 610 #define HCTSIZ_XFERSIZE_MASK 0x0007ffff 611 612 #define DCFG_EPMISCNT_SHIFT 18 613 #define DCFG_EPMISCNT_MASK 0x007c0000 614 #define DCFG_PERFRINT_SHIFT 11 615 #define DCFG_PERFRINT_MASK 0x00001800 616 #define DCFG_DEVADDR_SHIFT 4 617 #define DCFG_DEVADDR_MASK 0x000007f0 618 #define DCFG_DEVADDR_SET(x) (((x) & 0x7F) << 4) 619 #define DCFG_NZSTSOUTHSHK (1<<2) 620 #define DCFG_DEVSPD_SHIFT 0 621 #define DCFG_DEVSPD_MASK 0x00000003 622 #define DCFG_DEVSPD_SET(x) ((x) & 0x3) 623 #define DCFG_DEVSPD_HI 0 624 #define DCFG_DEVSPD_FULL20 1 625 #define DCFG_DEVSPD_FULL10 3 626 627 #define DCTL_PWRONPRGDONE (1<<11) 628 #define DCTL_CGOUTNAK (1<<10) 629 #define DCTL_SGOUTNAK (1<<9) 630 #define DCTL_CGNPINNAK (1<<8) 631 #define DCTL_SGNPINNAK (1<<7) 632 #define DCTL_TSTCTL_SHIFT 4 633 #define DCTL_TSTCTL_MASK 0x00000070 634 #define DCTL_GOUTNAKSTS (1<<3) 635 #define DCTL_GNPINNAKSTS (1<<2) 636 #define DCTL_SFTDISCON (1<<1) 637 #define DCTL_RMTWKUPSIG (1<<0) 638 639 #define DSTS_SOFFN_SHIFT 8 640 #define DSTS_SOFFN_MASK 0x003fff00 641 #define DSTS_SOFFN_GET(x) (((x) >> 8) & 0x3FFF) 642 #define DSTS_ERRTICERR (1<<3) 643 #define DSTS_ENUMSPD_SHIFT 1 644 #define DSTS_ENUMSPD_MASK 0x00000006 645 #define DSTS_ENUMSPD_GET(x) (((x) >> 1) & 3) 646 #define DSTS_ENUMSPD_HI 0 647 #define DSTS_ENUMSPD_FULL20 1 648 #define DSTS_ENUMSPD_LOW10 2 649 #define DSTS_ENUMSPD_FULL10 3 650 #define DSTS_SUSPSTS (1<<0) 651 652 #define DIEPMSK_TXFIFOUNDRNMSK (1<<8) 653 #define DIEPMSK_INEPNAKEFFMSK (1<<6) 654 #define DIEPMSK_INTKNEPMISMSK (1<<5) 655 #define DIEPMSK_INTKNTXFEMPMSK (1<<4) 656 #define DIEPMSK_FIFOEMPTY (1<<4) 657 #define DIEPMSK_TIMEOUTMSK (1<<3) 658 #define DIEPMSK_AHBERRMSK (1<<2) 659 #define DIEPMSK_EPDISBLDMSK (1<<1) 660 #define DIEPMSK_XFERCOMPLMSK (1<<0) 661 662 #define DOEPMSK_OUTPKTERRMSK (1<<8) 663 #define DOEPMSK_BACK2BACKSETUP (1<<6) 664 #define DOEPMSK_OUTTKNEPDISMSK (1<<4) 665 #define DOEPMSK_FIFOEMPTY (1<<4) 666 #define DOEPMSK_SETUPMSK (1<<3) 667 #define DOEPMSK_AHBERRMSK (1<<2) 668 #define DOEPMSK_EPDISBLDMSK (1<<1) 669 #define DOEPMSK_XFERCOMPLMSK (1<<0) 670 671 #define DIEPINT_TXFIFOUNDRN (1<<8) 672 #define DIEPINT_INEPNAKEFF (1<<6) 673 #define DIEPINT_INTKNEPMIS (1<<5) 674 #define DIEPINT_INTKNTXFEMP (1<<4) 675 #define DIEPINT_TIMEOUT (1<<3) 676 #define DIEPINT_AHBERR (1<<2) 677 #define DIEPINT_EPDISBLD (1<<1) 678 #define DIEPINT_XFERCOMPL (1<<0) 679 680 #define DOEPINT_OUTPKTERR (1<<8) 681 #define DOEPINT_BACK2BACKSETUP (1<<6) 682 #define DOEPINT_OUTTKNEPDIS (1<<4) 683 #define DOEPINT_SETUP (1<<3) 684 #define DOEPINT_AHBERR (1<<2) 685 #define DOEPINT_EPDISBLD (1<<1) 686 #define DOEPINT_XFERCOMPL (1<<0) 687 688 #define DAINT_INEPINT_MASK 0xffff0000 689 #define DAINT_INEPINT_SHIFT 0 690 #define DAINT_OUTEPINT_MASK 0x0000ffff 691 #define DAINT_OUTEPINT_SHIFT 16 692 693 #define DAINTMSK_INEPINT_MASK 0xffff0000 694 #define DAINTMSK_INEPINT_SHIFT 0 695 #define DAINTMSK_OUTEPINT_MASK 0x0000ffff 696 #define DAINTMSK_OUTEPINT_SHIFT 16 697 698 #define DTKNQR1_EPTKN_SHIFT 8 699 #define DTKNQR1_EPTKN_MASK 0xffffff00 700 #define DTKNQR1_WRAPBIT (1<<7) 701 #define DTKNQR1_INTKNWPTR_SHIFT 0 702 #define DTKNQR1_INTKNWPTR_MASK 0x0000001f 703 704 #define DVBUSDIS_DVBUSDIS_SHIFT 0 705 #define DVBUSDIS_DVBUSDIS_MASK 0x0000ffff 706 707 #define DVBUSPULSE_DVBUSPULSE_SHIFT 0 708 #define DVBUSPULSE_DVBUSPULSE_MASK 0x00000fff 709 710 #define DTHRCTL_ARBPRKEN (1<<27) 711 #define DTHRCTL_RXTHRLEN_SHIFT 17 712 #define DTHRCTL_RXTHRLEN_MASK 0x03fe0000 713 #define DTHRCTL_RXTHREN (1<<16) 714 #define DTHRCTL_TXTHRLEN_SHIFT 2 715 #define DTHRCTL_TXTHRLEN_MASK 0x000007fc 716 #define DTHRCTL_ISOTHREN (1<<1) 717 #define DTHRCTL_NONISOTHREN (1<<0) 718 719 #define DIEPEMPMSK_INEPTXFEMPMSK_SHIFT 0 720 #define DIEPEMPMSK_INEPTXFEMPMSK_MASK 0x0000ffff 721 722 #define DIEPCTL_EPENA (1<<31) 723 #define DIEPCTL_EPDIS (1<<30) 724 #define DIEPCTL_SETD1PID (1<<29) 725 #define DIEPCTL_SETD0PID (1<<28) 726 #define DIEPCTL_SNAK (1<<27) 727 #define DIEPCTL_CNAK (1<<26) 728 #define DIEPCTL_TXFNUM_SHIFT 22 729 #define DIEPCTL_TXFNUM_MASK 0x03c00000 730 #define DIEPCTL_TXFNUM_SET(n) (((n) & 15) << 22) 731 #define DIEPCTL_STALL (1<<21) 732 #define DIEPCTL_EPTYPE_SHIFT 18 733 #define DIEPCTL_EPTYPE_MASK 0x000c0000 734 #define DIEPCTL_EPTYPE_SET(n) (((n) & 3) << 18) 735 #define DIEPCTL_EPTYPE_CONTROL 0 736 #define DIEPCTL_EPTYPE_ISOC 1 737 #define DIEPCTL_EPTYPE_BULK 2 738 #define DIEPCTL_EPTYPE_INTERRUPT 3 739 #define DIEPCTL_NAKSTS (1<<17) 740 #define DIEPCTL_USBACTEP (1<<15) 741 #define DIEPCTL_NEXTEP_SHIFT 11 742 #define DIEPCTL_NEXTEP_MASK 0x00007800 743 #define DIEPCTL_MPS_SHIFT 0 744 #define DIEPCTL_MPS_MASK 0x000007ff 745 #define DIEPCTL_MPS_SET(n) ((n) & 0x7FF) 746 #define DIEPCTL_MPS_64 (0<<0) 747 #define DIEPCTL_MPS_32 (1<<0) 748 #define DIEPCTL_MPS_16 (2<<0) 749 #define DIEPCTL_MPS_8 (3<<0) 750 751 #define DOEPCTL_EPENA (1<<31) 752 #define DOEPCTL_EPDIS (1<<30) 753 #define DOEPCTL_SETD1PID (1<<29) 754 #define DOEPCTL_SETD0PID (1<<28) 755 #define DOEPCTL_SNAK (1<<27) 756 #define DOEPCTL_CNAK (1<<26) 757 #define DOEPCTL_FNUM_SET(n) (((n) & 15) << 22) 758 #define DOEPCTL_STALL (1<<21) 759 #define DOEPCTL_EPTYPE_SHIFT 18 760 #define DOEPCTL_EPTYPE_MASK 0x000c0000 761 #define DOEPCTL_EPTYPE_SET(n) (((n) & 3) << 18) 762 #define DOEPCTL_NAKSTS (1<<17) 763 #define DOEPCTL_USBACTEP (1<<15) 764 #define DOEPCTL_MPS_SHIFT 0 765 #define DOEPCTL_MPS_MASK 0x000007ff 766 #define DOEPCTL_MPS_SET(n) ((n) & 0x7FF) 767 #define DOEPCTL_MPS_64 (0<<0) 768 #define DOEPCTL_MPS_32 (1<<0) 769 #define DOEPCTL_MPS_16 (2<<0) 770 #define DOEPCTL_MPS_8 (3<<0) 771 772 /* common bits */ 773 #define DXEPINT_TXFEMP (1<<7) 774 #define DXEPINT_SETUP (1<<3) 775 #define DXEPINT_XFER_COMPL (1<<0) 776 777 #define DIEPTSIZ_XFERSIZE_MASK 0x0007ffff 778 #define DIEPTSIZ_XFERSIZE_SHIFT 0 779 #define DIEPTSIZ_PKTCNT_MASK 0x1ff80000 780 #define DIEPTSIZ_PKTCNT_SHIFT 19 781 #define DIEPTSIZ_MC_MASK 0x60000000 782 #define DIEPTSIZ_MC_SHIFT 29 783 784 #define DOEPTSIZ_XFERSIZE_MASK 0x0007ffff 785 #define DOEPTSIZ_XFERSIZE_SHIFT 0 786 #define DOEPTSIZ_PKTCNT_MASK 0x1ff80000 787 #define DOEPTSIZ_PKTCNT_SHIFT 19 788 #define DOEPTSIZ_MC_MASK 0x60000000 789 #define DOEPTSIZ_MC_SHIFT 29 790 791 /* common bits */ 792 #define DXEPTSIZ_SET_MULTI(n) (((n) & 3) << 29) 793 #define DXEPTSIZ_SET_NPKT(n) (((n) & 0x3FF) << 19) 794 #define DXEPTSIZ_GET_NPKT(n) (((n) >> 19) & 0x3FF) 795 #define DXEPTSIZ_SET_NBYTES(n) (((n) & 0x7FFFFF) << 0) 796 #define DXEPTSIZ_GET_NBYTES(n) (((n) >> 0) & 0x7FFFFF) 797 798 /* generic endpoint mask */ 799 800 #define ENDPOINT_MASK(x,in) \ 801 ((in) ? (1U << ((x) & 15U)) : \ 802 (0x10000U << ((x) & 15U))) 803 804 #endif /* _DWC_OTGREG_H_ */
Cache object: cc532797d4beae1697616c1c3ec0f75f
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