Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/controller/xhci_pci.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/stdint.h> 32 #include <sys/stddef.h> 33 #include <sys/param.h> 34 #include <sys/queue.h> 35 #include <sys/types.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/sysctl.h> 44 #include <sys/sx.h> 45 #include <sys/unistd.h> 46 #include <sys/callout.h> 47 #include <sys/malloc.h> 48 #include <sys/priv.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 53 #include <dev/usb/usb_core.h> 54 #include <dev/usb/usb_busdma.h> 55 #include <dev/usb/usb_process.h> 56 #include <dev/usb/usb_util.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/usb_pci.h> 61 #include <dev/usb/controller/xhci.h> 62 #include <dev/usb/controller/xhcireg.h> 63 #include "usb_if.h" 64 65 #define PCI_XHCI_VENDORID_AMD 0x1022 66 #define PCI_XHCI_VENDORID_INTEL 0x8086 67 #define PCI_XHCI_VENDORID_VMWARE 0x15ad 68 #define PCI_XHCI_VENDORID_ZHAOXIN 0x1d17 69 70 static device_probe_t xhci_pci_probe; 71 static device_detach_t xhci_pci_detach; 72 static usb_take_controller_t xhci_pci_take_controller; 73 74 static device_method_t xhci_device_methods[] = { 75 /* device interface */ 76 DEVMETHOD(device_probe, xhci_pci_probe), 77 DEVMETHOD(device_attach, xhci_pci_attach), 78 DEVMETHOD(device_detach, xhci_pci_detach), 79 DEVMETHOD(device_suspend, bus_generic_suspend), 80 DEVMETHOD(device_resume, bus_generic_resume), 81 DEVMETHOD(device_shutdown, bus_generic_shutdown), 82 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 83 84 DEVMETHOD_END 85 }; 86 87 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 88 sizeof(struct xhci_softc)); 89 90 DRIVER_MODULE(xhci, pci, xhci_pci_driver, NULL, NULL); 91 MODULE_DEPEND(xhci, usb, 1, 1, 1); 92 93 static const char * 94 xhci_pci_match(device_t self) 95 { 96 uint32_t device_id = pci_get_devid(self); 97 98 switch (device_id) { 99 case 0x145c1022: 100 return ("AMD KERNCZ USB 3.0 controller"); 101 case 0x148c1022: 102 return ("AMD Starship USB 3.0 controller"); 103 case 0x149c1022: 104 return ("AMD Matisse USB 3.0 controller"); 105 case 0x43ba1022: 106 return ("AMD X399 USB 3.0 controller"); 107 case 0x43b91022: /* X370 */ 108 case 0x43bb1022: /* B350 */ 109 return ("AMD 300 Series USB 3.0 controller"); 110 case 0x78121022: 111 case 0x78141022: 112 case 0x79141022: 113 return ("AMD FCH USB 3.0 controller"); 114 115 case 0x077815ad: 116 case 0x077915ad: 117 return ("VMware USB 3.0 controller"); 118 119 case 0x145f1d94: 120 return ("Hygon USB 3.0 controller"); 121 122 case 0x01941033: 123 return ("NEC uPD720200 USB 3.0 controller"); 124 case 0x00151912: 125 return ("NEC uPD720202 USB 3.0 controller"); 126 127 case 0x10001b73: 128 return ("Fresco Logic FL1000G USB 3.0 controller"); 129 case 0x11001b73: 130 return ("Fresco Logic FL1100 USB 3.0 controller"); 131 132 case 0x10421b21: 133 return ("ASMedia ASM1042 USB 3.0 controller"); 134 case 0x11421b21: 135 return ("ASMedia ASM1042A USB 3.0 controller"); 136 case 0x13431b21: 137 return ("ASMedia ASM1143 USB 3.1 controller"); 138 case 0x32421b21: 139 return ("ASMedia ASM3242 USB 3.2 controller"); 140 141 case 0x0b278086: 142 return ("Intel Goshen Ridge Thunderbolt 4 USB controller"); 143 case 0x0f358086: 144 return ("Intel BayTrail USB 3.0 controller"); 145 case 0x11388086: 146 return ("Intel Maple Ridge Thunderbolt 4 USB controller"); 147 case 0x15c18086: 148 case 0x15d48086: 149 case 0x15db8086: 150 return ("Intel Alpine Ridge Thunderbolt 3 USB controller"); 151 case 0x15e98086: 152 case 0x15ec8086: 153 case 0x15f08086: 154 return ("Intel Titan Ridge Thunderbolt 3 USB controller"); 155 case 0x19d08086: 156 return ("Intel Denverton USB 3.0 controller"); 157 case 0x9c318086: 158 case 0x1e318086: 159 return ("Intel Panther Point USB 3.0 controller"); 160 case 0x22b58086: 161 return ("Intel Braswell USB 3.0 controller"); 162 case 0x31a88086: 163 return ("Intel Gemini Lake USB 3.0 controller"); 164 case 0x34ed8086: 165 return ("Intel Ice Lake-LP USB 3.1 controller"); 166 case 0x43ed8086: 167 return ("Intel Tiger Lake-H USB 3.2 controller"); 168 case 0x461e8086: 169 return ("Intel Alder Lake-P Thunderbolt 4 USB controller"); 170 case 0x51ed8086: 171 return ("Intel Alder Lake USB 3.2 controller"); 172 case 0x5aa88086: 173 return ("Intel Apollo Lake USB 3.0 controller"); 174 case 0x7ae08086: 175 return ("Intel Alder Lake USB 3.2 controller"); 176 case 0x8a138086: 177 return ("Intel Ice Lake Thunderbolt 3 USB controller"); 178 case 0x8c318086: 179 return ("Intel Lynx Point USB 3.0 controller"); 180 case 0x8cb18086: 181 return ("Intel Wildcat Point USB 3.0 controller"); 182 case 0x8d318086: 183 return ("Intel Wellsburg USB 3.0 controller"); 184 case 0x9a138086: 185 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller"); 186 case 0x9a178086: 187 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller"); 188 case 0x9cb18086: 189 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 190 case 0x9d2f8086: 191 return ("Intel Sunrise Point-LP USB 3.0 controller"); 192 case 0xa0ed8086: 193 return ("Intel Tiger Lake-LP USB 3.2 controller"); 194 case 0xa12f8086: 195 return ("Intel Sunrise Point USB 3.0 controller"); 196 case 0xa1af8086: 197 return ("Intel Lewisburg USB 3.0 controller"); 198 case 0xa2af8086: 199 return ("Intel Union Point USB 3.0 controller"); 200 case 0xa36d8086: 201 return ("Intel Cannon Lake USB 3.1 controller"); 202 203 case 0xa01b177d: 204 return ("Cavium ThunderX USB 3.0 controller"); 205 206 case 0x1ada10de: 207 return ("NVIDIA TU106 USB 3.1 controller"); 208 209 case 0x1d179202: 210 return ("Zhaoxin ZX-100 USB 3.0 controller"); 211 case 0x1d179203: 212 return ("Zhaoxin ZX-200 USB 3.0 controller"); 213 case 0x1d179204: 214 return ("Zhaoxin ZX-E USB 3.0 controller"); 215 216 default: 217 break; 218 } 219 220 if ((pci_get_class(self) == PCIC_SERIALBUS) 221 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 222 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 223 return ("XHCI (generic) USB 3.0 controller"); 224 } 225 return (NULL); /* dunno */ 226 } 227 228 static int 229 xhci_pci_probe(device_t self) 230 { 231 const char *desc = xhci_pci_match(self); 232 233 if (desc) { 234 device_set_desc(self, desc); 235 return (BUS_PROBE_DEFAULT); 236 } else { 237 return (ENXIO); 238 } 239 } 240 241 static int xhci_use_msi = 1; 242 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 243 static int xhci_use_msix = 1; 244 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 245 246 static void 247 xhci_interrupt_poll(void *_sc) 248 { 249 struct xhci_softc *sc = _sc; 250 USB_BUS_UNLOCK(&sc->sc_bus); 251 xhci_interrupt(sc); 252 USB_BUS_LOCK(&sc->sc_bus); 253 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 254 } 255 256 static int 257 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 258 { 259 uint32_t temp; 260 uint32_t usb3_mask; 261 uint32_t usb2_mask; 262 263 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 264 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 265 266 temp |= set; 267 temp &= ~clear; 268 269 /* Don't set bits which the hardware doesn't support */ 270 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 271 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 272 273 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 274 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 275 276 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 277 278 return (0); 279 } 280 281 int 282 xhci_pci_attach(device_t self) 283 { 284 struct xhci_softc *sc = device_get_softc(self); 285 int count, err, msix_table, rid; 286 uint8_t usemsi = 1; 287 uint8_t usedma32 = 0; 288 289 rid = PCI_XHCI_CBMEM; 290 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 291 RF_ACTIVE); 292 if (!sc->sc_io_res) { 293 device_printf(self, "Could not map memory\n"); 294 return (ENOMEM); 295 } 296 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 297 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 298 sc->sc_io_size = rman_get_size(sc->sc_io_res); 299 300 switch (pci_get_devid(self)) { 301 case 0x10091b73: /* Fresco Logic FL1009 USB3.0 xHCI Controller */ 302 case 0x8241104c: /* TUSB73x0 USB3.0 xHCI Controller */ 303 sc->sc_no_deconfigure = 1; 304 break; 305 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 306 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 307 /* Don't use 64-bit DMA on these controllers. */ 308 usedma32 = 1; 309 break; 310 case 0x10001b73: /* FL1000G */ 311 /* Fresco Logic host doesn't support MSI. */ 312 usemsi = 0; 313 break; 314 case 0x0f358086: /* BayTrail */ 315 case 0x9c318086: /* Panther Point */ 316 case 0x1e318086: /* Panther Point */ 317 case 0x8c318086: /* Lynx Point */ 318 case 0x8cb18086: /* Wildcat Point */ 319 case 0x9cb18086: /* Broadwell Mobile Integrated */ 320 /* 321 * On Intel chipsets, reroute ports from EHCI to XHCI 322 * controller and use a different IMOD value. 323 */ 324 sc->sc_port_route = &xhci_pci_port_route; 325 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 326 sc->sc_ctlstep = 1; 327 break; 328 default: 329 break; 330 } 331 332 if (xhci_init(sc, self, usedma32)) { 333 device_printf(self, "Could not initialize softc\n"); 334 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 335 sc->sc_io_res); 336 return (ENXIO); 337 } 338 339 pci_enable_busmaster(self); 340 341 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 342 343 rid = 0; 344 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 345 if (msix_table == PCI_XHCI_CBMEM) { 346 sc->sc_msix_res = sc->sc_io_res; 347 } else { 348 sc->sc_msix_res = bus_alloc_resource_any(self, 349 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 350 if (sc->sc_msix_res == NULL) { 351 /* May not be enabled */ 352 device_printf(self, 353 "Unable to map MSI-X table\n"); 354 } 355 } 356 if (sc->sc_msix_res != NULL) { 357 count = 1; 358 if (pci_alloc_msix(self, &count) == 0) { 359 if (bootverbose) 360 device_printf(self, "MSI-X enabled\n"); 361 rid = 1; 362 } else { 363 if (sc->sc_msix_res != sc->sc_io_res) { 364 bus_release_resource(self, 365 SYS_RES_MEMORY, 366 msix_table, sc->sc_msix_res); 367 } 368 sc->sc_msix_res = NULL; 369 } 370 } 371 } 372 if (rid == 0 && xhci_use_msi && usemsi) { 373 count = 1; 374 if (pci_alloc_msi(self, &count) == 0) { 375 if (bootverbose) 376 device_printf(self, "MSI enabled\n"); 377 rid = 1; 378 } 379 } 380 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 381 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 382 if (sc->sc_irq_res == NULL) { 383 pci_release_msi(self); 384 device_printf(self, "Could not allocate IRQ\n"); 385 /* goto error; FALLTHROUGH - use polling */ 386 } 387 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 388 if (sc->sc_bus.bdev == NULL) { 389 device_printf(self, "Could not add USB device\n"); 390 goto error; 391 } 392 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 393 394 switch (pci_get_vendor(self)) { 395 case PCI_XHCI_VENDORID_AMD: 396 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor)); 397 break; 398 case PCI_XHCI_VENDORID_INTEL: 399 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor)); 400 break; 401 case PCI_XHCI_VENDORID_VMWARE: 402 strlcpy(sc->sc_vendor, "VMware", sizeof(sc->sc_vendor)); 403 break; 404 case PCI_XHCI_VENDORID_ZHAOXIN: 405 strlcpy(sc->sc_vendor, "Zhaoxin", sizeof(sc->sc_vendor)); 406 break; 407 default: 408 if (bootverbose) 409 device_printf(self, "(New XHCI DeviceId=0x%08x)\n", 410 pci_get_devid(self)); 411 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 412 "(0x%04x)", pci_get_vendor(self)); 413 break; 414 } 415 416 if (sc->sc_irq_res != NULL && xhci_use_polling() == 0) { 417 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 418 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 419 if (err != 0) { 420 bus_release_resource(self, SYS_RES_IRQ, 421 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 422 sc->sc_irq_res = NULL; 423 pci_release_msi(self); 424 device_printf(self, "Could not setup IRQ, err=%d\n", err); 425 sc->sc_intr_hdl = NULL; 426 } 427 } 428 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 429 if (xhci_use_polling() != 0) { 430 device_printf(self, "Interrupt polling at %dHz\n", hz); 431 USB_BUS_LOCK(&sc->sc_bus); 432 xhci_interrupt_poll(sc); 433 USB_BUS_UNLOCK(&sc->sc_bus); 434 } else 435 goto error; 436 } 437 438 xhci_pci_take_controller(self); 439 440 err = xhci_halt_controller(sc); 441 442 if (err == 0) 443 err = xhci_start_controller(sc); 444 445 if (err == 0) 446 err = device_probe_and_attach(sc->sc_bus.bdev); 447 448 if (err) { 449 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 450 goto error; 451 } 452 return (0); 453 454 error: 455 xhci_pci_detach(self); 456 return (ENXIO); 457 } 458 459 static int 460 xhci_pci_detach(device_t self) 461 { 462 struct xhci_softc *sc = device_get_softc(self); 463 464 /* during module unload there are lots of children leftover */ 465 device_delete_children(self); 466 467 usb_callout_drain(&sc->sc_callout); 468 xhci_halt_controller(sc); 469 xhci_reset_controller(sc); 470 471 pci_disable_busmaster(self); 472 473 if (sc->sc_irq_res && sc->sc_intr_hdl) { 474 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 475 sc->sc_intr_hdl = NULL; 476 } 477 if (sc->sc_irq_res) { 478 bus_release_resource(self, SYS_RES_IRQ, 479 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 480 sc->sc_irq_res = NULL; 481 pci_release_msi(self); 482 } 483 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 484 bus_release_resource(self, SYS_RES_MEMORY, 485 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 486 sc->sc_msix_res = NULL; 487 } 488 if (sc->sc_io_res) { 489 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 490 sc->sc_io_res); 491 sc->sc_io_res = NULL; 492 } 493 494 xhci_uninit(sc); 495 496 return (0); 497 } 498 499 static int 500 xhci_pci_take_controller(device_t self) 501 { 502 struct xhci_softc *sc = device_get_softc(self); 503 uint32_t cparams; 504 uint32_t eecp; 505 uint32_t eec; 506 uint16_t to; 507 uint8_t bios_sem; 508 509 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 510 511 eec = -1; 512 513 /* Synchronise with the BIOS if it owns the controller. */ 514 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 515 eecp += XHCI_XECP_NEXT(eec) << 2) { 516 eec = XREAD4(sc, capa, eecp); 517 518 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 519 continue; 520 bios_sem = XREAD1(sc, capa, eecp + 521 XHCI_XECP_BIOS_SEM); 522 if (bios_sem == 0) 523 continue; 524 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 525 "to give up control\n"); 526 XWRITE1(sc, capa, eecp + 527 XHCI_XECP_OS_SEM, 1); 528 to = 500; 529 while (1) { 530 bios_sem = XREAD1(sc, capa, eecp + 531 XHCI_XECP_BIOS_SEM); 532 if (bios_sem == 0) 533 break; 534 535 if (--to == 0) { 536 device_printf(sc->sc_bus.bdev, 537 "timed out waiting for BIOS\n"); 538 break; 539 } 540 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 541 } 542 } 543 return (0); 544 }
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