FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/ehci.c
1 /* $NetBSD: ehci.c,v 1.91 2005/02/27 00:27:51 perry Exp $ */
2
3 /*-
4 * Copyright (c) 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net) and by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
41 *
42 * The EHCI 1.0 spec can be found at
43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
44 * and the USB 2.0 spec at
45 * http://www.usb.org/developers/docs/usb_20.zip
46 *
47 */
48
49 /*
50 * TODO:
51 * 1) The EHCI driver lacks support for isochronous transfers, so
52 * devices using them don't work.
53 *
54 * 2) Interrupt transfer scheduling does not manage the time available
55 * in each frame, so it is possible for the transfers to overrun
56 * the end of the frame.
57 *
58 * 3) Command failures are not recovered correctly.
59 */
60
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD: src/sys/dev/usb/ehci.c,v 1.67 2008/10/14 07:05:20 raj Exp $");
63
64 #include <sys/param.h>
65 #include <sys/systm.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/endian.h>
69 #include <sys/module.h>
70 #include <sys/bus.h>
71 #include <sys/lock.h>
72 #include <sys/lockmgr.h>
73 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__)
74 #include <machine/cpu.h>
75 #endif
76 #include <sys/proc.h>
77 #include <sys/queue.h>
78 #include <sys/sysctl.h>
79
80 #include <machine/bus.h>
81 #include <machine/endian.h>
82
83 #include <dev/usb/usb.h>
84 #include <dev/usb/usbdi.h>
85 #include <dev/usb/usbdivar.h>
86 #include <dev/usb/usb_mem.h>
87 #include <dev/usb/usb_quirks.h>
88
89 #include <dev/usb/ehcireg.h>
90 #include <dev/usb/ehcivar.h>
91
92 #define delay(d) DELAY(d)
93
94 #ifdef USB_DEBUG
95 #define EHCI_DEBUG USB_DEBUG
96 #define DPRINTF(x) do { if (ehcidebug) printf x; } while (0)
97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0)
98 int ehcidebug = 0;
99 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
100 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
101 &ehcidebug, 0, "ehci debug level");
102 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f))
103 #else
104 #define DPRINTF(x)
105 #define DPRINTFN(n,x)
106 #endif
107
108 struct ehci_pipe {
109 struct usbd_pipe pipe;
110
111 ehci_soft_qh_t *sqh;
112 union {
113 ehci_soft_qtd_t *qtd;
114 /* ehci_soft_itd_t *itd; */
115 } tail;
116 union {
117 /* Control pipe */
118 struct {
119 usb_dma_t reqdma;
120 u_int length;
121 /*ehci_soft_qtd_t *setup, *data, *stat;*/
122 } ctl;
123 /* Interrupt pipe */
124 struct {
125 u_int length;
126 } intr;
127 /* Bulk pipe */
128 struct {
129 u_int length;
130 } bulk;
131 /* Iso pipe */
132 struct {
133 u_int next_frame;
134 u_int cur_xfers;
135 } isoc;
136 } u;
137 };
138
139 static usbd_status ehci_open(usbd_pipe_handle);
140 static void ehci_poll(struct usbd_bus *);
141 static void ehci_softintr(void *);
142 static int ehci_intr1(ehci_softc_t *);
143 static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
144 static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
145 static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *);
146 static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *);
147 static void ehci_idone(struct ehci_xfer *);
148 static void ehci_timeout(void *);
149 static void ehci_timeout_task(void *);
150 static void ehci_intrlist_timeout(void *);
151
152 static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
153 static void ehci_freem(struct usbd_bus *, usb_dma_t *);
154
155 static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
156 static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
157
158 static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
159 static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
160 static void ehci_root_ctrl_abort(usbd_xfer_handle);
161 static void ehci_root_ctrl_close(usbd_pipe_handle);
162 static void ehci_root_ctrl_done(usbd_xfer_handle);
163
164 static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
165 static usbd_status ehci_root_intr_start(usbd_xfer_handle);
166 static void ehci_root_intr_abort(usbd_xfer_handle);
167 static void ehci_root_intr_close(usbd_pipe_handle);
168 static void ehci_root_intr_done(usbd_xfer_handle);
169
170 static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
171 static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
172 static void ehci_device_ctrl_abort(usbd_xfer_handle);
173 static void ehci_device_ctrl_close(usbd_pipe_handle);
174 static void ehci_device_ctrl_done(usbd_xfer_handle);
175
176 static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
177 static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
178 static void ehci_device_bulk_abort(usbd_xfer_handle);
179 static void ehci_device_bulk_close(usbd_pipe_handle);
180 static void ehci_device_bulk_done(usbd_xfer_handle);
181
182 static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
183 static usbd_status ehci_device_intr_start(usbd_xfer_handle);
184 static void ehci_device_intr_abort(usbd_xfer_handle);
185 static void ehci_device_intr_close(usbd_pipe_handle);
186 static void ehci_device_intr_done(usbd_xfer_handle);
187
188 static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
189 static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
190 static void ehci_device_isoc_abort(usbd_xfer_handle);
191 static void ehci_device_isoc_close(usbd_pipe_handle);
192 static void ehci_device_isoc_done(usbd_xfer_handle);
193
194 static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
195 static void ehci_noop(usbd_pipe_handle pipe);
196
197 static int ehci_str(usb_string_descriptor_t *, int, char *);
198 static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
199 static void ehci_disown(ehci_softc_t *, int, int);
200
201 static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
202 static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
203
204 static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
205 static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
206 static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
207 ehci_softc_t *, int, int, usbd_xfer_handle,
208 ehci_soft_qtd_t *, ehci_soft_qtd_t *,
209 ehci_soft_qtd_t **, ehci_soft_qtd_t **);
210 static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qh_t *,
211 ehci_soft_qtd_t *, ehci_soft_qtd_t *);
212
213 static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *);
214 static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *);
215 static void ehci_rem_free_itd_chain(ehci_softc_t *,
216 struct ehci_xfer *);
217 static void ehci_abort_isoc_xfer(usbd_xfer_handle, usbd_status);
218
219 static usbd_status ehci_device_request(usbd_xfer_handle xfer);
220
221 static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
222 int ival);
223
224 static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
225 static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
226 ehci_soft_qh_t *);
227 static void ehci_activate_qh(ehci_soft_qh_t *, ehci_soft_qtd_t *);
228 static void ehci_sync_hc(ehci_softc_t *);
229
230 static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
231 static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
232
233 #ifdef EHCI_DEBUG
234 static void ehci_dump_regs(ehci_softc_t *);
235 void ehci_dump(void);
236 static ehci_softc_t *theehci;
237 static void ehci_dump_link(ehci_link_t, int);
238 static void ehci_dump_sqtds(ehci_soft_qtd_t *);
239 static void ehci_dump_sqtd(ehci_soft_qtd_t *);
240 static void ehci_dump_qtd(ehci_qtd_t *);
241 static void ehci_dump_sqh(ehci_soft_qh_t *);
242 #ifdef notyet
243 static void ehci_dump_sitd(struct ehci_soft_itd *);
244 static void ehci_dump_itd(struct ehci_soft_itd *);
245 #endif
246 #ifdef DIAGNOSTIC
247 static void ehci_dump_exfer(struct ehci_xfer *);
248 #endif
249 #endif
250
251 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
252
253 #define EHCI_INTR_ENDPT 1
254
255 #define ehci_add_intr_list(sc, ex) \
256 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
257 #define ehci_del_intr_list(ex) \
258 do { \
259 LIST_REMOVE((ex), inext); \
260 (ex)->inext.le_prev = NULL; \
261 } while (0)
262 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL)
263
264 static struct usbd_bus_methods ehci_bus_methods = {
265 ehci_open,
266 ehci_softintr,
267 ehci_poll,
268 ehci_allocm,
269 ehci_freem,
270 ehci_allocx,
271 ehci_freex,
272 };
273
274 static struct usbd_pipe_methods ehci_root_ctrl_methods = {
275 ehci_root_ctrl_transfer,
276 ehci_root_ctrl_start,
277 ehci_root_ctrl_abort,
278 ehci_root_ctrl_close,
279 ehci_noop,
280 ehci_root_ctrl_done,
281 };
282
283 static struct usbd_pipe_methods ehci_root_intr_methods = {
284 ehci_root_intr_transfer,
285 ehci_root_intr_start,
286 ehci_root_intr_abort,
287 ehci_root_intr_close,
288 ehci_noop,
289 ehci_root_intr_done,
290 };
291
292 static struct usbd_pipe_methods ehci_device_ctrl_methods = {
293 ehci_device_ctrl_transfer,
294 ehci_device_ctrl_start,
295 ehci_device_ctrl_abort,
296 ehci_device_ctrl_close,
297 ehci_noop,
298 ehci_device_ctrl_done,
299 };
300
301 static struct usbd_pipe_methods ehci_device_intr_methods = {
302 ehci_device_intr_transfer,
303 ehci_device_intr_start,
304 ehci_device_intr_abort,
305 ehci_device_intr_close,
306 ehci_device_clear_toggle,
307 ehci_device_intr_done,
308 };
309
310 static struct usbd_pipe_methods ehci_device_bulk_methods = {
311 ehci_device_bulk_transfer,
312 ehci_device_bulk_start,
313 ehci_device_bulk_abort,
314 ehci_device_bulk_close,
315 ehci_device_clear_toggle,
316 ehci_device_bulk_done,
317 };
318
319 static struct usbd_pipe_methods ehci_device_isoc_methods = {
320 ehci_device_isoc_transfer,
321 ehci_device_isoc_start,
322 ehci_device_isoc_abort,
323 ehci_device_isoc_close,
324 ehci_noop,
325 ehci_device_isoc_done,
326 };
327
328 static usbd_status
329 ehci_hcreset(ehci_softc_t *sc)
330 {
331 u_int32_t hcr;
332 u_int i;
333
334 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
335 for (i = 0; i < 100; i++) {
336 usb_delay_ms(&sc->sc_bus, 1);
337 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
338 if (hcr)
339 break;
340 }
341 if (!hcr)
342 /*
343 * Fall through and try reset anyway even though
344 * Table 2-9 in the EHCI spec says this will result
345 * in undefined behavior.
346 */
347 printf("%s: stop timeout\n",
348 device_get_nameunit(sc->sc_bus.bdev));
349
350 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
351 for (i = 0; i < 100; i++) {
352 usb_delay_ms(&sc->sc_bus, 1);
353 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
354 if (!hcr) {
355 if (sc->sc_flags & EHCI_SCFLG_SETMODE)
356 EOWRITE4(sc, 0x68, 0x3);
357
358 return (USBD_NORMAL_COMPLETION);
359 }
360 }
361 printf("%s: reset timeout\n", device_get_nameunit(sc->sc_bus.bdev));
362 return (USBD_IOERROR);
363 }
364
365 usbd_status
366 ehci_init(ehci_softc_t *sc)
367 {
368 u_int32_t version, sparams, cparams, hcr;
369 u_int i;
370 usbd_status err;
371 ehci_soft_qh_t *sqh;
372 u_int ncomp;
373 int lev;
374
375 DPRINTF(("ehci_init: start\n"));
376 #ifdef EHCI_DEBUG
377 theehci = sc;
378 #endif
379
380 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
381
382 version = EREAD2(sc, EHCI_HCIVERSION);
383 printf("%s: EHCI version %x.%x\n", device_get_nameunit(sc->sc_bus.bdev),
384 version >> 8, version & 0xff);
385
386 sparams = EREAD4(sc, EHCI_HCSPARAMS);
387 DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
388 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
389 ncomp = EHCI_HCS_N_CC(sparams);
390 if (ncomp != sc->sc_ncomp) {
391 printf("%s: wrong number of companions (%d != %d)\n",
392 device_get_nameunit(sc->sc_bus.bdev),
393 ncomp, sc->sc_ncomp);
394 if (ncomp < sc->sc_ncomp)
395 sc->sc_ncomp = ncomp;
396 }
397 if (sc->sc_ncomp > 0) {
398 printf("%s: companion controller%s, %d port%s each:",
399 device_get_nameunit(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "",
400 EHCI_HCS_N_PCC(sparams),
401 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
402 for (i = 0; i < sc->sc_ncomp; i++)
403 printf(" %s", device_get_nameunit(sc->sc_comps[i]->bdev));
404 printf("\n");
405 }
406 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
407 cparams = EREAD4(sc, EHCI_HCCPARAMS);
408 DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
409
410 if (EHCI_HCC_64BIT(cparams)) {
411 /* MUST clear segment register if 64 bit capable. */
412 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
413 }
414
415 sc->sc_bus.usbrev = USBREV_2_0;
416
417 /* Reset the controller */
418 DPRINTF(("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)));
419 err = ehci_hcreset(sc);
420 if (err != USBD_NORMAL_COMPLETION)
421 return (err);
422
423 /* frame list size at default, read back what we got and use that */
424 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
425 case 0: sc->sc_flsize = 1024; break;
426 case 1: sc->sc_flsize = 512; break;
427 case 2: sc->sc_flsize = 256; break;
428 case 3: return (USBD_IOERROR);
429 }
430 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
431 EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
432 if (err)
433 return (err);
434 DPRINTF(("%s: flsize=%d\n", device_get_nameunit(sc->sc_bus.bdev),sc->sc_flsize));
435 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
436
437 for (i = 0; i < sc->sc_flsize; i++) {
438 sc->sc_flist[i] = EHCI_NULL;
439 }
440
441 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
442
443 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
444 M_USB, M_NOWAIT | M_ZERO);
445 if (sc->sc_softitds == NULL)
446 return (ENOMEM);
447 LIST_INIT(&sc->sc_freeitds);
448
449 /* Set up the bus struct. */
450 sc->sc_bus.methods = &ehci_bus_methods;
451 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
452
453 #if defined(__NetBSD__) || defined(__OpenBSD__)
454 sc->sc_powerhook = powerhook_establish(ehci_power, sc);
455 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc);
456 #endif
457
458 sc->sc_eintrs = EHCI_NORMAL_INTRS;
459
460 /*
461 * Allocate the interrupt dummy QHs. These are arranged to give
462 * poll intervals that are powers of 2 times 1ms.
463 */
464 for (i = 0; i < EHCI_INTRQHS; i++) {
465 sqh = ehci_alloc_sqh(sc);
466 if (sqh == NULL) {
467 err = USBD_NOMEM;
468 goto bad1;
469 }
470 sc->sc_islots[i].sqh = sqh;
471 }
472 lev = 0;
473 for (i = 0; i < EHCI_INTRQHS; i++) {
474 if (i == EHCI_IQHIDX(lev + 1, 0))
475 lev++;
476 sqh = sc->sc_islots[i].sqh;
477 if (i == 0) {
478 /* The last (1ms) QH terminates. */
479 sqh->qh.qh_link = EHCI_NULL;
480 sqh->next = NULL;
481 } else {
482 /* Otherwise the next QH has half the poll interval */
483 sqh->next =
484 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh;
485 sqh->qh.qh_link = htole32(sqh->next->physaddr |
486 EHCI_LINK_QH);
487 }
488 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
489 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
490 sqh->qh.qh_curqtd = EHCI_NULL;
491 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
492 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
493 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
494 }
495 /* Point the frame list at the last level (128ms). */
496 for (i = 0; i < sc->sc_flsize; i++) {
497 sc->sc_flist[i] = htole32(EHCI_LINK_QH |
498 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
499 i)].sqh->physaddr);
500 }
501
502 /* Allocate dummy QH that starts the async list. */
503 sqh = ehci_alloc_sqh(sc);
504 if (sqh == NULL) {
505 err = USBD_NOMEM;
506 goto bad1;
507 }
508 /* Fill the QH */
509 sqh->qh.qh_endp =
510 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
511 sqh->qh.qh_link =
512 htole32(sqh->physaddr | EHCI_LINK_QH);
513 sqh->qh.qh_curqtd = EHCI_NULL;
514 sqh->prev = sqh; /*It's a circular list.. */
515 sqh->next = sqh;
516 /* Fill the overlay qTD */
517 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
518 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
519 sqh->qh.qh_qtd.qtd_status = htole32(0);
520 #ifdef EHCI_DEBUG
521 if (ehcidebug) {
522 ehci_dump_sqh(sqh);
523 }
524 #endif
525
526 /* Point to async list */
527 sc->sc_async_head = sqh;
528 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
529
530 callout_init(&sc->sc_tmo_intrlist, 0);
531
532 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0);
533
534 /* Enable interrupts */
535 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
536
537 /* Turn on controller */
538 EOWRITE4(sc, EHCI_USBCMD,
539 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
540 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
541 EHCI_CMD_ASE |
542 EHCI_CMD_PSE |
543 EHCI_CMD_RS);
544
545 /* Take over port ownership */
546 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
547
548 for (i = 0; i < 100; i++) {
549 usb_delay_ms(&sc->sc_bus, 1);
550 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
551 if (!hcr)
552 break;
553 }
554 if (hcr) {
555 printf("%s: run timeout\n", device_get_nameunit(sc->sc_bus.bdev));
556 return (USBD_IOERROR);
557 }
558
559 return (USBD_NORMAL_COMPLETION);
560
561 #if 0
562 bad2:
563 ehci_free_sqh(sc, sc->sc_async_head);
564 #endif
565 bad1:
566 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
567 return (err);
568 }
569
570 int
571 ehci_intr(void *v)
572 {
573 ehci_softc_t *sc = v;
574
575 if (sc == NULL || sc->sc_dying)
576 return (0);
577
578 /* If we get an interrupt while polling, then just ignore it. */
579 if (sc->sc_bus.use_polling) {
580 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
581
582 if (intrs)
583 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
584 #ifdef DIAGNOSTIC
585 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
586 #endif
587 return (0);
588 }
589
590 return (ehci_intr1(sc));
591 }
592
593 static int
594 ehci_intr1(ehci_softc_t *sc)
595 {
596 u_int32_t intrs, eintrs;
597
598 DPRINTFN(20,("ehci_intr1: enter\n"));
599
600 /* In case the interrupt occurs before initialization has completed. */
601 if (sc == NULL) {
602 #ifdef DIAGNOSTIC
603 printf("ehci_intr1: sc == NULL\n");
604 #endif
605 return (0);
606 }
607
608 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
609 if (!intrs)
610 return (0);
611
612 eintrs = intrs & sc->sc_eintrs;
613 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
614 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
615 (u_int)eintrs));
616 if (!eintrs)
617 return (0);
618
619 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
620 sc->sc_bus.intr_context++;
621 sc->sc_bus.no_intrs++;
622 if (eintrs & EHCI_STS_IAA) {
623 DPRINTF(("ehci_intr1: door bell\n"));
624 wakeup(&sc->sc_async_head);
625 eintrs &= ~EHCI_STS_IAA;
626 }
627 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
628 DPRINTFN(5,("ehci_intr1: %s %s\n",
629 eintrs & EHCI_STS_INT ? "INT" : "",
630 eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
631 usb_schedsoftintr(&sc->sc_bus);
632 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
633 }
634 if (eintrs & EHCI_STS_HSE) {
635 printf("%s: unrecoverable error, controller halted\n",
636 device_get_nameunit(sc->sc_bus.bdev));
637 /* XXX what else */
638 }
639 if (eintrs & EHCI_STS_PCD) {
640 ehci_pcd(sc, sc->sc_intrxfer);
641 eintrs &= ~EHCI_STS_PCD;
642 }
643
644 sc->sc_bus.intr_context--;
645
646 if (eintrs != 0) {
647 /* Block unprocessed interrupts. */
648 sc->sc_eintrs &= ~eintrs;
649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
650 printf("%s: blocking intrs 0x%x\n",
651 device_get_nameunit(sc->sc_bus.bdev), eintrs);
652 }
653
654 return (1);
655 }
656
657 /*
658 * XXX write back xfer data for architectures with a write-back
659 * data cache; this is a hack because usb is mis-architected
660 * in blindly mixing bus_dma w/ PIO.
661 */
662 static __inline void
663 hacksync(usbd_xfer_handle xfer)
664 {
665 bus_dma_tag_t tag;
666 struct usb_dma_mapping *dmap;
667
668 if (xfer->length == 0)
669 return;
670 tag = xfer->pipe->device->bus->buffer_dmatag;
671 dmap = &xfer->dmamap;
672 bus_dmamap_sync(tag, dmap->map, BUS_DMASYNC_PREWRITE);
673 }
674
675 void
676 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
677 {
678 usbd_pipe_handle pipe;
679 u_char *p;
680 int i, m;
681
682 if (xfer == NULL) {
683 /* Just ignore the change. */
684 return;
685 }
686
687 pipe = xfer->pipe;
688
689 p = xfer->buffer;
690 m = min(sc->sc_noport, xfer->length * 8 - 1);
691 memset(p, 0, xfer->length);
692 for (i = 1; i <= m; i++) {
693 /* Pick out CHANGE bits from the status reg. */
694 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
695 p[i/8] |= 1 << (i%8);
696 }
697 DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
698 xfer->actlen = xfer->length;
699 xfer->status = USBD_NORMAL_COMPLETION;
700
701 hacksync(xfer); /* XXX to compensate for usb_transfer_complete */
702 usb_transfer_complete(xfer);
703 }
704
705 void
706 ehci_softintr(void *v)
707 {
708 ehci_softc_t *sc = v;
709 struct ehci_xfer *ex, *nextex;
710
711 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_get_nameunit(sc->sc_bus.bdev),
712 sc->sc_bus.intr_context));
713
714 sc->sc_bus.intr_context++;
715
716 /*
717 * The only explanation I can think of for why EHCI is as brain dead
718 * as UHCI interrupt-wise is that Intel was involved in both.
719 * An interrupt just tells us that something is done, we have no
720 * clue what, so we need to scan through all active transfers. :-(
721 */
722 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
723 nextex = LIST_NEXT(ex, inext);
724 ehci_check_intr(sc, ex);
725 }
726
727 /* Schedule a callout to catch any dropped transactions. */
728 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) &&
729 !LIST_EMPTY(&sc->sc_intrhead))
730 callout_reset(&sc->sc_tmo_intrlist, hz / 5,
731 ehci_intrlist_timeout, sc);
732
733 #ifdef USB_USE_SOFTINTR
734 if (sc->sc_softwake) {
735 sc->sc_softwake = 0;
736 wakeup(&sc->sc_softwake);
737 }
738 #endif /* USB_USE_SOFTINTR */
739
740 sc->sc_bus.intr_context--;
741 }
742
743 /* Check for an interrupt. */
744 void
745 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
746 {
747 int attr;
748
749 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
750
751 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes;
752 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS)
753 ehci_check_itd_intr(sc, ex);
754 else
755 ehci_check_qh_intr(sc, ex);
756 }
757
758 void
759 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
760 {
761 ehci_soft_qtd_t *sqtd, *lsqtd;
762 u_int32_t status;
763
764 if (ex->sqtdstart == NULL) {
765 printf("ehci_check_qh_intr: not valid sqtd\n");
766 return;
767 }
768 lsqtd = ex->sqtdend;
769 #ifdef DIAGNOSTIC
770 if (lsqtd == NULL) {
771 printf("ehci_check_qh_intr: lsqtd==0\n");
772 return;
773 }
774 #endif
775 /*
776 * If the last TD is still active we need to check whether there
777 * is a an error somewhere in the middle, or whether there was a
778 * short packet (SPD and not ACTIVE).
779 */
780 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
781 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
782 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
783 status = le32toh(sqtd->qtd.qtd_status);
784 /* If there's an active QTD the xfer isn't done. */
785 if (status & EHCI_QTD_ACTIVE)
786 break;
787 /* Any kind of error makes the xfer done. */
788 if (status & EHCI_QTD_HALTED)
789 goto done;
790 /* We want short packets, and it is short: it's done */
791 if (EHCI_QTD_GET_BYTES(status) != 0)
792 goto done;
793 }
794 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
795 ex, ex->sqtdstart));
796 return;
797 }
798 done:
799 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
800 callout_stop(&ex->xfer.timeout_handle);
801 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task);
802 ehci_idone(ex);
803 }
804
805 void
806 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
807 {
808 ehci_soft_itd_t *itd;
809 int i;
810
811 if (ex->itdstart == NULL) {
812 printf("ehci_check_itd_intr: not valid itd\n");
813 return;
814 }
815
816 itd = ex->itdend;
817 #ifdef DIAGNOSTIC
818 if (itd == NULL) {
819 printf("ehci_check_itd_intr: itdend == 0\n");
820 return;
821 }
822 #endif
823
824 /*
825 * Step 1, check no active transfers in last itd, meaning we're finished
826 */
827 for (i = 0; i < 8; i++) {
828 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
829 break;
830 }
831
832 if (i == 8) {
833 goto done; /* All 8 descriptors inactive, it's done */
834 }
835
836 /*
837 * Step 2, check for errors in status bits, throughout chain...
838 */
839
840 DPRINTFN(12, ("ehci_check_itd_intr: active ex=%p\n", ex));
841
842 for (itd = ex->itdstart; itd != ex->itdend; itd = itd->xfer_next) {
843 for (i = 0; i < 8; i++) {
844 if (le32toh(itd->itd.itd_ctl[i]) & (EHCI_ITD_BUF_ERR |
845 EHCI_ITD_BABBLE | EHCI_ITD_ERROR))
846 break;
847 }
848 if (i != 8) { /* Error in one of the itds */
849 goto done;
850 }
851 } /* itd search loop */
852
853 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex,
854 ex->itdstart));
855 return;
856 done:
857 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex));
858 callout_stop(&ex->xfer.timeout_handle);
859 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task);
860 ehci_idone(ex);
861 }
862
863 void
864 ehci_idone(struct ehci_xfer *ex)
865 {
866 usbd_xfer_handle xfer = &ex->xfer;
867 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
868 ehci_soft_qtd_t *sqtd, *lsqtd;
869 u_int32_t status = 0, nstatus = 0;
870 ehci_physaddr_t nextphys, altnextphys;
871 int actlen, cerr;
872
873 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
874 #ifdef DIAGNOSTIC
875 {
876 int s = splhigh();
877 if (ex->isdone) {
878 splx(s);
879 #ifdef EHCI_DEBUG
880 printf("ehci_idone: ex is done!\n ");
881 ehci_dump_exfer(ex);
882 #else
883 printf("ehci_idone: ex=%p is done!\n", ex);
884 #endif
885 return;
886 }
887 ex->isdone = 1;
888 splx(s);
889 }
890 #endif
891
892 if (xfer->status == USBD_CANCELLED ||
893 xfer->status == USBD_TIMEOUT) {
894 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
895 return;
896 }
897
898 #ifdef EHCI_DEBUG
899 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
900 if (ehcidebug > 10)
901 ehci_dump_sqtds(ex->sqtdstart);
902 #endif
903
904 /*
905 * Make sure that the QH overlay qTD does not reference any
906 * of the qTDs we are about to free. This is probably only
907 * necessary if the transfer is marked as HALTED.
908 */
909 nextphys = EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_next));
910 altnextphys =
911 EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_altnext));
912 for (sqtd = ex->sqtdstart; sqtd != ex->sqtdend->nextqtd;
913 sqtd = sqtd->nextqtd) {
914 if (sqtd->physaddr == nextphys) {
915 epipe->sqh->qh.qh_qtd.qtd_next =
916 htole32(ex->sqtdend->nextqtd->physaddr);
917 DPRINTFN(4, ("ehci_idone: updated overlay next ptr\n"));
918
919 }
920 if (sqtd->physaddr == altnextphys) {
921 DPRINTFN(4,
922 ("ehci_idone: updated overlay altnext ptr\n"));
923 epipe->sqh->qh.qh_qtd.qtd_altnext =
924 htole32(ex->sqtdend->nextqtd->physaddr);
925 }
926 }
927
928 /* The transfer is done, compute actual length and status. */
929 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)
930 == UE_ISOCHRONOUS) {
931 /* Isoc transfer */
932 struct ehci_soft_itd *itd;
933 int i, nframes, len, uframes;
934
935 nframes = 0;
936 actlen = 0;
937
938 switch (xfer->pipe->endpoint->edesc->bInterval) {
939 case 0:
940 panic("ehci: isoc xfer suddenly has 0 bInterval, "
941 "invalid\n");
942 case 1:
943 uframes = 1;
944 break;
945 case 2:
946 uframes = 2;
947 break;
948 case 3:
949 uframes = 4;
950 break;
951 default:
952 uframes = 8;
953 break;
954 }
955
956 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) {
957 for (i = 0; i < 8; i += uframes) {
958 /* XXX - driver didn't fill in the frame full
959 * of uframes. This leads to scheduling
960 * inefficiencies, but working around
961 * this doubles complexity of tracking
962 * an xfer.
963 */
964 if (nframes >= xfer->nframes)
965 break;
966
967 status = le32toh(itd->itd.itd_ctl[i]);
968 len = EHCI_ITD_GET_LEN(status);
969 xfer->frlengths[nframes++] = len;
970 actlen += len;
971 }
972 if (nframes >= xfer->nframes)
973 break;
974 }
975 xfer->actlen = actlen;
976 xfer->status = USBD_NORMAL_COMPLETION;
977
978 goto end;
979 }
980
981 /* Continue processing xfers using queue heads */
982
983 lsqtd = ex->sqtdend;
984 actlen = 0;
985 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd;
986 sqtd =sqtd->nextqtd) {
987 nstatus = le32toh(sqtd->qtd.qtd_status);
988 if (nstatus & EHCI_QTD_ACTIVE)
989 break;
990
991 status = nstatus;
992 /* halt is ok if descriptor is last, and complete */
993 if (sqtd == lsqtd && EHCI_QTD_GET_BYTES(status) == 0)
994 status &= ~EHCI_QTD_HALTED;
995 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
996 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
997 }
998
999 cerr = EHCI_QTD_GET_CERR(status);
1000 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, "
1001 "status=0x%x\n", xfer->length, actlen, cerr, status));
1002 xfer->actlen = actlen;
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