1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Copyright (c) 2006
6 * Alfred Perlstein <alfred@freebsd.org>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/usb/if_auereg.h,v 1.27 2007/01/08 23:24:21 alfred Exp $
36 */
37
38 /*
39 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
40 * chip. The Pegasus uses a total of four USB endpoints: the control
41 * endpoint (0), a bulk read endpoint for receiving packets (1),
42 * a bulk write endpoint for sending packets (2) and an interrupt
43 * endpoint for passing RX and TX status (3). Endpoint 0 is used
44 * to read and write the ethernet module's registers. All registers
45 * are 8 bits wide.
46 *
47 * Packet transfer is done in 64 byte chunks. The last chunk in a
48 * transfer is denoted by having a length less that 64 bytes. For
49 * the RX case, the data includes an optional RX status word.
50 */
51
52 #ifndef AUEREG_H
53 #define AUEREG_H
54
55 #define AUE_UR_READREG 0xF0
56 #define AUE_UR_WRITEREG 0xF1
57
58 #define AUE_CONFIG_NO 1
59 #define AUE_IFACE_IDX 0
60
61 /*
62 * Note that while the ADMtek technically has four
63 * endpoints, the control endpoint (endpoint 0) is
64 * regarded as special by the USB code and drivers
65 * don't have direct access to it. (We access it
66 * using usbd_do_request() when reading/writing
67 * registers.) Consequently, our endpoint indexes
68 * don't match those in the ADMtek Pegasus manual:
69 * we consider the RX data endpoint to be index 0
70 * and work up from there.
71 */
72 #define AUE_ENDPT_RX 0x0
73 #define AUE_ENDPT_TX 0x1
74 #define AUE_ENDPT_INTR 0x2
75 #define AUE_ENDPT_MAX 0x3
76
77 #define AUE_INTR_PKTLEN 0x8
78
79 #define AUE_CTL0 0x00
80 #define AUE_CTL1 0x01
81 #define AUE_CTL2 0x02
82 #define AUE_MAR0 0x08
83 #define AUE_MAR1 0x09
84 #define AUE_MAR2 0x0A
85 #define AUE_MAR3 0x0B
86 #define AUE_MAR4 0x0C
87 #define AUE_MAR5 0x0D
88 #define AUE_MAR6 0x0E
89 #define AUE_MAR7 0x0F
90 #define AUE_MAR AUE_MAR0
91 #define AUE_PAR0 0x10
92 #define AUE_PAR1 0x11
93 #define AUE_PAR2 0x12
94 #define AUE_PAR3 0x13
95 #define AUE_PAR4 0x14
96 #define AUE_PAR5 0x15
97 #define AUE_PAR AUE_PAR0
98 #define AUE_PAUSE0 0x18
99 #define AUE_PAUSE1 0x19
100 #define AUE_PAUSE AUE_PAUSE0
101 #define AUE_RX_FLOWCTL_CNT 0x1A
102 #define AUE_RX_FLOWCTL_FIFO 0x1B
103 #define AUE_REG_1D 0x1D
104 #define AUE_EE_REG 0x20
105 #define AUE_EE_DATA0 0x21
106 #define AUE_EE_DATA1 0x22
107 #define AUE_EE_DATA AUE_EE_DATA0
108 #define AUE_EE_CTL 0x23
109 #define AUE_PHY_ADDR 0x25
110 #define AUE_PHY_DATA0 0x26
111 #define AUE_PHY_DATA1 0x27
112 #define AUE_PHY_DATA AUE_PHY_DATA0
113 #define AUE_PHY_CTL 0x28
114 #define AUE_USB_STS 0x2A
115 #define AUE_TXSTAT0 0x2B
116 #define AUE_TXSTAT1 0x2C
117 #define AUE_TXSTAT AUE_TXSTAT0
118 #define AUE_RXSTAT 0x2D
119 #define AUE_PKTLOST0 0x2E
120 #define AUE_PKTLOST1 0x2F
121 #define AUE_PKTLOST AUE_PKTLOST0
122
123 #define AUE_REG_7B 0x7B
124 #define AUE_GPIO0 0x7E
125 #define AUE_GPIO1 0x7F
126 #define AUE_REG_81 0x81
127
128 #define AUE_CTL0_INCLUDE_RXCRC 0x01
129 #define AUE_CTL0_ALLMULTI 0x02
130 #define AUE_CTL0_STOP_BACKOFF 0x04
131 #define AUE_CTL0_RXSTAT_APPEND 0x08
132 #define AUE_CTL0_WAKEON_ENB 0x10
133 #define AUE_CTL0_RXPAUSE_ENB 0x20
134 #define AUE_CTL0_RX_ENB 0x40
135 #define AUE_CTL0_TX_ENB 0x80
136
137 #define AUE_CTL1_HOMELAN 0x04
138 #define AUE_CTL1_RESETMAC 0x08
139 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */
140 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */
141 #define AUE_CTL1_DELAYHOME 0x40
142
143 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */
144 #define AUE_CTL2_RX_BADFRAMES 0x02
145 #define AUE_CTL2_RX_PROMISC 0x04
146 #define AUE_CTL2_LOOPBACK 0x08
147 #define AUE_CTL2_EEPROMWR_ENB 0x10
148 #define AUE_CTL2_EEPROM_LOAD 0x20
149
150 #define AUE_EECTL_WRITE 0x01
151 #define AUE_EECTL_READ 0x02
152 #define AUE_EECTL_DONE 0x04
153
154 #define AUE_PHYCTL_PHYREG 0x1F
155 #define AUE_PHYCTL_WRITE 0x20
156 #define AUE_PHYCTL_READ 0x40
157 #define AUE_PHYCTL_DONE 0x80
158
159 #define AUE_USBSTS_SUSPEND 0x01
160 #define AUE_USBSTS_RESUME 0x02
161
162 #define AUE_TXSTAT0_JABTIMO 0x04
163 #define AUE_TXSTAT0_CARLOSS 0x08
164 #define AUE_TXSTAT0_NOCARRIER 0x10
165 #define AUE_TXSTAT0_LATECOLL 0x20
166 #define AUE_TXSTAT0_EXCESSCOLL 0x40
167 #define AUE_TXSTAT0_UNDERRUN 0x80
168
169 #define AUE_TXSTAT1_PKTCNT 0x0F
170 #define AUE_TXSTAT1_FIFO_EMPTY 0x40
171 #define AUE_TXSTAT1_FIFO_FULL 0x80
172
173 #define AUE_RXSTAT_OVERRUN 0x01
174 #define AUE_RXSTAT_PAUSE 0x02
175
176 #define AUE_GPIO_IN0 0x01
177 #define AUE_GPIO_OUT0 0x02
178 #define AUE_GPIO_SEL0 0x04
179 #define AUE_GPIO_IN1 0x08
180 #define AUE_GPIO_OUT1 0x10
181 #define AUE_GPIO_SEL1 0x20
182
183 struct aue_intrpkt {
184 u_int8_t aue_txstat0;
185 u_int8_t aue_txstat1;
186 u_int8_t aue_rxstat;
187 u_int8_t aue_rxlostpkt0;
188 u_int8_t aue_rxlostpkt1;
189 u_int8_t aue_wakeupstat;
190 u_int8_t aue_rsvd;
191 };
192
193 struct aue_rxpkt {
194 u_int16_t aue_pktlen;
195 u_int8_t aue_rxstat;
196 };
197
198 #define AUE_RXSTAT_MCAST 0x01
199 #define AUE_RXSTAT_GIANT 0x02
200 #define AUE_RXSTAT_RUNT 0x04
201 #define AUE_RXSTAT_CRCERR 0x08
202 #define AUE_RXSTAT_DRIBBLE 0x10
203 #define AUE_RXSTAT_MASK 0x1E
204
205 #define AUE_INC(x, y) (x) = (x + 1) % y
206
207 struct aue_softc {
208 #if defined(__FreeBSD__)
209 #define GET_MII(sc) (device_get_softc((sc)->aue_miibus))
210 #elif defined(__NetBSD__)
211 #define GET_MII(sc) (&(sc)->aue_mii)
212 #elif defined(__OpenBSD__)
213 #define GET_MII(sc) (&(sc)->aue_mii)
214 #endif
215 struct ifnet *aue_ifp;
216 device_t aue_dev;
217 device_t aue_miibus;
218 usbd_device_handle aue_udev;
219 usbd_interface_handle aue_iface;
220 u_int16_t aue_vendor;
221 u_int16_t aue_product;
222 int aue_ed[AUE_ENDPT_MAX];
223 usbd_pipe_handle aue_ep[AUE_ENDPT_MAX];
224 int aue_unit;
225 u_int8_t aue_link;
226 int aue_timer;
227 int aue_if_flags;
228 struct ue_cdata aue_cdata;
229 struct callout aue_tick_callout;
230 struct usb_taskqueue aue_taskqueue;
231 struct task aue_task;
232 struct mtx aue_mtx;
233 struct sx aue_sx;
234 u_int16_t aue_flags;
235 char aue_dying;
236 struct timeval aue_rx_notice;
237 struct usb_qdat aue_qdat;
238 int aue_deferedtasks;
239 };
240
241 #if 0
242 /*
243 * Some debug code to make sure we don't take a blocking lock in
244 * interrupt context.
245 */
246 #include <sys/types.h>
247 #include <sys/proc.h>
248 #include <sys/kdb.h>
249
250 #define AUE_DUMPSTATE(tag) aue_dumpstate(__func__, tag)
251
252 static inline void
253 aue_dumpstate(const char *func, const char *tag)
254 {
255 if ((curthread->td_pflags & TDP_NOSLEEPING) ||
256 (curthread->td_pflags & TDP_ITHREAD)) {
257 kdb_backtrace();
258 printf("%s: %s sleep: %sok ithread: %s\n", func, tag,
259 curthread->td_pflags & TDP_NOSLEEPING ? "not" : "",
260 curthread->td_pflags & TDP_ITHREAD ? "yes" : "no");
261 }
262 }
263 #else
264 #define AUE_DUMPSTATE(tag)
265 #endif
266
267 #define AUE_LOCK(_sc) mtx_lock(&(_sc)->aue_mtx)
268 #define AUE_UNLOCK(_sc) mtx_unlock(&(_sc)->aue_mtx)
269 #define AUE_SXLOCK(_sc) \
270 do { AUE_DUMPSTATE("sxlock"); sx_xlock(&(_sc)->aue_sx); } while(0)
271 #define AUE_SXUNLOCK(_sc) sx_xunlock(&(_sc)->aue_sx)
272 #define AUE_SXASSERTLOCKED(_sc) sx_assert(&(_sc)->aue_sx, SX_XLOCKED)
273 #define AUE_SXASSERTUNLOCKED(_sc) sx_assert(&(_sc)->aue_sx, SX_UNLOCKED)
274
275 #define AUE_TIMEOUT 1000
276 #define AUE_MIN_FRAMELEN 60
277 #define AUE_INTR_INTERVAL 100 /* ms */
278
279 /*
280 * These bits are used to notify the task about pending events.
281 * The names correspond to the interrupt context routines that would
282 * be normally called. (example: AUE_TASK_WATCHDOG -> aue_watchdog())
283 */
284 #define AUE_TASK_WATCHDOG 0x0001
285 #define AUE_TASK_TICK 0x0002
286 #define AUE_TASK_START 0x0004
287 #define AUE_TASK_RXSTART 0x0008
288 #define AUE_TASK_RXEOF 0x0010
289 #define AUE_TASK_TXEOF 0x0020
290
291 #define AUE_GIANTLOCK() mtx_lock(&Giant);
292 #define AUE_GIANTUNLOCK() mtx_unlock(&Giant);
293
294 #endif /* !AUEREG_H */
295
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