1 /*-
2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/dev/usb/if_cuereg.h,v 1.20 2007/06/11 05:42:47 imp Exp $
33 */
34
35 /*
36 * Definitions for the CATC Netmate II USB to ethernet controller.
37 */
38
39
40 /*
41 * Vendor specific control commands.
42 */
43 #define CUE_CMD_RESET 0xF4
44 #define CUE_CMD_GET_MACADDR 0xF2
45 #define CUE_CMD_WRITEREG 0xFA
46 #define CUE_CMD_READREG 0xFB
47 #define CUE_CMD_READSRAM 0xF1
48 #define CUE_CMD_WRITESRAM 0xFC
49
50 /*
51 * Internal registers
52 */
53 #define CUE_TX_BUFCNT 0x20
54 #define CUE_RX_BUFCNT 0x21
55 #define CUE_ADVANCED_OPMODES 0x22
56 #define CUE_TX_BUFPKTS 0x23
57 #define CUE_RX_BUFPKTS 0x24
58 #define CUE_RX_MAXCHAIN 0x25
59
60 #define CUE_ETHCTL 0x60
61 #define CUE_ETHSTS 0x61
62 #define CUE_PAR5 0x62
63 #define CUE_PAR4 0x63
64 #define CUE_PAR3 0x64
65 #define CUE_PAR2 0x65
66 #define CUE_PAR1 0x66
67 #define CUE_PAR0 0x67
68
69 /* Error counters, all 16 bits wide. */
70 #define CUE_TX_SINGLECOLL 0x69
71 #define CUE_TX_MULTICOLL 0x6B
72 #define CUE_TX_EXCESSCOLL 0x6D
73 #define CUE_RX_FRAMEERR 0x6F
74
75 #define CUE_LEDCTL 0x81
76
77 /* Advenced operating mode register */
78 #define CUE_AOP_SRAMWAITS 0x03
79 #define CUE_AOP_EMBED_RXLEN 0x08
80 #define CUE_AOP_RXCOMBINE 0x10
81 #define CUE_AOP_TXCOMBINE 0x20
82 #define CUE_AOP_EVEN_PKT_READS 0x40
83 #define CUE_AOP_LOOPBK 0x80
84
85 /* Ethernet control register */
86 #define CUE_ETHCTL_RX_ON 0x01
87 #define CUE_ETHCTL_LINK_POLARITY 0x02
88 #define CUE_ETHCTL_LINK_FORCE_OK 0x04
89 #define CUE_ETHCTL_MCAST_ON 0x08
90 #define CUE_ETHCTL_PROMISC 0x10
91
92 /* Ethernet status register */
93 #define CUE_ETHSTS_NO_CARRIER 0x01
94 #define CUE_ETHSTS_LATECOLL 0x02
95 #define CUE_ETHSTS_EXCESSCOLL 0x04
96 #define CUE_ETHSTS_TXBUF_AVAIL 0x08
97 #define CUE_ETHSTS_BAD_POLARITY 0x10
98 #define CUE_ETHSTS_LINK_OK 0x20
99
100 /* LED control register */
101 #define CUE_LEDCTL_BLINK_1X 0x00
102 #define CUE_LEDCTL_BLINK_2X 0x01
103 #define CUE_LEDCTL_BLINK_QUARTER_ON 0x02
104 #define CUE_LEDCTL_BLINK_QUARTER_OFF 0x03
105 #define CUE_LEDCTL_OFF 0x04
106 #define CUE_LEDCTL_FOLLOW_LINK 0x08
107
108 /*
109 * Address in ASIC's internal SRAM where the
110 * multicast hash table lives. The table is 64 bytes long,
111 * giving us a 512-bit table. We have to set the bit that
112 * corresponds to the broadcast address in order to enable
113 * reception of broadcast frames.
114 */
115 #define CUE_MCAST_TABLE_ADDR 0xFA80
116 #define CUE_MCAST_TABLE_LEN 64
117
118 #define CUE_TIMEOUT 1000
119 #define CUE_MIN_FRAMELEN 60
120 #define CUE_RX_FRAMES 1
121 #define CUE_TX_FRAMES 1
122
123 #define CUE_CTL_READ 0x01
124 #define CUE_CTL_WRITE 0x02
125
126 #define CUE_CONFIG_NO 1
127
128 /*
129 * The interrupt endpoint is currently unused
130 * by the KLSI part.
131 */
132 #define CUE_ENDPT_RX 0x0
133 #define CUE_ENDPT_TX 0x1
134 #define CUE_ENDPT_INTR 0x2
135 #define CUE_ENDPT_MAX 0x3
136
137 struct cue_type {
138 u_int16_t cue_vid;
139 u_int16_t cue_did;
140 };
141
142 #define CUE_INC(x, y) (x) = (x + 1) % y
143
144 struct cue_softc {
145 struct ifnet *cue_ifp;
146 device_t cue_dev;
147 usbd_device_handle cue_udev;
148 usbd_interface_handle cue_iface;
149 int cue_ed[CUE_ENDPT_MAX];
150 usbd_pipe_handle cue_ep[CUE_ENDPT_MAX];
151 u_int8_t cue_mctab[CUE_MCAST_TABLE_LEN];
152 int cue_if_flags;
153 u_int16_t cue_rxfilt;
154 struct ue_cdata cue_cdata;
155 struct callout_handle cue_stat_ch;
156 struct mtx cue_mtx;
157 char cue_dying;
158 struct timeval cue_rx_notice;
159 struct usb_qdat cue_qdat;
160 };
161
162 #if 0
163 #define CUE_LOCK(_sc) mtx_lock(&(_sc)->cue_mtx)
164 #define CUE_UNLOCK(_sc) mtx_unlock(&(_sc)->cue_mtx)
165 #else
166 #define CUE_LOCK(_sc)
167 #define CUE_UNLOCK(_sc)
168 #endif
169
|