The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/if_uralreg.h

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    1 /*      $FreeBSD: releng/7.3/sys/dev/usb/if_uralreg.h 170530 2007-06-11 03:36:55Z sam $ */
    2 
    3 /*-
    4  * Copyright (c) 2005, 2006
    5  *      Damien Bergamini <damien.bergamini@free.fr>
    6  *
    7  * Permission to use, copy, modify, and distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  */
   19 
   20 #define RAL_NOISE_FLOOR         -95
   21 #define RAL_RSSI_CORR           120
   22 
   23 #define RAL_RX_DESC_SIZE        (sizeof (struct ural_rx_desc))
   24 #define RAL_TX_DESC_SIZE        (sizeof (struct ural_tx_desc))
   25 
   26 #define RAL_CONFIG_NO   1
   27 #define RAL_IFACE_INDEX 0
   28 
   29 #define RAL_VENDOR_REQUEST      0x01
   30 #define RAL_WRITE_MAC           0x02
   31 #define RAL_READ_MAC            0x03
   32 #define RAL_WRITE_MULTI_MAC     0x06
   33 #define RAL_READ_MULTI_MAC      0x07
   34 #define RAL_READ_EEPROM         0x09
   35 
   36 /*
   37  * MAC registers.
   38  */
   39 #define RAL_MAC_CSR0    0x0400  /* ASIC Version */
   40 #define RAL_MAC_CSR1    0x0402  /* System control */
   41 #define RAL_MAC_CSR2    0x0404  /* MAC addr0 */
   42 #define RAL_MAC_CSR3    0x0406  /* MAC addr1 */
   43 #define RAL_MAC_CSR4    0x0408  /* MAC addr2 */
   44 #define RAL_MAC_CSR5    0x040a  /* BSSID0 */
   45 #define RAL_MAC_CSR6    0x040c  /* BSSID1 */
   46 #define RAL_MAC_CSR7    0x040e  /* BSSID2 */
   47 #define RAL_MAC_CSR8    0x0410  /* Max frame length */
   48 #define RAL_MAC_CSR9    0x0412  /* Timer control */
   49 #define RAL_MAC_CSR10   0x0414  /* Slot time */
   50 #define RAL_MAC_CSR11   0x0416  /* IFS */
   51 #define RAL_MAC_CSR12   0x0418  /* EIFS */
   52 #define RAL_MAC_CSR13   0x041a  /* Power mode0 */
   53 #define RAL_MAC_CSR14   0x041c  /* Power mode1 */
   54 #define RAL_MAC_CSR15   0x041e  /* Power saving transition0 */
   55 #define RAL_MAC_CSR16   0x0420  /* Power saving transition1 */
   56 #define RAL_MAC_CSR17   0x0422  /* Power state control */
   57 #define RAL_MAC_CSR18   0x0424  /* Auto wake-up control */
   58 #define RAL_MAC_CSR19   0x0426  /* GPIO control */
   59 #define RAL_MAC_CSR20   0x0428  /* LED control0 */
   60 #define RAL_MAC_CSR22   0x042c  /* XXX not documented */
   61 
   62 /*
   63  * Tx/Rx Registers.
   64  */
   65 #define RAL_TXRX_CSR0   0x0440  /* Security control */
   66 #define RAL_TXRX_CSR2   0x0444  /* Rx control */
   67 #define RAL_TXRX_CSR5   0x044a  /* CCK Tx BBP ID0 */
   68 #define RAL_TXRX_CSR6   0x044c  /* CCK Tx BBP ID1 */
   69 #define RAL_TXRX_CSR7   0x044e  /* OFDM Tx BBP ID0 */
   70 #define RAL_TXRX_CSR8   0x0450  /* OFDM Tx BBP ID1 */
   71 #define RAL_TXRX_CSR10  0x0454  /* Auto responder control */
   72 #define RAL_TXRX_CSR11  0x0456  /* Auto responder basic rate */
   73 #define RAL_TXRX_CSR18  0x0464  /* Beacon interval */
   74 #define RAL_TXRX_CSR19  0x0466  /* Beacon/sync control */
   75 #define RAL_TXRX_CSR20  0x0468  /* Beacon alignment */
   76 #define RAL_TXRX_CSR21  0x046a  /* XXX not documented */
   77 
   78 /*
   79  * Security registers.
   80  */
   81 #define RAL_SEC_CSR0    0x0480  /* Shared key 0, word 0 */
   82 
   83 /*
   84  * PHY registers.
   85  */
   86 #define RAL_PHY_CSR2    0x04c4  /* Tx MAC configuration */
   87 #define RAL_PHY_CSR4    0x04c8  /* Interface configuration */
   88 #define RAL_PHY_CSR5    0x04ca  /* BBP Pre-Tx CCK */
   89 #define RAL_PHY_CSR6    0x04cc  /* BBP Pre-Tx OFDM */
   90 #define RAL_PHY_CSR7    0x04ce  /* BBP serial control */
   91 #define RAL_PHY_CSR8    0x04d0  /* BBP serial status */
   92 #define RAL_PHY_CSR9    0x04d2  /* RF serial control0 */
   93 #define RAL_PHY_CSR10   0x04d4  /* RF serial control1 */
   94 
   95 /*
   96  * Statistics registers.
   97  */
   98 #define RAL_STA_CSR0    0x04e0  /* FCS error */
   99 
  100 
  101 #define RAL_DISABLE_RX          (1 << 0)
  102 #define RAL_DROP_CRC            (1 << 1)
  103 #define RAL_DROP_PHY            (1 << 2)
  104 #define RAL_DROP_CTL            (1 << 3)
  105 #define RAL_DROP_NOT_TO_ME      (1 << 4)
  106 #define RAL_DROP_TODS           (1 << 5)
  107 #define RAL_DROP_BAD_VERSION    (1 << 6)
  108 #define RAL_DROP_MULTICAST      (1 << 9)
  109 #define RAL_DROP_BROADCAST      (1 << 10)
  110 
  111 #define RAL_SHORT_PREAMBLE      (1 << 2)
  112 
  113 #define RAL_RESET_ASIC  (1 << 0)
  114 #define RAL_RESET_BBP   (1 << 1)
  115 #define RAL_HOST_READY  (1 << 2)
  116 
  117 #define RAL_ENABLE_TSF                  (1 << 0)
  118 #define RAL_ENABLE_TSF_SYNC(x)          (((x) & 0x3) << 1)
  119 #define RAL_ENABLE_TBCN                 (1 << 3)
  120 #define RAL_ENABLE_BEACON_GENERATOR     (1 << 4)
  121 
  122 #define RAL_RF_AWAKE    (3 << 7)
  123 #define RAL_BBP_AWAKE   (3 << 5)
  124 
  125 #define RAL_BBP_WRITE   (1 << 15)
  126 #define RAL_BBP_BUSY    (1 << 0)
  127 
  128 #define RAL_RF1_AUTOTUNE        0x08000
  129 #define RAL_RF3_AUTOTUNE        0x00040
  130 
  131 #define RAL_RF_2522     0x00
  132 #define RAL_RF_2523     0x01
  133 #define RAL_RF_2524     0x02
  134 #define RAL_RF_2525     0x03
  135 #define RAL_RF_2525E    0x04
  136 #define RAL_RF_2526     0x05
  137 /* dual-band RF */
  138 #define RAL_RF_5222     0x10
  139 
  140 #define RAL_BBP_VERSION 0
  141 #define RAL_BBP_TX      2
  142 #define RAL_BBP_RX      14
  143 
  144 #define RAL_BBP_ANTA            0x00
  145 #define RAL_BBP_DIVERSITY       0x01
  146 #define RAL_BBP_ANTB            0x02
  147 #define RAL_BBP_ANTMASK         0x03
  148 #define RAL_BBP_FLIPIQ          0x04
  149 
  150 #define RAL_JAPAN_FILTER        0x08
  151 
  152 struct ural_tx_desc {
  153         uint32_t        flags;
  154 #define RAL_TX_RETRY(x)         ((x) << 4)
  155 #define RAL_TX_MORE_FRAG        (1 << 8)
  156 #define RAL_TX_ACK              (1 << 9)
  157 #define RAL_TX_TIMESTAMP        (1 << 10)
  158 #define RAL_TX_OFDM             (1 << 11)
  159 #define RAL_TX_NEWSEQ           (1 << 12)
  160 
  161 #define RAL_TX_IFS_MASK         0x00006000
  162 #define RAL_TX_IFS_BACKOFF      (0 << 13)
  163 #define RAL_TX_IFS_SIFS         (1 << 13)
  164 #define RAL_TX_IFS_NEWBACKOFF   (2 << 13)
  165 #define RAL_TX_IFS_NONE         (3 << 13)
  166 
  167         uint16_t        wme;
  168 #define RAL_LOGCWMAX(x)         (((x) & 0xf) << 12)
  169 #define RAL_LOGCWMIN(x)         (((x) & 0xf) << 8)
  170 #define RAL_AIFSN(x)            (((x) & 0x3) << 6)
  171 #define RAL_IVOFFSET(x)         (((x) & 0x3f))
  172 
  173         uint16_t        reserved1;
  174         uint8_t         plcp_signal;
  175         uint8_t         plcp_service;
  176 #define RAL_PLCP_LENGEXT        0x80
  177 
  178         uint8_t         plcp_length_lo;
  179         uint8_t         plcp_length_hi;
  180         uint32_t        iv;
  181         uint32_t        eiv;
  182 } __packed;
  183 
  184 struct ural_rx_desc {
  185         uint32_t        flags;
  186 #define RAL_RX_CRC_ERROR        (1 << 5)
  187 #define RAL_RX_OFDM             (1 << 6)
  188 #define RAL_RX_PHY_ERROR        (1 << 7)
  189 
  190         uint8_t         rssi;
  191         uint8_t         rate;
  192         uint16_t        reserved;
  193 
  194         uint32_t        iv;
  195         uint32_t        eiv;
  196 } __packed;
  197 
  198 #define RAL_RF_LOBUSY   (1 << 15)
  199 #define RAL_RF_BUSY     (1 << 31)
  200 #define RAL_RF_20BIT    (20 << 24)
  201 
  202 #define RAL_RF1 0
  203 #define RAL_RF2 2
  204 #define RAL_RF3 1
  205 #define RAL_RF4 3
  206 
  207 #define RAL_EEPROM_ADDRESS      0x0004
  208 #define RAL_EEPROM_TXPOWER      0x003c
  209 #define RAL_EEPROM_CONFIG0      0x0016
  210 #define RAL_EEPROM_BBP_BASE     0x001c

Cache object: 75eb364faae8e53c95873ccc1843b990


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