if_urlreg.h

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    1 /*      $NetBSD: if_urlreg.h,v 1.2 2003/09/04 15:17:39 tsutsui Exp $    */
    2 /*
    3  * Copyright (c) 2001, 2002
    4  *     Shingo WATANABE <nabe@nabechan.org>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. Neither the name of the author nor the names of any co-contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  */
   31 
   32 #define URL_IFACE_INDEX         0
   33 #define URL_CONFIG_NO           1
   34 
   35 #define URL_TX_LIST_CNT         1
   36 #define URL_RX_LIST_CNT         1
   37 
   38 #define URL_TX_TIMEOUT          1000
   39 #define URL_TIMEOUT             10000
   40 
   41 #define ETHER_ALIGN             2
   42 
   43 
   44 /* Packet length */
   45 #define URL_MAX_MTU             1536
   46 #define URL_MIN_FRAME_LEN       60
   47 #define URL_BUFSZ               URL_MAX_MTU
   48 
   49 /* Request */
   50 #define URL_REQ_MEM             0x05
   51 
   52 #define URL_CMD_READMEM         1
   53 #define URL_CMD_WRITEMEM        2
   54 
   55 /* Registers */
   56 #define URL_IDR0                0x0120 /* Ethernet Address, load from 93C46 */
   57 #define URL_IDR1                0x0121 /* Ethernet Address, load from 93C46 */
   58 #define URL_IDR2                0x0122 /* Ethernet Address, load from 93C46 */
   59 #define URL_IDR3                0x0123 /* Ethernet Address, load from 93C46 */
   60 #define URL_IDR4                0x0124 /* Ethernet Address, load from 93C46 */
   61 #define URL_IDR5                0x0125 /* Ethernet Address, load from 93C46 */
   62 
   63 #define URL_MAR0                0x0126 /* Multicast register */
   64 #define URL_MAR1                0x0127 /* Multicast register */
   65 #define URL_MAR2                0x0128 /* Multicast register */
   66 #define URL_MAR3                0x0129 /* Multicast register */
   67 #define URL_MAR4                0x012a /* Multicast register */
   68 #define URL_MAR5                0x012b /* Multicast register */
   69 #define URL_MAR6                0x012c /* Multicast register */
   70 #define URL_MAR7                0x012d /* Multicast register */
   71 #define URL_MAR                 URL_MAR0
   72 
   73 #define URL_CR                  0x012e /* Command Register */
   74 #define  URL_CR_WEPROM          (1<<5) /* EEPROM Write Enable */
   75 #define  URL_CR_SOFT_RST        (1<<4) /* Software Reset */
   76 #define  URL_CR_RE              (1<<3) /* Ethernet Receive Enable */
   77 #define  URL_CR_TE              (1<<2) /* Ethernet Transmit Enable */
   78 #define  URL_CR_EP3CLREN        (1<<1) /* Enable clearing the performance counter */
   79 #define  URL_CR_AUTOLOAD        (1<<0) /* Auto-load the contents of 93C46 */
   80 
   81 #define URL_TCR                 0x012f /* Transmit Control Register */
   82 #define  URL_TCR_TXRR1          (1<<7) /* TX Retry Count */
   83 #define  URL_TCR_TXRR0          (1<<6) /* TX Retry Count */
   84 #define  URL_TCR_IFG1           (1<<4) /* Interframe Gap Time */
   85 #define  URL_TCR_IFG0           (1<<4) /* Interframe Gap Time */
   86 #define  URL_TCR_NOCRC          (1<<0) /* no CRC Append */
   87 
   88 #define URL_RCR                 0x0130 /* Receive Configuration Register */
   89 #define  URL_RCR_TAIL           (1<<7)
   90 #define  URL_RCR_AER            (1<<6)
   91 #define  URL_RCR_AR             (1<<5)
   92 #define  URL_RCR_AM             (1<<4)
   93 #define  URL_RCR_AB             (1<<3)
   94 #define  URL_RCR_AD             (1<<2)
   95 #define  URL_RCR_AAM            (1<<1)
   96 #define  URL_RCR_AAP            (1<<0)
   97 
   98 #define URL_MSR                 0x137 /* Media Status Register */
   99 #define  URL_MSR_TXFCE          (1<<7)
  100 #define  URL_MSR_RXFCE          (1<<6)
  101 #define  URL_MSR_DUPLEX         (1<<4)
  102 #define  URL_MSR_SPEED_100      (1<<3)
  103 #define  URL_MSR_LINK           (1<<2)
  104 #define  URL_MSR_TXPF           (1<<1)
  105 #define  URL_MSR_RXPF           (1<<0)
  106 
  107 #define URL_PHYADD              0x138 /* MII PHY Address select */
  108 #define  URL_PHYADD_MASK        0x1f /* MII PHY Address select */
  109 
  110 #define URL_PHYDAT              0x139 /* MII PHY data */
  111 
  112 #define URL_PHYCNT              0x13b /* MII PHY control */
  113 #define  URL_PHYCNT_PHYOWN      (1<<6) /* Own bit */
  114 #define  URL_PHYCNT_RWCR        (1<<5) /* MII management data R/W control */
  115 #define  URL_PHY_PHYOFF_MASK    0x1f /* PHY register offset */
  116 
  117 #define URL_BMCR                0x140 /* Basic mode control register */
  118 #define URL_BMSR                0x142 /* Basic mode status register */
  119 #define URL_ANAR                0x144 /* Auto-negotiation advertisement register */
  120 #define URL_ANLP                0x146 /* Auto-negotiation link partner ability register */
  121 
  122 
  123 typedef uWord url_rxhdr_t;      /* Recive Header */
  124 #define URL_RXHDR_BYTEC_MASK    (0x0fff) /* RX bytes count */
  125 #define URL_RXHDR_VALID_MASK    (0x1000) /* Valid packet */
  126 #define URL_RXHDR_RUNTPKT_MASK  (0x2000) /* Runt packet */
  127 #define URL_RXHDR_PHYPKT_MASK   (0x4000) /* Physical match packet */
  128 #define URL_RXHDR_MCASTPKT_MASK (0x8000) /* Multicast packet */
  129 
  130 #define GET_IFP(sc)             (&(sc)->sc_ec.ec_if)
  131 #define GET_MII(sc)             (&(sc)->sc_mii)
  132 
  133 struct url_chain {
  134         struct url_softc        *url_sc;
  135         usbd_xfer_handle        url_xfer;
  136         char                    *url_buf;
  137         struct mbuf             *url_mbuf;
  138         int                     url_idx;
  139 };
  140 
  141 struct url_cdata {
  142         struct url_chain        url_tx_chain[URL_TX_LIST_CNT];
  143         struct url_chain        url_rx_chain[URL_TX_LIST_CNT];
  144 #if 0
  145         /* XXX: Intrrupt Endpoint is not yet supported! */
  146         struct url_intrpkg      url_ibuf;
  147 #endif
  148         int                     url_tx_prod;
  149         int                     url_tx_cons;
  150         int                     url_tx_cnt;
  151         int                     url_rx_prod;
  152 };
  153 
  154 struct url_softc {
  155         USBBASEDEVICE           sc_dev; /* base device */
  156         usbd_device_handle      sc_udev;
  157 
  158         /* USB */
  159         usbd_interface_handle   sc_ctl_iface;
  160         /* int                  sc_ctl_iface_no; */
  161         int                     sc_bulkin_no; /* bulk in endpoint */
  162         int                     sc_bulkout_no; /* bulk out endpoint */
  163         int                     sc_intrin_no; /* intr in endpoint */
  164         usbd_pipe_handle        sc_pipe_rx;
  165         usbd_pipe_handle        sc_pipe_tx;
  166         usbd_pipe_handle        sc_pipe_intr;
  167         usb_callout_t           sc_stat_ch;
  168         u_int                   sc_rx_errs;
  169         /* u_int                sc_intr_errs; */
  170         struct timeval          sc_rx_notice;
  171 
  172         /* Ethernet */
  173         struct ethercom         sc_ec; /* ethernet common */
  174         struct mii_data         sc_mii;
  175         struct lock             sc_mii_lock;
  176         int                     sc_link;
  177 #define sc_media url_mii.mii_media
  178 #if NRND > 0
  179         rndsource_element_t     rnd_source;
  180 #endif
  181         struct url_cdata        sc_cdata;
  182 
  183         int                     sc_attached;
  184         int                     sc_dying;
  185         int                     sc_refcnt;
  186 
  187         struct usb_task         sc_tick_task;
  188         struct usb_task         sc_stop_task;
  189 
  190         u_int16_t               sc_flags;
  191 };

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FreeBSD/Linux Kernel Cross Reference sys/dev/usb/if_urlreg.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/if_urlreg.h