FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/net/if_axe.c
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 /*
39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
40 * Used in the LinkSys USB200M and various other adapters.
41 *
42 * Manuals available from:
43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
45 * controller) to find the definitions for the RX control register.
46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
47 *
48 * Written by Bill Paul <wpaul@windriver.com>
49 * Senior Engineer
50 * Wind River Systems
51 */
52
53 /*
54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
55 * It uses an external PHY (reference designs use a RealTek chip),
56 * and has a 64-bit multicast hash filter. There is some information
57 * missing from the manual which one needs to know in order to make
58 * the chip function:
59 *
60 * - You must set bit 7 in the RX control register, otherwise the
61 * chip won't receive any packets.
62 * - You must initialize all 3 IPG registers, or you won't be able
63 * to send any packets.
64 *
65 * Note that this device appears to only support loading the station
66 * address via autload from the EEPROM (i.e. there's no way to manually
67 * set it).
68 *
69 * (Adam Weinberger wanted me to name this driver if_gir.c.)
70 */
71
72 /*
73 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
74 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
75 *
76 * Manual here:
77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
79 */
80
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/bus.h>
84 #include <sys/condvar.h>
85 #include <sys/endian.h>
86 #include <sys/kernel.h>
87 #include <sys/lock.h>
88 #include <sys/malloc.h>
89 #include <sys/mbuf.h>
90 #include <sys/module.h>
91 #include <sys/mutex.h>
92 #include <sys/socket.h>
93 #include <sys/sockio.h>
94 #include <sys/sysctl.h>
95 #include <sys/sx.h>
96
97 #include <net/if.h>
98 #include <net/if_var.h>
99 #include <net/ethernet.h>
100 #include <net/if_types.h>
101 #include <net/if_media.h>
102 #include <net/if_vlan_var.h>
103
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106
107 #include <dev/usb/usb.h>
108 #include <dev/usb/usbdi.h>
109 #include <dev/usb/usbdi_util.h>
110 #include "usbdevs.h"
111
112 #define USB_DEBUG_VAR axe_debug
113 #include <dev/usb/usb_debug.h>
114 #include <dev/usb/usb_process.h>
115
116 #include <dev/usb/net/usb_ethernet.h>
117 #include <dev/usb/net/if_axereg.h>
118
119 #include "miibus_if.h"
120
121 /*
122 * AXE_178_MAX_FRAME_BURST
123 * max frame burst size for Ax88178 and Ax88772
124 * 0 2048 bytes
125 * 1 4096 bytes
126 * 2 8192 bytes
127 * 3 16384 bytes
128 * use the largest your system can handle without USB stalling.
129 *
130 * NB: 88772 parts appear to generate lots of input errors with
131 * a 2K rx buffer and 8K is only slightly faster than 4K on an
132 * EHCI port on a T42 so change at your own risk.
133 */
134 #define AXE_178_MAX_FRAME_BURST 1
135
136 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137
138 #ifdef USB_DEBUG
139 static int axe_debug = 0;
140
141 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
142 "USB axe");
143 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0,
144 "Debug level");
145 #endif
146
147 /*
148 * Various supported device vendors/products.
149 */
150 static const STRUCT_USB_HOST_ID axe_devs[] = {
151 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
152 AXE_DEV(ABOCOM, UF200, 0),
153 AXE_DEV(ACERCM, EP1427X2, 0),
154 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
155 AXE_DEV(ASIX, AX88172, 0),
156 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
157 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
158 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
159 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
160 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
161 AXE_DEV(ATEN, UC210T, 0),
162 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
163 AXE_DEV(BILLIONTON, USB2AR, 0),
164 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
165 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
166 AXE_DEV(DLINK, DUBE100, 0),
167 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
168 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B),
169 AXE_DEV(GOODWAY, GWUSB2E, 0),
170 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
171 AXE_DEV(JVC, MP_PRX1, 0),
172 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B),
173 AXE_DEV(LINKSYS2, USB200M, 0),
174 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
175 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
176 AXE_DEV(MELCO, LUAU2KTX, 0),
177 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
178 AXE_DEV(NETGEAR, FA120, 0),
179 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
180 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
181 AXE_DEV(SITECOM, LN029, 0),
182 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
183 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178),
184 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
185 #undef AXE_DEV
186 };
187
188 static device_probe_t axe_probe;
189 static device_attach_t axe_attach;
190 static device_detach_t axe_detach;
191
192 static usb_callback_t axe_bulk_read_callback;
193 static usb_callback_t axe_bulk_write_callback;
194
195 static miibus_readreg_t axe_miibus_readreg;
196 static miibus_writereg_t axe_miibus_writereg;
197 static miibus_statchg_t axe_miibus_statchg;
198
199 static uether_fn_t axe_attach_post;
200 static uether_fn_t axe_init;
201 static uether_fn_t axe_stop;
202 static uether_fn_t axe_start;
203 static uether_fn_t axe_tick;
204 static uether_fn_t axe_setmulti;
205 static uether_fn_t axe_setpromisc;
206
207 static int axe_attach_post_sub(struct usb_ether *);
208 static int axe_ifmedia_upd(struct ifnet *);
209 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
210 static int axe_cmd(struct axe_softc *, int, int, int, void *);
211 static void axe_ax88178_init(struct axe_softc *);
212 static void axe_ax88772_init(struct axe_softc *);
213 static void axe_ax88772_phywake(struct axe_softc *);
214 static void axe_ax88772a_init(struct axe_softc *);
215 static void axe_ax88772b_init(struct axe_softc *);
216 static int axe_get_phyno(struct axe_softc *, int);
217 static int axe_ioctl(struct ifnet *, u_long, caddr_t);
218 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
219 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
220 unsigned offset, unsigned, struct axe_csum_hdr *);
221 static void axe_csum_cfg(struct usb_ether *);
222
223 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
224 [AXE_BULK_DT_WR] = {
225 .type = UE_BULK,
226 .endpoint = UE_ADDR_ANY,
227 .direction = UE_DIR_OUT,
228 .frames = 16,
229 .bufsize = 16 * MCLBYTES,
230 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
231 .callback = axe_bulk_write_callback,
232 .timeout = 10000, /* 10 seconds */
233 },
234
235 [AXE_BULK_DT_RD] = {
236 .type = UE_BULK,
237 .endpoint = UE_ADDR_ANY,
238 .direction = UE_DIR_IN,
239 .bufsize = 16384, /* bytes */
240 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
241 .callback = axe_bulk_read_callback,
242 .timeout = 0, /* no timeout */
243 },
244 };
245
246 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
247 { 0x8000, 0x8001, 2048 },
248 { 0x8100, 0x8147, 4096},
249 { 0x8200, 0x81EB, 6144},
250 { 0x8300, 0x83D7, 8192},
251 { 0x8400, 0x851E, 16384},
252 { 0x8500, 0x8666, 20480},
253 { 0x8600, 0x87AE, 24576},
254 { 0x8700, 0x8A3D, 32768}
255 };
256
257 static device_method_t axe_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, axe_probe),
260 DEVMETHOD(device_attach, axe_attach),
261 DEVMETHOD(device_detach, axe_detach),
262
263 /* MII interface */
264 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
265 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
266 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
267
268 DEVMETHOD_END
269 };
270
271 static driver_t axe_driver = {
272 .name = "axe",
273 .methods = axe_methods,
274 .size = sizeof(struct axe_softc),
275 };
276
277 DRIVER_MODULE(axe, uhub, axe_driver, NULL, NULL);
278 DRIVER_MODULE(miibus, axe, miibus_driver, 0, 0);
279 MODULE_DEPEND(axe, uether, 1, 1, 1);
280 MODULE_DEPEND(axe, usb, 1, 1, 1);
281 MODULE_DEPEND(axe, ether, 1, 1, 1);
282 MODULE_DEPEND(axe, miibus, 1, 1, 1);
283 MODULE_VERSION(axe, 1);
284 USB_PNP_HOST_INFO(axe_devs);
285
286 static const struct usb_ether_methods axe_ue_methods = {
287 .ue_attach_post = axe_attach_post,
288 .ue_attach_post_sub = axe_attach_post_sub,
289 .ue_start = axe_start,
290 .ue_init = axe_init,
291 .ue_stop = axe_stop,
292 .ue_tick = axe_tick,
293 .ue_setmulti = axe_setmulti,
294 .ue_setpromisc = axe_setpromisc,
295 .ue_mii_upd = axe_ifmedia_upd,
296 .ue_mii_sts = axe_ifmedia_sts,
297 };
298
299 static int
300 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
301 {
302 struct usb_device_request req;
303 usb_error_t err;
304
305 AXE_LOCK_ASSERT(sc, MA_OWNED);
306
307 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
308 UT_WRITE_VENDOR_DEVICE :
309 UT_READ_VENDOR_DEVICE);
310 req.bRequest = AXE_CMD_CMD(cmd);
311 USETW(req.wValue, val);
312 USETW(req.wIndex, index);
313 USETW(req.wLength, AXE_CMD_LEN(cmd));
314
315 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
316
317 return (err);
318 }
319
320 static int
321 axe_miibus_readreg(device_t dev, int phy, int reg)
322 {
323 struct axe_softc *sc = device_get_softc(dev);
324 uint16_t val;
325 int locked;
326
327 locked = mtx_owned(&sc->sc_mtx);
328 if (!locked)
329 AXE_LOCK(sc);
330
331 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
332 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
333 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
334
335 val = le16toh(val);
336 if (AXE_IS_772(sc) && reg == MII_BMSR) {
337 /*
338 * BMSR of AX88772 indicates that it supports extended
339 * capability but the extended status register is
340 * revered for embedded ethernet PHY. So clear the
341 * extended capability bit of BMSR.
342 */
343 val &= ~BMSR_EXTCAP;
344 }
345
346 if (!locked)
347 AXE_UNLOCK(sc);
348 return (val);
349 }
350
351 static int
352 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
353 {
354 struct axe_softc *sc = device_get_softc(dev);
355 int locked;
356
357 val = htole32(val);
358 locked = mtx_owned(&sc->sc_mtx);
359 if (!locked)
360 AXE_LOCK(sc);
361
362 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
363 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
364 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
365
366 if (!locked)
367 AXE_UNLOCK(sc);
368 return (0);
369 }
370
371 static void
372 axe_miibus_statchg(device_t dev)
373 {
374 struct axe_softc *sc = device_get_softc(dev);
375 struct mii_data *mii = GET_MII(sc);
376 struct ifnet *ifp;
377 uint16_t val;
378 int err, locked;
379
380 locked = mtx_owned(&sc->sc_mtx);
381 if (!locked)
382 AXE_LOCK(sc);
383
384 ifp = uether_getifp(&sc->sc_ue);
385 if (mii == NULL || ifp == NULL ||
386 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
387 goto done;
388
389 sc->sc_flags &= ~AXE_FLAG_LINK;
390 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
391 (IFM_ACTIVE | IFM_AVALID)) {
392 switch (IFM_SUBTYPE(mii->mii_media_active)) {
393 case IFM_10_T:
394 case IFM_100_TX:
395 sc->sc_flags |= AXE_FLAG_LINK;
396 break;
397 case IFM_1000_T:
398 if ((sc->sc_flags & AXE_FLAG_178) == 0)
399 break;
400 sc->sc_flags |= AXE_FLAG_LINK;
401 break;
402 default:
403 break;
404 }
405 }
406
407 /* Lost link, do nothing. */
408 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
409 goto done;
410
411 val = 0;
412 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
413 val |= AXE_MEDIA_FULL_DUPLEX;
414 if (AXE_IS_178_FAMILY(sc)) {
415 if ((IFM_OPTIONS(mii->mii_media_active) &
416 IFM_ETH_TXPAUSE) != 0)
417 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
418 if ((IFM_OPTIONS(mii->mii_media_active) &
419 IFM_ETH_RXPAUSE) != 0)
420 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
421 }
422 }
423 if (AXE_IS_178_FAMILY(sc)) {
424 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
425 if ((sc->sc_flags & AXE_FLAG_178) != 0)
426 val |= AXE_178_MEDIA_ENCK;
427 switch (IFM_SUBTYPE(mii->mii_media_active)) {
428 case IFM_1000_T:
429 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
430 break;
431 case IFM_100_TX:
432 val |= AXE_178_MEDIA_100TX;
433 break;
434 case IFM_10_T:
435 /* doesn't need to be handled */
436 break;
437 }
438 }
439 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
440 if (err)
441 device_printf(dev, "media change failed, error %d\n", err);
442 done:
443 if (!locked)
444 AXE_UNLOCK(sc);
445 }
446
447 /*
448 * Set media options.
449 */
450 static int
451 axe_ifmedia_upd(struct ifnet *ifp)
452 {
453 struct axe_softc *sc = ifp->if_softc;
454 struct mii_data *mii = GET_MII(sc);
455 struct mii_softc *miisc;
456 int error;
457
458 AXE_LOCK_ASSERT(sc, MA_OWNED);
459
460 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
461 PHY_RESET(miisc);
462 error = mii_mediachg(mii);
463 return (error);
464 }
465
466 /*
467 * Report current media status.
468 */
469 static void
470 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
471 {
472 struct axe_softc *sc = ifp->if_softc;
473 struct mii_data *mii = GET_MII(sc);
474
475 AXE_LOCK(sc);
476 mii_pollstat(mii);
477 ifmr->ifm_active = mii->mii_media_active;
478 ifmr->ifm_status = mii->mii_media_status;
479 AXE_UNLOCK(sc);
480 }
481
482 static u_int
483 axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
484 {
485 uint8_t *hashtbl = arg;
486 uint32_t h;
487
488 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
489 hashtbl[h / 8] |= 1 << (h % 8);
490
491 return (1);
492 }
493
494 static void
495 axe_setmulti(struct usb_ether *ue)
496 {
497 struct axe_softc *sc = uether_getsc(ue);
498 struct ifnet *ifp = uether_getifp(ue);
499 uint16_t rxmode;
500 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
501
502 AXE_LOCK_ASSERT(sc, MA_OWNED);
503
504 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
505 rxmode = le16toh(rxmode);
506
507 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
508 rxmode |= AXE_RXCMD_ALLMULTI;
509 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
510 return;
511 }
512 rxmode &= ~AXE_RXCMD_ALLMULTI;
513
514 if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl);
515
516 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
517 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
518 }
519
520 static int
521 axe_get_phyno(struct axe_softc *sc, int sel)
522 {
523 int phyno;
524
525 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
526 case PHY_TYPE_100_HOME:
527 case PHY_TYPE_GIG:
528 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
529 break;
530 case PHY_TYPE_SPECIAL:
531 /* FALLTHROUGH */
532 case PHY_TYPE_RSVD:
533 /* FALLTHROUGH */
534 case PHY_TYPE_NON_SUP:
535 /* FALLTHROUGH */
536 default:
537 phyno = -1;
538 break;
539 }
540
541 return (phyno);
542 }
543
544 #define AXE_GPIO_WRITE(x, y) do { \
545 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
546 uether_pause(ue, (y)); \
547 } while (0)
548
549 static void
550 axe_ax88178_init(struct axe_softc *sc)
551 {
552 struct usb_ether *ue;
553 int gpio0, ledmode, phymode;
554 uint16_t eeprom, val;
555
556 ue = &sc->sc_ue;
557 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
558 /* XXX magic */
559 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
560 eeprom = le16toh(eeprom);
561 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
562
563 /* if EEPROM is invalid we have to use to GPIO0 */
564 if (eeprom == 0xffff) {
565 phymode = AXE_PHY_MODE_MARVELL;
566 gpio0 = 1;
567 ledmode = 0;
568 } else {
569 phymode = eeprom & 0x7f;
570 gpio0 = (eeprom & 0x80) ? 0 : 1;
571 ledmode = eeprom >> 8;
572 }
573
574 if (bootverbose)
575 device_printf(sc->sc_ue.ue_dev,
576 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
577 phymode);
578 /* Program GPIOs depending on PHY hardware. */
579 switch (phymode) {
580 case AXE_PHY_MODE_MARVELL:
581 if (gpio0 == 1) {
582 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
583 hz / 32);
584 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
585 hz / 32);
586 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
587 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
588 hz / 32);
589 } else {
590 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
591 AXE_GPIO1_EN, hz / 3);
592 if (ledmode == 1) {
593 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
594 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
595 hz / 3);
596 } else {
597 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
598 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
600 AXE_GPIO2_EN, hz / 4);
601 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
602 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
603 }
604 }
605 break;
606 case AXE_PHY_MODE_CICADA:
607 case AXE_PHY_MODE_CICADA_V2:
608 case AXE_PHY_MODE_CICADA_V2_ASIX:
609 if (gpio0 == 1)
610 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
611 AXE_GPIO0_EN, hz / 32);
612 else
613 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
614 AXE_GPIO1_EN, hz / 32);
615 break;
616 case AXE_PHY_MODE_AGERE:
617 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
618 AXE_GPIO1_EN, hz / 32);
619 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
620 AXE_GPIO2_EN, hz / 32);
621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
622 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
623 AXE_GPIO2_EN, hz / 32);
624 break;
625 case AXE_PHY_MODE_REALTEK_8211CL:
626 case AXE_PHY_MODE_REALTEK_8211BN:
627 case AXE_PHY_MODE_REALTEK_8251CL:
628 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
629 AXE_GPIO1 | AXE_GPIO1_EN;
630 AXE_GPIO_WRITE(val, hz / 32);
631 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
632 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
633 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
634 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
635 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
636 0x1F, 0x0005);
637 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
638 0x0C, 0x0000);
639 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
640 0x0001);
641 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
642 0x01, val | 0x0080);
643 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
644 0x1F, 0x0000);
645 }
646 break;
647 default:
648 /* Unknown PHY model or no need to program GPIOs. */
649 break;
650 }
651
652 /* soft reset */
653 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
654 uether_pause(ue, hz / 4);
655
656 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
657 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
658 uether_pause(ue, hz / 4);
659 /* Enable MII/GMII/RGMII interface to work with external PHY. */
660 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
661 uether_pause(ue, hz / 4);
662
663 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
664 }
665
666 static void
667 axe_ax88772_init(struct axe_softc *sc)
668 {
669 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
670 uether_pause(&sc->sc_ue, hz / 16);
671
672 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
673 /* ask for the embedded PHY */
674 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
675 uether_pause(&sc->sc_ue, hz / 64);
676
677 /* power down and reset state, pin reset state */
678 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
679 AXE_SW_RESET_CLEAR, NULL);
680 uether_pause(&sc->sc_ue, hz / 16);
681
682 /* power down/reset state, pin operating state */
683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
684 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
685 uether_pause(&sc->sc_ue, hz / 4);
686
687 /* power up, reset */
688 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
689
690 /* power up, operating */
691 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
692 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
693 } else {
694 /* ask for external PHY */
695 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
696 uether_pause(&sc->sc_ue, hz / 64);
697
698 /* power down internal PHY */
699 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
700 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
701 }
702
703 uether_pause(&sc->sc_ue, hz / 4);
704 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
705 }
706
707 static void
708 axe_ax88772_phywake(struct axe_softc *sc)
709 {
710 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
711 /* Manually select internal(embedded) PHY - MAC mode. */
712 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
713 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
714 NULL);
715 uether_pause(&sc->sc_ue, hz / 32);
716 } else {
717 /*
718 * Manually select external PHY - MAC mode.
719 * Reverse MII/RMII is for AX88772A PHY mode.
720 */
721 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
722 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
723 uether_pause(&sc->sc_ue, hz / 32);
724 }
725 /* Take PHY out of power down. */
726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
727 AXE_SW_RESET_IPRL, NULL);
728 uether_pause(&sc->sc_ue, hz / 4);
729 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
730 uether_pause(&sc->sc_ue, hz);
731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
732 uether_pause(&sc->sc_ue, hz / 32);
733 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
734 uether_pause(&sc->sc_ue, hz / 32);
735 }
736
737 static void
738 axe_ax88772a_init(struct axe_softc *sc)
739 {
740 struct usb_ether *ue;
741
742 ue = &sc->sc_ue;
743 /* Reload EEPROM. */
744 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
745 axe_ax88772_phywake(sc);
746 /* Stop MAC. */
747 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
748 }
749
750 static void
751 axe_ax88772b_init(struct axe_softc *sc)
752 {
753 struct usb_ether *ue;
754 uint16_t eeprom;
755 uint8_t *eaddr;
756 int i;
757
758 ue = &sc->sc_ue;
759 /* Reload EEPROM. */
760 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
761 /*
762 * Save PHY power saving configuration(high byte) and
763 * clear EEPROM checksum value(low byte).
764 */
765 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
766 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
767
768 /*
769 * Auto-loaded default station address from internal ROM is
770 * 00:00:00:00:00:00 such that an explicit access to EEPROM
771 * is required to get real station address.
772 */
773 eaddr = ue->ue_eaddr;
774 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
775 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
776 &eeprom);
777 eeprom = le16toh(eeprom);
778 *eaddr++ = (uint8_t)(eeprom & 0xFF);
779 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
780 }
781 /* Wakeup PHY. */
782 axe_ax88772_phywake(sc);
783 /* Stop MAC. */
784 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
785 }
786
787 #undef AXE_GPIO_WRITE
788
789 static void
790 axe_reset(struct axe_softc *sc)
791 {
792 struct usb_config_descriptor *cd;
793 usb_error_t err;
794
795 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
796
797 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
798 cd->bConfigurationValue);
799 if (err)
800 DPRINTF("reset failed (ignored)\n");
801
802 /* Wait a little while for the chip to get its brains in order. */
803 uether_pause(&sc->sc_ue, hz / 100);
804
805 /* Reinitialize controller to achieve full reset. */
806 if (sc->sc_flags & AXE_FLAG_178)
807 axe_ax88178_init(sc);
808 else if (sc->sc_flags & AXE_FLAG_772)
809 axe_ax88772_init(sc);
810 else if (sc->sc_flags & AXE_FLAG_772A)
811 axe_ax88772a_init(sc);
812 else if (sc->sc_flags & AXE_FLAG_772B)
813 axe_ax88772b_init(sc);
814 }
815
816 static void
817 axe_attach_post(struct usb_ether *ue)
818 {
819 struct axe_softc *sc = uether_getsc(ue);
820
821 /*
822 * Load PHY indexes first. Needed by axe_xxx_init().
823 */
824 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
825 if (bootverbose)
826 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
827 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
828 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
829 if (sc->sc_phyno == -1)
830 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
831 if (sc->sc_phyno == -1) {
832 device_printf(sc->sc_ue.ue_dev,
833 "no valid PHY address found, assuming PHY address 0\n");
834 sc->sc_phyno = 0;
835 }
836
837 /* Initialize controller and get station address. */
838 if (sc->sc_flags & AXE_FLAG_178) {
839 axe_ax88178_init(sc);
840 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
841 } else if (sc->sc_flags & AXE_FLAG_772) {
842 axe_ax88772_init(sc);
843 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
844 } else if (sc->sc_flags & AXE_FLAG_772A) {
845 axe_ax88772a_init(sc);
846 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
847 } else if (sc->sc_flags & AXE_FLAG_772B) {
848 axe_ax88772b_init(sc);
849 } else
850 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
851
852 /*
853 * Fetch IPG values.
854 */
855 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
856 /* Set IPG values. */
857 sc->sc_ipgs[0] = 0x15;
858 sc->sc_ipgs[1] = 0x16;
859 sc->sc_ipgs[2] = 0x1A;
860 } else
861 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
862 }
863
864 static int
865 axe_attach_post_sub(struct usb_ether *ue)
866 {
867 struct axe_softc *sc;
868 struct ifnet *ifp;
869 u_int adv_pause;
870 int error;
871
872 sc = uether_getsc(ue);
873 ifp = ue->ue_ifp;
874 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
875 ifp->if_start = uether_start;
876 ifp->if_ioctl = axe_ioctl;
877 ifp->if_init = uether_init;
878 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
879 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
880 IFQ_SET_READY(&ifp->if_snd);
881
882 if (AXE_IS_178_FAMILY(sc))
883 ifp->if_capabilities |= IFCAP_VLAN_MTU;
884 if (sc->sc_flags & AXE_FLAG_772B) {
885 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
886 ifp->if_hwassist = AXE_CSUM_FEATURES;
887 /*
888 * Checksum offloading of AX88772B also works with VLAN
889 * tagged frames but there is no way to take advantage
890 * of the feature because vlan(4) assumes
891 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
892 * support checksum offloading with VLAN. VLAN hardware
893 * tagging support of AX88772B is very limited so it's
894 * not possible to announce IFCAP_VLAN_HWTAGGING.
895 */
896 }
897 ifp->if_capenable = ifp->if_capabilities;
898 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
899 adv_pause = MIIF_DOPAUSE;
900 else
901 adv_pause = 0;
902 bus_topo_lock();
903 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
904 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
905 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
906 bus_topo_unlock();
907
908 return (error);
909 }
910
911 /*
912 * Probe for a AX88172 chip.
913 */
914 static int
915 axe_probe(device_t dev)
916 {
917 struct usb_attach_arg *uaa = device_get_ivars(dev);
918
919 if (uaa->usb_mode != USB_MODE_HOST)
920 return (ENXIO);
921 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
922 return (ENXIO);
923 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
924 return (ENXIO);
925
926 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
927 }
928
929 /*
930 * Attach the interface. Allocate softc structures, do ifmedia
931 * setup and ethernet/BPF attach.
932 */
933 static int
934 axe_attach(device_t dev)
935 {
936 struct usb_attach_arg *uaa = device_get_ivars(dev);
937 struct axe_softc *sc = device_get_softc(dev);
938 struct usb_ether *ue = &sc->sc_ue;
939 uint8_t iface_index;
940 int error;
941
942 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
943
944 device_set_usb_desc(dev);
945
946 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
947
948 iface_index = AXE_IFACE_IDX;
949 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
950 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
951 if (error) {
952 device_printf(dev, "allocating USB transfers failed\n");
953 goto detach;
954 }
955
956 ue->ue_sc = sc;
957 ue->ue_dev = dev;
958 ue->ue_udev = uaa->device;
959 ue->ue_mtx = &sc->sc_mtx;
960 ue->ue_methods = &axe_ue_methods;
961
962 error = uether_ifattach(ue);
963 if (error) {
964 device_printf(dev, "could not attach interface\n");
965 goto detach;
966 }
967 return (0); /* success */
968
969 detach:
970 axe_detach(dev);
971 return (ENXIO); /* failure */
972 }
973
974 static int
975 axe_detach(device_t dev)
976 {
977 struct axe_softc *sc = device_get_softc(dev);
978 struct usb_ether *ue = &sc->sc_ue;
979
980 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
981 uether_ifdetach(ue);
982 mtx_destroy(&sc->sc_mtx);
983
984 return (0);
985 }
986
987 #if (AXE_BULK_BUF_SIZE >= 0x10000)
988 #error "Please update axe_bulk_read_callback()!"
989 #endif
990
991 static void
992 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
993 {
994 struct axe_softc *sc = usbd_xfer_softc(xfer);
995 struct usb_ether *ue = &sc->sc_ue;
996 struct usb_page_cache *pc;
997 int actlen;
998
999 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1000
1001 switch (USB_GET_STATE(xfer)) {
1002 case USB_ST_TRANSFERRED:
1003 pc = usbd_xfer_get_frame(xfer, 0);
1004 axe_rx_frame(ue, pc, actlen);
1005
1006 /* FALLTHROUGH */
1007 case USB_ST_SETUP:
1008 tr_setup:
1009 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1010 usbd_transfer_submit(xfer);
1011 uether_rxflush(ue);
1012 return;
1013
1014 default: /* Error */
1015 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1016
1017 if (error != USB_ERR_CANCELLED) {
1018 /* try to clear stall first */
1019 usbd_xfer_set_stall(xfer);
1020 goto tr_setup;
1021 }
1022 return;
1023 }
1024 }
1025
1026 static int
1027 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1028 {
1029 struct axe_softc *sc;
1030 struct axe_sframe_hdr hdr;
1031 struct axe_csum_hdr csum_hdr;
1032 int error, len, pos;
1033
1034 sc = uether_getsc(ue);
1035 pos = 0;
1036 len = 0;
1037 error = 0;
1038 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1039 while (pos < actlen) {
1040 if ((int)(pos + sizeof(hdr)) > actlen) {
1041 /* too little data */
1042 error = EINVAL;
1043 break;
1044 }
1045 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1046
1047 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1048 /* we lost sync */
1049 error = EINVAL;
1050 break;
1051 }
1052 pos += sizeof(hdr);
1053 len = le16toh(hdr.len);
1054 if (pos + len > actlen) {
1055 /* invalid length */
1056 error = EINVAL;
1057 break;
1058 }
1059 axe_rxeof(ue, pc, pos, len, NULL);
1060 pos += len + (len % 2);
1061 }
1062 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1063 while (pos < actlen) {
1064 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1065 /* too little data */
1066 error = EINVAL;
1067 break;
1068 }
1069 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1070
1071 csum_hdr.len = le16toh(csum_hdr.len);
1072 csum_hdr.ilen = le16toh(csum_hdr.ilen);
1073 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1074 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1075 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1076 sc->sc_lenmask) {
1077 /* we lost sync */
1078 error = EINVAL;
1079 break;
1080 }
1081 /*
1082 * Get total transferred frame length including
1083 * checksum header. The length should be multiple
1084 * of 4.
1085 */
1086 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1087 len = (len + 3) & ~3;
1088 if (pos + len > actlen) {
1089 /* invalid length */
1090 error = EINVAL;
1091 break;
1092 }
1093 axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1094 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1095 pos += len;
1096 }
1097 } else
1098 axe_rxeof(ue, pc, 0, actlen, NULL);
1099
1100 if (error != 0)
1101 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
1102 return (error);
1103 }
1104
1105 static int
1106 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned offset,
1107 unsigned len, struct axe_csum_hdr *csum_hdr)
1108 {
1109 struct ifnet *ifp = ue->ue_ifp;
1110 struct mbuf *m;
1111
1112 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1113 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1114 return (EINVAL);
1115 }
1116
1117 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1118 if (m == NULL) {
1119 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1120 return (ENOMEM);
1121 }
1122 m->m_len = m->m_pkthdr.len = MCLBYTES;
1123 m_adj(m, ETHER_ALIGN);
1124
1125 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1126
1127 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1128 m->m_pkthdr.rcvif = ifp;
1129 m->m_pkthdr.len = m->m_len = len;
1130
1131 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1132 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1133 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1134 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1135 CSUM_IP_VALID;
1136 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1137 AXE_CSUM_HDR_L4_TYPE_TCP ||
1138 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1139 AXE_CSUM_HDR_L4_TYPE_UDP) {
1140 m->m_pkthdr.csum_flags |=
1141 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1142 m->m_pkthdr.csum_data = 0xffff;
1143 }
1144 }
1145 }
1146
1147 (void)mbufq_enqueue(&ue->ue_rxq, m);
1148 return (0);
1149 }
1150
1151 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1152 #error "Please update axe_bulk_write_callback()!"
1153 #endif
1154
1155 static void
1156 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1157 {
1158 struct axe_softc *sc = usbd_xfer_softc(xfer);
1159 struct axe_sframe_hdr hdr;
1160 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1161 struct usb_page_cache *pc;
1162 struct mbuf *m;
1163 int nframes, pos;
1164
1165 switch (USB_GET_STATE(xfer)) {
1166 case USB_ST_TRANSFERRED:
1167 DPRINTFN(11, "transfer complete\n");
1168 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1169 /* FALLTHROUGH */
1170 case USB_ST_SETUP:
1171 tr_setup:
1172 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1173 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1174 /*
1175 * Don't send anything if there is no link or
1176 * controller is busy.
1177 */
1178 return;
1179 }
1180
1181 for (nframes = 0; nframes < 16 &&
1182 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1183 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1184 if (m == NULL)
1185 break;
1186 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1187 nframes);
1188 pos = 0;
1189 pc = usbd_xfer_get_frame(xfer, nframes);
1190 if (AXE_IS_178_FAMILY(sc)) {
1191 hdr.len = htole16(m->m_pkthdr.len);
1192 hdr.ilen = ~hdr.len;
1193 /*
1194 * If upper stack computed checksum, driver
1195 * should tell controller not to insert
1196 * computed checksum for checksum offloading
1197 * enabled controller.
1198 */
1199 if (ifp->if_capabilities & IFCAP_TXCSUM) {
1200 if ((m->m_pkthdr.csum_flags &
1201 AXE_CSUM_FEATURES) != 0)
1202 hdr.len |= htole16(
1203 AXE_TX_CSUM_PSEUDO_HDR);
1204 else
1205 hdr.len |= htole16(
1206 AXE_TX_CSUM_DIS);
1207 }
1208 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1209 pos += sizeof(hdr);
1210 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1211 pos += m->m_pkthdr.len;
1212 if ((pos % 512) == 0) {
1213 hdr.len = 0;
1214 hdr.ilen = 0xffff;
1215 usbd_copy_in(pc, pos, &hdr,
1216 sizeof(hdr));
1217 pos += sizeof(hdr);
1218 }
1219 } else {
1220 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1221 pos += m->m_pkthdr.len;
1222 }
1223
1224 /*
1225 * XXX
1226 * Update TX packet counter here. This is not
1227 * correct way but it seems that there is no way
1228 * to know how many packets are sent at the end
1229 * of transfer because controller combines
1230 * multiple writes into single one if there is
1231 * room in TX buffer of controller.
1232 */
1233 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1234
1235 /*
1236 * if there's a BPF listener, bounce a copy
1237 * of this frame to him:
1238 */
1239 BPF_MTAP(ifp, m);
1240
1241 m_freem(m);
1242
1243 /* Set frame length. */
1244 usbd_xfer_set_frame_len(xfer, nframes, pos);
1245 }
1246 if (nframes != 0) {
1247 usbd_xfer_set_frames(xfer, nframes);
1248 usbd_transfer_submit(xfer);
1249 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1250 }
1251 return;
1252 /* NOTREACHED */
1253 default: /* Error */
1254 DPRINTFN(11, "transfer error, %s\n",
1255 usbd_errstr(error));
1256
1257 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1258 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1259
1260 if (error != USB_ERR_CANCELLED) {
1261 /* try to clear stall first */
1262 usbd_xfer_set_stall(xfer);
1263 goto tr_setup;
1264 }
1265 return;
1266 }
1267 }
1268
1269 static void
1270 axe_tick(struct usb_ether *ue)
1271 {
1272 struct axe_softc *sc = uether_getsc(ue);
1273 struct mii_data *mii = GET_MII(sc);
1274
1275 AXE_LOCK_ASSERT(sc, MA_OWNED);
1276
1277 mii_tick(mii);
1278 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1279 axe_miibus_statchg(ue->ue_dev);
1280 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1281 axe_start(ue);
1282 }
1283 }
1284
1285 static void
1286 axe_start(struct usb_ether *ue)
1287 {
1288 struct axe_softc *sc = uether_getsc(ue);
1289
1290 /*
1291 * start the USB transfers, if not already started:
1292 */
1293 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1294 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1295 }
1296
1297 static void
1298 axe_csum_cfg(struct usb_ether *ue)
1299 {
1300 struct axe_softc *sc;
1301 struct ifnet *ifp;
1302 uint16_t csum1, csum2;
1303
1304 sc = uether_getsc(ue);
1305 AXE_LOCK_ASSERT(sc, MA_OWNED);
1306
1307 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1308 ifp = uether_getifp(ue);
1309 csum1 = 0;
1310 csum2 = 0;
1311 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1312 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1313 AXE_TXCSUM_UDP;
1314 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1315 csum1 = 0;
1316 csum2 = 0;
1317 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1318 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1319 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1320 AXE_RXCSUM_IGMP;
1321 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1322 }
1323 }
1324
1325 static void
1326 axe_init(struct usb_ether *ue)
1327 {
1328 struct axe_softc *sc = uether_getsc(ue);
1329 struct ifnet *ifp = uether_getifp(ue);
1330 uint16_t rxmode;
1331
1332 AXE_LOCK_ASSERT(sc, MA_OWNED);
1333
1334 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1335 return;
1336
1337 /* Cancel pending I/O */
1338 axe_stop(ue);
1339
1340 axe_reset(sc);
1341
1342 /* Set MAC address and transmitter IPG values. */
1343 if (AXE_IS_178_FAMILY(sc)) {
1344 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1345 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1346 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1347 } else {
1348 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1349 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1350 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1351 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1352 }
1353
1354 if (AXE_IS_178_FAMILY(sc)) {
1355 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1356 if ((sc->sc_flags & AXE_FLAG_772B) != 0 &&
1357 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1358 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1359 sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1360 } else {
1361 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1362 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1363 }
1364 }
1365
1366 /* Configure TX/RX checksum offloading. */
1367 axe_csum_cfg(ue);
1368
1369 if (sc->sc_flags & AXE_FLAG_772B) {
1370 /* AX88772B uses different maximum frame burst configuration. */
1371 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1372 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1373 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1374 }
1375
1376 /* Enable receiver, set RX mode. */
1377 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1378 if (AXE_IS_178_FAMILY(sc)) {
1379 if (sc->sc_flags & AXE_FLAG_772B) {
1380 /*
1381 * Select RX header format type 1. Aligning IP
1382 * header on 4 byte boundary is not needed when
1383 * checksum offloading feature is not used
1384 * because we always copy the received frame in
1385 * RX handler. When RX checksum offloading is
1386 * active, aligning IP header is required to
1387 * reflect actual frame length including RX
1388 * header size.
1389 */
1390 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1391 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1392 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1393 } else {
1394 /*
1395 * Default Rx buffer size is too small to get
1396 * maximum performance.
1397 */
1398 rxmode |= AXE_178_RXCMD_MFB_16384;
1399 }
1400 } else {
1401 rxmode |= AXE_172_RXCMD_UNICAST;
1402 }
1403
1404 /* If we want promiscuous mode, set the allframes bit. */
1405 if (ifp->if_flags & IFF_PROMISC)
1406 rxmode |= AXE_RXCMD_PROMISC;
1407
1408 if (ifp->if_flags & IFF_BROADCAST)
1409 rxmode |= AXE_RXCMD_BROADCAST;
1410
1411 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1412
1413 /* Load the multicast filter. */
1414 axe_setmulti(ue);
1415
1416 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1417
1418 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1419 /* Switch to selected media. */
1420 axe_ifmedia_upd(ifp);
1421 }
1422
1423 static void
1424 axe_setpromisc(struct usb_ether *ue)
1425 {
1426 struct axe_softc *sc = uether_getsc(ue);
1427 struct ifnet *ifp = uether_getifp(ue);
1428 uint16_t rxmode;
1429
1430 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1431
1432 rxmode = le16toh(rxmode);
1433
1434 if (ifp->if_flags & IFF_PROMISC) {
1435 rxmode |= AXE_RXCMD_PROMISC;
1436 } else {
1437 rxmode &= ~AXE_RXCMD_PROMISC;
1438 }
1439
1440 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1441
1442 axe_setmulti(ue);
1443 }
1444
1445 static void
1446 axe_stop(struct usb_ether *ue)
1447 {
1448 struct axe_softc *sc = uether_getsc(ue);
1449 struct ifnet *ifp = uether_getifp(ue);
1450
1451 AXE_LOCK_ASSERT(sc, MA_OWNED);
1452
1453 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1454 sc->sc_flags &= ~AXE_FLAG_LINK;
1455
1456 /*
1457 * stop all the transfers, if not already stopped:
1458 */
1459 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1460 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1461 }
1462
1463 static int
1464 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1465 {
1466 struct usb_ether *ue = ifp->if_softc;
1467 struct axe_softc *sc;
1468 struct ifreq *ifr;
1469 int error, mask, reinit;
1470
1471 sc = uether_getsc(ue);
1472 ifr = (struct ifreq *)data;
1473 error = 0;
1474 reinit = 0;
1475 if (cmd == SIOCSIFCAP) {
1476 AXE_LOCK(sc);
1477 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1478 if ((mask & IFCAP_TXCSUM) != 0 &&
1479 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1480 ifp->if_capenable ^= IFCAP_TXCSUM;
1481 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1482 ifp->if_hwassist |= AXE_CSUM_FEATURES;
1483 else
1484 ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1485 reinit++;
1486 }
1487 if ((mask & IFCAP_RXCSUM) != 0 &&
1488 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1489 ifp->if_capenable ^= IFCAP_RXCSUM;
1490 reinit++;
1491 }
1492 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
1493 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1494 else
1495 reinit = 0;
1496 AXE_UNLOCK(sc);
1497 if (reinit > 0)
1498 uether_init(ue);
1499 } else
1500 error = uether_ioctl(ifp, cmd, data);
1501
1502 return (error);
1503 }
Cache object: 4d0c37010dfc861503a442ba37f6df4d
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