1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD$
35 */
36
37 /*
38 * Definitions for the ASIX Electronics AX88172, AX88178
39 * and AX88772 to ethernet controllers.
40 */
41
42 /*
43 * Vendor specific commands. ASIX conveniently doesn't document the 'set
44 * NODEID' command in their datasheet (thanks a lot guys).
45 * To make handling these commands easier, I added some extra data which is
46 * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with
47 * the format: LDCC. L and D are both nibbles in the high byte. L represents
48 * the data length (0 to 15) and D represents the direction (0 for vendor read,
49 * 1 for vendor write). CC is the command byte, as specified in the manual.
50 */
51
52 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
53 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
54 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
55
56 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
57 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
58 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
59 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
60 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
61 #define AXE_CMD_MII_OPMODE_SW 0x0106
62 #define AXE_CMD_MII_READ_REG 0x2007
63 #define AXE_CMD_MII_WRITE_REG 0x2108
64 #define AXE_CMD_MII_READ_OPMODE 0x1009
65 #define AXE_CMD_MII_OPMODE_HW 0x010A
66 #define AXE_CMD_SROM_READ 0x200B
67 #define AXE_CMD_SROM_WRITE 0x010C
68 #define AXE_CMD_SROM_WR_ENABLE 0x010D
69 #define AXE_CMD_SROM_WR_DISABLE 0x010E
70 #define AXE_CMD_RXCTL_READ 0x200F
71 #define AXE_CMD_RXCTL_WRITE 0x0110
72 #define AXE_CMD_READ_IPG012 0x3011
73 #define AXE_172_CMD_WRITE_IPG0 0x0112
74 #define AXE_178_CMD_WRITE_IPG012 0x0112
75 #define AXE_172_CMD_WRITE_IPG1 0x0113
76 #define AXE_178_CMD_READ_NODEID 0x6013
77 #define AXE_172_CMD_WRITE_IPG2 0x0114
78 #define AXE_178_CMD_WRITE_NODEID 0x6114
79 #define AXE_CMD_READ_MCAST 0x8015
80 #define AXE_CMD_WRITE_MCAST 0x8116
81 #define AXE_172_CMD_READ_NODEID 0x6017
82 #define AXE_172_CMD_WRITE_NODEID 0x6118
83
84 #define AXE_CMD_READ_PHYID 0x2019
85 #define AXE_172_CMD_READ_MEDIA 0x101A
86 #define AXE_178_CMD_READ_MEDIA 0x201A
87 #define AXE_CMD_WRITE_MEDIA 0x011B
88 #define AXE_CMD_READ_MONITOR_MODE 0x101C
89 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D
90 #define AXE_CMD_READ_GPIO 0x101E
91 #define AXE_CMD_WRITE_GPIO 0x011F
92
93 #define AXE_CMD_SW_RESET_REG 0x0120
94 #define AXE_CMD_SW_PHY_STATUS 0x0021
95 #define AXE_CMD_SW_PHY_SELECT 0x0122
96
97 /* AX88772A and AX88772B only. */
98 #define AXE_CMD_READ_VLAN_CTRL 0x4027
99 #define AXE_CMD_WRITE_VLAN_CTRL 0x4028
100
101 #define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A
102 #define AXE_772B_CMD_READ_RXCSUM 0x002B
103 #define AXE_772B_CMD_WRITE_RXCSUM 0x012C
104 #define AXE_772B_CMD_READ_TXCSUM 0x002D
105 #define AXE_772B_CMD_WRITE_TXCSUM 0x012E
106
107 #define AXE_SW_RESET_CLEAR 0x00
108 #define AXE_SW_RESET_RR 0x01
109 #define AXE_SW_RESET_RT 0x02
110 #define AXE_SW_RESET_PRTE 0x04
111 #define AXE_SW_RESET_PRL 0x08
112 #define AXE_SW_RESET_BZ 0x10
113 #define AXE_SW_RESET_IPRL 0x20
114 #define AXE_SW_RESET_IPPD 0x40
115
116 /* AX88178 documentation says to always write this bit... */
117 #define AXE_178_RESET_MAGIC 0x40
118
119 #define AXE_178_MEDIA_GMII 0x0001
120 #define AXE_MEDIA_FULL_DUPLEX 0x0002
121 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004
122
123 /* AX88178/88772 documentation says to always write 1 to bit 2 */
124 #define AXE_178_MEDIA_MAGIC 0x0004
125 /* AX88772 documentation says to always write 0 to bit 3 */
126 #define AXE_178_MEDIA_ENCK 0x0008
127 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010
128 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010
129 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020
130 #define AXE_178_MEDIA_JUMBO_EN 0x0040
131 #define AXE_178_MEDIA_LTPF_ONLY 0x0080
132 #define AXE_178_MEDIA_RX_EN 0x0100
133 #define AXE_178_MEDIA_100TX 0x0200
134 #define AXE_178_MEDIA_SBP 0x0800
135 #define AXE_178_MEDIA_SUPERMAC 0x1000
136
137 #define AXE_RXCMD_PROMISC 0x0001
138 #define AXE_RXCMD_ALLMULTI 0x0002
139 #define AXE_172_RXCMD_UNICAST 0x0004
140 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004
141 #define AXE_RXCMD_BROADCAST 0x0008
142 #define AXE_RXCMD_MULTICAST 0x0010
143 #define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */
144 #define AXE_RXCMD_ENABLE 0x0080
145 #define AXE_178_RXCMD_MFB_MASK 0x0300
146 #define AXE_178_RXCMD_MFB_2048 0x0000
147 #define AXE_178_RXCMD_MFB_4096 0x0100
148 #define AXE_178_RXCMD_MFB_8192 0x0200
149 #define AXE_178_RXCMD_MFB_16384 0x0300
150 #define AXE_772B_RXCMD_HDR_TYPE_0 0x0000
151 #define AXE_772B_RXCMD_HDR_TYPE_1 0x0100
152 #define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200
153 #define AXE_772B_RXCMD_ADD_CHKSUM 0x0400
154 #define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */
155
156 #define AXE_PHY_SEL_PRI 1
157 #define AXE_PHY_SEL_SEC 0
158 #define AXE_PHY_TYPE_MASK 0xE0
159 #define AXE_PHY_TYPE_SHIFT 5
160 #define AXE_PHY_TYPE(x) \
161 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT)
162
163 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */
164 #define PHY_TYPE_GIG 1 /* Gigabit PHY */
165 #define PHY_TYPE_SPECIAL 4 /* Special case */
166 #define PHY_TYPE_RSVD 5 /* Reserved */
167 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */
168
169 #define AXE_PHY_NO_MASK 0x1F
170 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK)
171
172 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */
173
174 #define AXE_GPIO0_EN 0x01
175 #define AXE_GPIO0 0x02
176 #define AXE_GPIO1_EN 0x04
177 #define AXE_GPIO1 0x08
178 #define AXE_GPIO2_EN 0x10
179 #define AXE_GPIO2 0x20
180 #define AXE_GPIO_RELOAD_EEPROM 0x80
181
182 #define AXE_PHY_MODE_MARVELL 0x00
183 #define AXE_PHY_MODE_CICADA 0x01
184 #define AXE_PHY_MODE_AGERE 0x02
185 #define AXE_PHY_MODE_CICADA_V2 0x05
186 #define AXE_PHY_MODE_AGERE_GMII 0x06
187 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09
188 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C
189 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D
190 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E
191 #define AXE_PHY_MODE_ATTANSIC 0x40
192
193 /* AX88772A/AX88772B only. */
194 #define AXE_SW_PHY_SELECT_EXT 0x0000
195 #define AXE_SW_PHY_SELECT_EMBEDDED 0x0001
196 #define AXE_SW_PHY_SELECT_AUTO 0x0002
197 #define AXE_SW_PHY_SELECT_SS_MII 0x0004
198 #define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008
199 #define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C
200 #define AXE_SW_PHY_SELECT_SS_ENB 0x0010
201
202 /* AX88772A/AX88772B VLAN control. */
203 #define AXE_VLAN_CTRL_ENB 0x00001000
204 #define AXE_VLAN_CTRL_STRIP 0x00002000
205 #define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF
206 #define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000
207
208 #define AXE_RXCSUM_IP 0x0001
209 #define AXE_RXCSUM_IPVE 0x0002
210 #define AXE_RXCSUM_IPV6E 0x0004
211 #define AXE_RXCSUM_TCP 0x0008
212 #define AXE_RXCSUM_UDP 0x0010
213 #define AXE_RXCSUM_ICMP 0x0020
214 #define AXE_RXCSUM_IGMP 0x0040
215 #define AXE_RXCSUM_ICMP6 0x0080
216 #define AXE_RXCSUM_TCPV6 0x0100
217 #define AXE_RXCSUM_UDPV6 0x0200
218 #define AXE_RXCSUM_ICMPV6 0x0400
219 #define AXE_RXCSUM_IGMPV6 0x0800
220 #define AXE_RXCSUM_ICMP6V6 0x1000
221 #define AXE_RXCSUM_FOPC 0x8000
222
223 #define AXE_RXCSUM_64TE 0x0100
224 #define AXE_RXCSUM_PPPOE 0x0200
225 #define AXE_RXCSUM_RPCE 0x8000
226
227 #define AXE_TXCSUM_IP 0x0001
228 #define AXE_TXCSUM_TCP 0x0002
229 #define AXE_TXCSUM_UDP 0x0004
230 #define AXE_TXCSUM_ICMP 0x0008
231 #define AXE_TXCSUM_IGMP 0x0010
232 #define AXE_TXCSUM_ICMP6 0x0020
233 #define AXE_TXCSUM_TCPV6 0x0100
234 #define AXE_TXCSUM_UDPV6 0x0200
235 #define AXE_TXCSUM_ICMPV6 0x0400
236 #define AXE_TXCSUM_IGMPV6 0x0800
237 #define AXE_TXCSUM_ICMP6V6 0x1000
238
239 #define AXE_TXCSUM_64TE 0x0001
240 #define AXE_TXCSUM_PPPOE 0x0002
241
242 #define AXE_BULK_BUF_SIZE 16384 /* bytes */
243
244 #define AXE_CTL_READ 0x01
245 #define AXE_CTL_WRITE 0x02
246
247 #define AXE_CONFIG_IDX 0 /* config number 1 */
248 #define AXE_IFACE_IDX 0
249
250 /* EEPROM Map. */
251 #define AXE_EEPROM_772B_NODE_ID 0x04
252 #define AXE_EEPROM_772B_PHY_PWRCFG 0x18
253
254 struct ax88772b_mfb {
255 int byte_cnt;
256 int threshold;
257 int size;
258 };
259 #define AX88772B_MFB_2K 0
260 #define AX88772B_MFB_4K 1
261 #define AX88772B_MFB_6K 2
262 #define AX88772B_MFB_8K 3
263 #define AX88772B_MFB_16K 4
264 #define AX88772B_MFB_20K 5
265 #define AX88772B_MFB_24K 6
266 #define AX88772B_MFB_32K 7
267
268 struct axe_sframe_hdr {
269 uint16_t len;
270 #define AXE_HDR_LEN_MASK 0xFFFF
271 uint16_t ilen;
272 } __packed;
273
274 #define AXE_TX_CSUM_PSEUDO_HDR 0x4000
275 #define AXE_TX_CSUM_DIS 0x8000
276
277 /*
278 * When RX checksum offloading is enabled, AX88772B uses new RX header
279 * format and it's not compatible with previous RX header format. In
280 * addition, IP header align option should be enabled to get correct
281 * frame size including RX header. Total transferred size including
282 * the RX header is multiple of 4 and controller will pad necessary
283 * bytes if the length is not multiple of 4.
284 * This driver does not enable partial checksum feature which will
285 * compute 16bit checksum from 14th byte to the end of the frame. If
286 * this feature is enabled, computed checksum value is embedded into
287 * RX header which in turn means it uses different RX header format.
288 */
289 struct axe_csum_hdr {
290 uint16_t len;
291 #define AXE_CSUM_HDR_LEN_MASK 0x07FF
292 #define AXE_CSUM_HDR_CRC_ERR 0x1000
293 #define AXE_CSUM_HDR_MII_ERR 0x2000
294 #define AXE_CSUM_HDR_RUNT 0x4000
295 #define AXE_CSUM_HDR_BMCAST 0x8000
296 uint16_t ilen;
297 uint16_t cstatus;
298 #define AXE_CSUM_HDR_VLAN_MASK 0x0007
299 #define AXE_CSUM_HDR_VLAN_STRIP 0x0008
300 #define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070
301 #define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100
302 #define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200
303 #define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400
304 #define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800
305 #define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00
306 #define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000
307 #define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400
308 #define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00
309 #define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000
310 #define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000
311
312 #ifdef AXE_APPEND_PARTIAL_CSUM
313 /*
314 * These members present only when partial checksum
315 * offloading is enabled. The checksum value is simple
316 * 16bit sum of received frame starting at offset 14 of
317 * the frame to the end of the frame excluding FCS bytes.
318 */
319 uint16_t csum_value;
320 uint16_t dummy;
321 #endif
322 } __packed;
323
324 #define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK)
325
326 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
327
328 /* The interrupt endpoint is currently unused by the ASIX part. */
329 enum {
330 AXE_BULK_DT_WR,
331 AXE_BULK_DT_RD,
332 AXE_N_TRANSFER,
333 };
334
335 struct axe_softc {
336 struct usb_ether sc_ue;
337 struct mtx sc_mtx;
338 struct usb_xfer *sc_xfer[AXE_N_TRANSFER];
339 int sc_phyno;
340
341 int sc_flags;
342 #define AXE_FLAG_LINK 0x0001
343 #define AXE_FLAG_STD_FRAME 0x0010
344 #define AXE_FLAG_CSUM_FRAME 0x0020
345 #define AXE_FLAG_772 0x1000 /* AX88772 */
346 #define AXE_FLAG_772A 0x2000 /* AX88772A */
347 #define AXE_FLAG_772B 0x4000 /* AX88772B */
348 #define AXE_FLAG_178 0x8000 /* AX88178 */
349
350 uint8_t sc_ipgs[3];
351 uint8_t sc_phyaddrs[2];
352 uint16_t sc_pwrcfg;
353 uint16_t sc_lenmask;
354 };
355
356 #define AXE_IS_178_FAMILY(sc) \
357 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \
358 AXE_FLAG_178))
359
360 #define AXE_IS_772(sc) \
361 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B))
362
363 #define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
364 #define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
365 #define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
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