1 /* $NetBSD$ */
2 /* $FreeBSD: src/sys/dev/usb/sl811hsreg.h,v 1.1 2005/07/14 15:57:00 takawata Exp $ */
3
4
5 /*
6 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Tetsuya Isaki.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 /*
42 * ScanLogic SL811HS/T USB Host Controller
43 */
44
45 #define SL11_IDX_ADDR (0x00)
46 #define SL11_IDX_DATA (0x01)
47 #define SL11_PORTSIZE (0x02)
48
49 #define SL11_E0BASE (0x00) /* Base of Control0 */
50 #define SL11_E0CTRL (0x00) /* Host Control Register */
51 #define SL11_E0ADDR (0x01) /* Host Base Address */
52 #define SL11_E0LEN (0x02) /* Host Base Length */
53 #define SL11_E0STAT (0x03) /* USB Status (Read) */
54 #define SL11_E0PID SL11_E0STAT /* Host PID, Device Endpoint (Write) */
55 #define SL11_E0CONT (0x04) /* Transfer Count (Read) */
56 #define SL11_E0DEV SL11_E0CONT /* Host Device Address (Write) */
57
58 #define SL11_E1BASE (0x08) /* Base of Control1 */
59 #define SL11_E1CTRL (SL11_E1BASE + SL11_E0CTRL)
60 #define SL11_E1ADDR (SL11_E1BASE + SL11_E0ADDR)
61 #define SL11_E1LEN (SL11_E1BASE + SL11_E0LEN)
62 #define SL11_E1STAT (SL11_E1BASE + SL11_E0STAT)
63 #define SL11_E1PID (SL11_E1BASE + SL11_E0PID)
64 #define SL11_E1CONT (SL11_E1BASE + SL11_E0CONT)
65 #define SL11_E1DEV (SL11_E1BASE + SL11_E0DEV)
66
67 #define SL11_CTRL (0x05) /* Control Register1 */
68 #define SL11_IER (0x06) /* Interrupt Enable Register */
69 #define SL11_ISR (0x0d) /* Interrupt Status Register */
70 #define SL11_DATA (0x0e) /* SOF Counter Low (Write) */
71 #define SL11_REV SL11_DATA /* HW Revision Register (Read) */
72 #define SL811_CSOF (0x0f) /* SOF Counter High(R), Control2(W) */
73 #define SL11_MEM (0x10) /* Memory Buffer (0x10 - 0xff) */
74
75 #define SL11_EPCTRL_ARM (0x01)
76 #define SL11_EPCTRL_ENABLE (0x02)
77 #define SL11_EPCTRL_DIRECTION (0x04)
78 #define SL11_EPCTRL_ISO (0x10)
79 #define SL11_EPCTRL_SOF (0x20)
80 #define SL11_EPCTRL_DATATOGGLE (0x40)
81 #define SL11_EPCTRL_PREAMBLE (0x80)
82
83 #define SL11_EPPID_PIDMASK (0xf0)
84 #define SL11_EPPID_EPMASK (0x0f)
85
86 #define SL11_EPSTAT_ACK (0x01)
87 #define SL11_EPSTAT_ERROR (0x02)
88 #define SL11_EPSTAT_TIMEOUT (0x04)
89 #define SL11_EPSTAT_SEQUENCE (0x08)
90 #define SL11_EPSTAT_SETUP (0x10)
91 #define SL11_EPSTAT_OVERFLOW (0x20)
92 #define SL11_EPSTAT_NAK (0x40)
93 #define SL11_EPSTAT_STALL (0x80)
94
95 #define SL11_CTRL_ENABLESOF (0x01)
96 #define SL11_CTRL_EOF2 (0x04)
97 #define SL11_CTRL_RESETENGINE (0x08)
98 #define SL11_CTRL_JKSTATE (0x10)
99 #define SL11_CTRL_LOWSPEED (0x20)
100 #define SL11_CTRL_SUSPEND (0x40)
101
102 #define SL11_IER_USBA (0x01) /* USB-A done */
103 #define SL11_IER_USBB (0x02) /* USB-B done */
104 #define SL11_IER_BABBLE (0x04) /* Babble detection */
105 #define SL11_IER_SOFTIMER (0x10) /* 1ms SOF timer */
106 #define SL11_IER_INSERT (0x20) /* Slave Insert/Remove detection */
107 #define SL11_IER_RESET (0x40) /* USB Reset/Resume */
108
109 #define SL11_ISR_USBA (0x01) /* USB-A done */
110 #define SL11_ISR_USBB (0x02) /* USB-B done */
111 #define SL11_ISR_BABBLE (0x04) /* Babble detection */
112 #define SL11_ISR_SOFTIMER (0x10) /* 1ms SOF timer */
113 #define SL11_ISR_INSERT (0x20) /* Slave Insert/Remove detection */
114 #define SL11_ISR_RESET (0x40) /* USB Reset/Resume */
115 #define SL11_ISR_DATA (0x80) /* Value of the Data+ pin */
116
117 #define SL11_REV_USBA (0x01) /* USB-A */
118 #define SL11_REV_USBB (0x02) /* USB-B */
119 #define SL11_REV_REVMASK (0xf0) /* HW Revision */
120 #define SL11_REV_REVSL11H (0x00) /* HW is SL11H */
121 #define SL11_REV_REVSL811HS (0x10) /* HW is SL811HS */
122
123 #define SL811_CSOF_SOFMASK (0x3f) /* SOF High Counter */
124 #define SL811_CSOF_POLARITY (0x40) /* Change polarity */
125 #define SL811_CSOF_MASTER (0x80) /* Master/Slave selection */
126
127
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