The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/umct.h

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    1 /*      $NetBSD: umct.h,v 1.1 2001/03/28 18:42:13 ichiro Exp $  */
    2 /*
    3  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    4  * All rights reserved.
    5  *
    6  * This code is derived from software contributed to The NetBSD Foundation
    7  * by Ichiro FUKUHARA (ichiro@ichiro.org).
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *        This product includes software developed by the NetBSD
   20  *        Foundation, Inc. and its contributors.
   21  * 4. Neither the name of The NetBSD Foundation nor the names of its
   22  *    contributors may be used to endorse or promote products derived
   23  *    from this software without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   26  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  */
   37 
   38 /*
   39  * Vendor Request Interface
   40  */
   41 #define UMCT_SET_REQUEST        0x40
   42 #define UMCT_GET_REQUEST        0xc0
   43 
   44 #define REQ_SET_BAUD_RATE       5       /* Set Baud Rate Divisor */
   45 #define LENGTH_BAUD_RATE        4
   46 
   47 #define REQ_GET_MSR             2       /* Get Modem Status Register (MSR) */
   48 #define LENGTH_GET_MSR          1
   49 
   50 #define REQ_GET_LCR             6       /* Get Line Control Register (LCR) */
   51 #define LENGTH_GET_LCR          1
   52 
   53 #define REQ_SET_LCR             7       /* Set Line Control Register (LCR) */
   54 #define LENGTH_SET_LCR          1
   55 
   56 #define REQ_SET_MCR             10      /* Set Modem Control Register (MCR) */
   57 #define LENGTH_SET_MCR          1
   58 
   59 /*
   60  * Baud rate (divisor)
   61  */
   62 #define UMCT_BAUD_RATE(b)       (115200/b)
   63 
   64 /*
   65  * Line Control Register (LCR)
   66  */
   67 #define LCR_SET_BREAK           0x40
   68 #define LCR_PARITY_EVEN         0x18
   69 #define LCR_PARITY_ODD          0x08
   70 #define LCR_PARITY_NONE         0x00
   71 #define LCR_DATA_BITS_5         0x00
   72 #define LCR_DATA_BITS_6         0x01
   73 #define LCR_DATA_BITS_7         0x02
   74 #define LCR_DATA_BITS_8         0x03
   75 #define LCR_STOP_BITS_2         0x04
   76 #define LCR_STOP_BITS_1         0x00
   77 
   78 /*
   79  * Modem Control Register (MCR)
   80  */
   81 #define MCR_NONE                0x8
   82 #define MCR_RTS                 0xa
   83 #define MCR_DTR                 0x9
   84 
   85 /*
   86  * Modem Status Register (MSR)
   87  */
   88 #define MSR_CD                  0x80    /* Current CD */
   89 #define MSR_RI                  0x40    /* Current RI */
   90 #define MSR_DSR                 0x20    /* Current DSR */
   91 #define MSR_CTS                 0x10    /* Current CTS */
   92 #define MSR_DCD                 0x08    /* Delta CD */
   93 #define MSR_DRI                 0x04    /* Delta RI */
   94 #define MSR_DDSR                0x02    /* Delta DSR */
   95 #define MSR_DCTS                0x01    /* Delta CTS */
   96 
   97 /*
   98  * Line Status Register (LSR)
   99  */
  100 #define LSR_ERR                 0x80    /* OE | PE | FE | BI */
  101 #define LSR_TEMT                0x40    /* transmit register empty */
  102 #define LSR_THRE                0x20    /* transmit holding register empty */
  103 #define LSR_BI                  0x10    /* break indicator */
  104 #define LSR_FE                  0x08    /* framing error */
  105 #define LSR_OE                  0x02    /* overrun error */
  106 #define LSR_PE                  0x04    /* parity error */
  107 #define LSR_OE                  0x02    /* overrun error */
  108 #define LSR_DR                  0x01    /* receive data ready */

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