Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/wlan/if_rsureg.h
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1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 17 * $FreeBSD$ 18 */ 19 20 /* USB Requests. */ 21 #define R92S_REQ_REGS 0x05 22 23 /* 24 * MAC registers. 25 */ 26 #define R92S_SYSCFG 0x0000 27 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 28 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 29 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 30 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 31 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 32 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 33 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 34 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 35 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 36 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 37 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 38 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 39 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 40 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 41 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 42 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 43 44 #define R92S_CMDCTRL 0x0040 45 #define R92S_CR (R92S_CMDCTRL + 0x000) 46 #define R92S_TXPAUSE (R92S_CMDCTRL + 0x002) 47 #define R92S_TCR (R92S_CMDCTRL + 0x004) 48 #define R92S_RCR (R92S_CMDCTRL + 0x008) 49 50 #define R92S_MACIDSETTING 0x0050 51 #define R92S_MACID (R92S_MACIDSETTING + 0x000) 52 #define R92S_MAR (R92S_MACIDSETTING + 0x010) 53 54 #define R92S_TIMECTRL 0x0080 55 #define R92S_TSFTR (R92S_TIMECTRL + 0x000) 56 57 #define R92S_FIFOCTRL 0x00a0 58 #define R92S_RXFLTMAP_MGT (R92S_FIFOCTRL + 0x076) 59 #define R92S_RXFLTMAP_CTL (R92S_FIFOCTRL + 0x078) 60 #define R92S_RXFLTMAP_DATA (R92S_FIFOCTRL + 0x07a) 61 #define R92S_RXFLTMAP_MESH (R92S_FIFOCTRL + 0x07c) 62 63 #define R92S_SECURITY 0x0240 64 #define R92S_CAMCMD (R92S_SECURITY + 0x000) 65 #define R92S_CAMWRITE (R92S_SECURITY + 0x004) 66 #define R92S_CAMREAD (R92S_SECURITY + 0x008) 67 68 #define R92S_GP 0x02e0 69 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) 70 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 71 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 72 #define R92S_LEDCFG (R92S_GP + 0x012) 73 74 #define R92S_IOCMD_CTRL 0x0370 75 #define R92S_IOCMD_DATA 0x0374 76 77 #define R92S_USB_HRPWM 0xfe58 78 79 /* Bits for R92S_SYS_FUNC_EN. */ 80 #define R92S_FEN_CPUEN 0x0400 81 82 /* Bits for R92S_PMC_FSM. */ 83 #define R92S_PMC_FSM_CUT_M 0x000f8000 84 #define R92S_PMC_FSM_CUT_S 15 85 86 /* Bits for R92S_SYS_CLKR. */ 87 #define R92S_SYS_CLKSEL 0x0001 88 #define R92S_SYS_PS_CLKSEL 0x0002 89 #define R92S_SYS_CPU_CLKSEL 0x0004 90 #define R92S_MAC_CLK_EN 0x0800 91 #define R92S_SYS_CLK_EN 0x1000 92 #define R92S_SWHW_SEL 0x4000 93 #define R92S_FWHW_SEL 0x8000 94 95 /* Bits for R92S_EE_9346CR. */ 96 #define R92S_9356SEL 0x10 97 #define R92S_EEPROM_EN 0x20 98 99 /* Bits for R92S_AFE_MISC. */ 100 #define R92S_AFE_MISC_BGEN 0x01 101 #define R92S_AFE_MISC_MBEN 0x02 102 #define R92S_AFE_MISC_I32_EN 0x08 103 104 /* Bits for R92S_SPS1_CTRL. */ 105 #define R92S_SPS1_LDEN 0x01 106 #define R92S_SPS1_SWEN 0x02 107 108 /* Bits for R92S_LDOA15_CTRL. */ 109 #define R92S_LDA15_EN 0x01 110 111 /* Bits for R92S_LDOV12D_CTRL. */ 112 #define R92S_LDV12_EN 0x01 113 114 /* Bits for R92C_EFUSE_CTRL. */ 115 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff 116 #define R92S_EFUSE_CTRL_DATA_S 0 117 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 118 #define R92S_EFUSE_CTRL_ADDR_S 8 119 #define R92S_EFUSE_CTRL_VALID 0x80000000 120 121 /* Bits for R92S_CR. */ 122 #define R92S_CR_TXDMA_EN 0x10 123 124 /* Bits for R92S_TXPAUSE. */ 125 #define R92S_TXPAUSE_VO 0x01 126 #define R92S_TXPAUSE_VI 0x02 127 #define R92S_TXPAUSE_BE 0x04 128 #define R92S_TXPAUSE_BK 0x08 129 #define R92S_TXPAUSE_MGT 0x10 130 #define R92S_TXPAUSE_HIGH 0x20 131 #define R92S_TXPAUSE_HCCA 0x40 132 133 /* Shortcuts. */ 134 #define R92S_TXPAUSE_AC \ 135 (R92S_TXPAUSE_VO | R92S_TXPAUSE_VI | \ 136 R92S_TXPAUSE_BE | R92S_TXPAUSE_BK) 137 138 #define R92S_TXPAUSE_ALL \ 139 (R92S_TXPAUSE_AC | R92S_TXPAUSE_MGT | \ 140 R92S_TXPAUSE_HIGH | R92S_TXPAUSE_HCCA | 0x80) 141 142 /* Bits for R92S_TCR. */ 143 #define R92S_TCR_IMEM_CODE_DONE 0x01 144 #define R92S_TCR_IMEM_CHK_RPT 0x02 145 #define R92S_TCR_EMEM_CODE_DONE 0x04 146 #define R92S_TCR_EMEM_CHK_RPT 0x08 147 #define R92S_TCR_DMEM_CODE_DONE 0x10 148 #define R92S_TCR_IMEM_RDY 0x20 149 #define R92S_TCR_FWRDY 0x80 150 151 /* Bits for R92S_RCR. */ 152 #define R92S_RCR_AAP 0x00000001 153 #define R92S_RCR_APM 0x00000002 154 #define R92S_RCR_AM 0x00000004 155 #define R92S_RCR_AB 0x00000008 156 #define R92S_RCR_ACRC32 0x00000020 157 #define R92S_RCR_AICV 0x00001000 158 #define R92S_RCR_APP_ICV 0x00010000 159 #define R92S_RCR_APP_MIC 0x00020000 160 #define R92S_RCR_ADF 0x00040000 161 #define R92S_RCR_ACF 0x00080000 162 #define R92S_RCR_AMF 0x00100000 163 #define R92S_RCR_ADD3 0x00200000 164 #define R92S_RCR_APWRMGT 0x00400000 165 #define R92S_RCR_CBSSID 0x00800000 166 #define R92S_RCR_APP_PHYSTS 0x02000000 167 #define R92S_RCR_TCP_OFFLD_EN 0x04000000 168 #define R92S_RCR_ENMBID 0x08000000 169 170 /* Bits for R92S_RXFLTMAP*. */ 171 #define R92S_RXFLTMAP_MGT_DEF 0x3f3f 172 #define R92S_RXFLTMAP_FW(subtype) \ 173 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 174 175 /* Bits for R92S_GPIO_IO_SEL. */ 176 #define R92S_GPIO_WPS 0x10 177 178 /* Bits for R92S_MAC_PINMUX_CTRL. */ 179 #define R92S_GPIOSEL_GPIO_M 0x03 180 #define R92S_GPIOSEL_GPIO_S 0 181 #define R92S_GPIOSEL_GPIO_JTAG 0 182 #define R92S_GPIOSEL_GPIO_PHYDBG 1 183 #define R92S_GPIOSEL_GPIO_BT 2 184 #define R92S_GPIOSEL_GPIO_WLANDBG 3 185 #define R92S_GPIOMUX_EN 0x08 186 187 /* Bits for R92S_CAMCMD. */ 188 #define R92S_CAMCMD_ADDR_M 0x000000ff 189 #define R92S_CAMCMD_ADDR_S 0 190 #define R92S_CAMCMD_READ 0x00000000 191 #define R92S_CAMCMD_WRITE 0x00010000 192 #define R92S_CAMCMD_POLLING 0x80000000 193 194 /* 195 * CAM entries. 196 */ 197 #define R92S_CAM_ENTRY_LIMIT 32 198 #define R92S_CAM_ENTRY_BYTES howmany(R92S_CAM_ENTRY_LIMIT, NBBY) 199 200 #define R92S_CAM_CTL0(entry) ((entry) * 8 + 0) 201 #define R92S_CAM_CTL1(entry) ((entry) * 8 + 1) 202 #define R92S_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 203 204 /* Bits for R92S_CAM_CTL0(i). */ 205 #define R92S_CAM_KEYID_M 0x00000003 206 #define R92S_CAM_KEYID_S 0 207 #define R92S_CAM_ALGO_M 0x0000001c 208 #define R92S_CAM_ALGO_S 2 209 #define R92S_CAM_VALID 0x00008000 210 #define R92S_CAM_MACLO_M 0xffff0000 211 #define R92S_CAM_MACLO_S 16 212 213 /* Bits for R92S_IOCMD_CTRL. */ 214 #define R92S_IOCMD_CLASS_M 0xff000000 215 #define R92S_IOCMD_CLASS_S 24 216 #define R92S_IOCMD_CLASS_BB_RF 0xf0 217 #define R92S_IOCMD_VALUE_M 0x00ffff00 218 #define R92S_IOCMD_VALUE_S 8 219 #define R92S_IOCMD_INDEX_M 0x000000ff 220 #define R92S_IOCMD_INDEX_S 0 221 #define R92S_IOCMD_INDEX_BB_READ 0 222 #define R92S_IOCMD_INDEX_BB_WRITE 1 223 #define R92S_IOCMD_INDEX_RF_READ 2 224 #define R92S_IOCMD_INDEX_RF_WRITE 3 225 226 /* Bits for R92S_USB_HRPWM. */ 227 #define R92S_USB_HRPWM_PS_ALL_ON 0x04 228 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 229 230 /* 231 * Macros to access subfields in registers. 232 */ 233 /* Mask and Shift (getter). */ 234 #define MS(val, field) \ 235 (((val) & field##_M) >> field##_S) 236 237 /* Shift and Mask (setter). */ 238 #define SM(field, val) \ 239 (((val) << field##_S) & field##_M) 240 241 /* Rewrite. */ 242 #define RW(var, field, val) \ 243 (((var) & ~field##_M) | SM(field, val)) 244 245 /* 246 * ROM field with RF config. 247 */ 248 enum { 249 RTL8712_RFCONFIG_1T = 0x10, 250 RTL8712_RFCONFIG_2T = 0x20, 251 RTL8712_RFCONFIG_1R = 0x01, 252 RTL8712_RFCONFIG_2R = 0x02, 253 RTL8712_RFCONFIG_1T1R = 0x11, 254 RTL8712_RFCONFIG_1T2R = 0x12, 255 RTL8712_RFCONFIG_TURBO = 0x92, 256 RTL8712_RFCONFIG_2T2R = 0x22 257 }; 258 259 /* 260 * Firmware image header. 261 */ 262 struct r92s_fw_priv { 263 /* QWORD0 */ 264 uint16_t signature; 265 uint8_t hci_sel; 266 #define R92S_HCI_SEL_PCIE 0x01 267 #define R92S_HCI_SEL_USB 0x02 268 #define R92S_HCI_SEL_SDIO 0x04 269 #define R92S_HCI_SEL_8172 0x10 270 #define R92S_HCI_SEL_AP 0x80 271 272 uint8_t chip_version; 273 uint16_t custid; 274 uint8_t rf_config; 275 //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R 276 uint8_t nendpoints; 277 /* QWORD1 */ 278 uint32_t regulatory; 279 uint8_t rfintfs; 280 uint8_t def_nettype; 281 uint8_t turbo_mode; 282 uint8_t lowpower_mode; 283 /* QWORD2 */ 284 uint8_t lbk_mode; 285 uint8_t mp_mode; 286 uint8_t vcs_type; 287 #define R92S_VCS_TYPE_DISABLE 0 288 #define R92S_VCS_TYPE_ENABLE 1 289 #define R92S_VCS_TYPE_AUTO 2 290 291 uint8_t vcs_mode; 292 #define R92S_VCS_MODE_NONE 0 293 #define R92S_VCS_MODE_RTS_CTS 1 294 #define R92S_VCS_MODE_CTS2SELF 2 295 296 uint32_t reserved1; 297 /* QWORD3 */ 298 uint8_t qos_en; 299 uint8_t bw40_en; 300 uint8_t amsdu2ampdu_en; 301 uint8_t ampdu_en; 302 uint8_t rc_offload; 303 uint8_t agg_offload; 304 uint16_t reserved2; 305 /* QWORD4 */ 306 uint8_t beacon_offload; 307 uint8_t mlme_offload; 308 uint8_t hwpc_offload; 309 uint8_t tcpcsum_offload; 310 uint8_t tcp_offload; 311 uint8_t ps_offload; 312 uint8_t wwlan_offload; 313 uint8_t reserved3; 314 /* QWORD5 */ 315 uint16_t tcp_tx_len; 316 uint16_t tcp_rx_len; 317 uint32_t reserved4; 318 } __packed; 319 320 struct r92s_fw_hdr { 321 uint16_t signature; 322 uint16_t version; 323 uint32_t dmemsz; 324 uint32_t imemsz; 325 uint32_t sramsz; 326 uint32_t privsz; 327 uint16_t efuse_addr; 328 uint16_t h2c_resp_addr; 329 uint32_t svnrev; 330 uint8_t month; 331 uint8_t day; 332 uint8_t hour; 333 uint8_t minute; 334 struct r92s_fw_priv priv; 335 } __packed; 336 337 /* Structure for FW commands and FW events notifications. */ 338 struct r92s_fw_cmd_hdr { 339 uint16_t len; 340 uint8_t code; 341 uint8_t seq; 342 #define R92S_FW_CMD_MORE 0x80 343 344 uint32_t reserved; 345 } __packed; 346 347 /* FW commands codes. */ 348 #define R92S_CMD_READ_MACREG 0 349 #define R92S_CMD_WRITE_MACREG 1 350 #define R92S_CMD_READ_BBREG 2 351 #define R92S_CMD_WRITE_BBREG 3 352 #define R92S_CMD_READ_RFREG 4 353 #define R92S_CMD_WRITE_RFREG 5 354 #define R92S_CMD_READ_EEPROM 6 355 #define R92S_CMD_WRITE_EEPROM 7 356 #define R92S_CMD_READ_EFUSE 8 357 #define R92S_CMD_WRITE_EFUSE 9 358 #define R92S_CMD_READ_CAM 10 359 #define R92S_CMD_WRITE_CAM 11 360 #define R92S_CMD_SET_BCNITV 12 361 #define R92S_CMD_SET_MBIDCFG 13 362 #define R92S_CMD_JOIN_BSS 14 363 #define R92S_CMD_DISCONNECT 15 364 #define R92S_CMD_CREATE_BSS 16 365 #define R92S_CMD_SET_OPMODE 17 366 #define R92S_CMD_SITE_SURVEY 18 367 #define R92S_CMD_SET_AUTH 19 368 #define R92S_CMD_SET_KEY 20 369 #define R92S_CMD_SET_STA_KEY 21 370 #define R92S_CMD_SET_ASSOC_STA 22 371 #define R92S_CMD_DEL_ASSOC_STA 23 372 #define R92S_CMD_SET_STAPWRSTATE 24 373 #define R92S_CMD_SET_BASIC_RATE 25 374 #define R92S_CMD_GET_BASIC_RATE 26 375 #define R92S_CMD_SET_DATA_RATE 27 376 #define R92S_CMD_GET_DATA_RATE 28 377 #define R92S_CMD_SET_PHY_INFO 29 378 #define R92S_CMD_GET_PHY_INFO 30 379 #define R92S_CMD_SET_PHY 31 380 #define R92S_CMD_GET_PHY 32 381 #define R92S_CMD_READ_RSSI 33 382 #define R92S_CMD_READ_GAIN 34 383 #define R92S_CMD_SET_ATIM 35 384 #define R92S_CMD_SET_PWR_MODE 36 385 #define R92S_CMD_JOIN_BSS_RPT 37 386 #define R92S_CMD_SET_RA_TABLE 38 387 #define R92S_CMD_GET_RA_TABLE 39 388 #define R92S_CMD_GET_CCX_REPORT 40 389 #define R92S_CMD_GET_DTM_REPORT 41 390 #define R92S_CMD_GET_TXRATE_STATS 42 391 #define R92S_CMD_SET_USB_SUSPEND 43 392 #define R92S_CMD_SET_H2C_LBK 44 393 #define R92S_CMD_ADDBA_REQ 45 394 #define R92S_CMD_SET_CHANNEL 46 395 #define R92S_CMD_SET_TXPOWER 47 396 #define R92S_CMD_SWITCH_ANTENNA 48 397 #define R92S_CMD_SET_CRYSTAL_CAL 49 398 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 399 #define R92S_CMD_SET_SINGLE_TONE_TX 51 400 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 401 #define R92S_CMD_SET_CONTINUOUS_TX 53 402 #define R92S_CMD_SWITCH_BANDWIDTH 54 403 #define R92S_CMD_TX_BEACON 55 404 #define R92S_CMD_SET_POWER_TRACKING 56 405 #define R92S_CMD_AMSDU_TO_AMPDU 57 406 #define R92S_CMD_SET_MAC_ADDRESS 58 407 #define R92S_CMD_GET_H2C_LBK 59 408 #define R92S_CMD_SET_PBREQ_IE 60 409 #define R92S_CMD_SET_ASSOCREQ_IE 61 410 #define R92S_CMD_SET_PBRESP_IE 62 411 #define R92S_CMD_SET_ASSOCRESP_IE 63 412 #define R92S_CMD_GET_CURDATARATE 64 413 #define R92S_CMD_GET_TXRETRY_CNT 65 414 #define R92S_CMD_GET_RXRETRY_CNT 66 415 #define R92S_CMD_GET_BCNOK_CNT 67 416 #define R92S_CMD_GET_BCNERR_CNT 68 417 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 418 #define R92S_CMD_SET_DIG 70 419 #define R92S_CMD_SET_RA 71 420 #define R92S_CMD_SET_PT 72 421 #define R92S_CMD_READ_TSSI 73 422 423 /* FW events notifications codes. */ 424 #define R92S_EVT_READ_MACREG 0 425 #define R92S_EVT_READ_BBREG 1 426 #define R92S_EVT_READ_RFREG 2 427 #define R92S_EVT_READ_EEPROM 3 428 #define R92S_EVT_READ_EFUSE 4 429 #define R92S_EVT_READ_CAM 5 430 #define R92S_EVT_GET_BASICRATE 6 431 #define R92S_EVT_GET_DATARATE 7 432 #define R92S_EVT_SURVEY 8 433 #define R92S_EVT_SURVEY_DONE 9 434 #define R92S_EVT_JOIN_BSS 10 435 #define R92S_EVT_ADD_STA 11 436 #define R92S_EVT_DEL_STA 12 437 #define R92S_EVT_ATIM_DONE 13 438 #define R92S_EVT_TX_REPORT 14 439 #define R92S_EVT_CCX_REPORT 15 440 #define R92S_EVT_DTM_REPORT 16 441 #define R92S_EVT_TXRATE_STATS 17 442 #define R92S_EVT_C2H_LBK 18 443 #define R92S_EVT_FWDBG 19 444 #define R92S_EVT_C2H_FEEDBACK 20 445 #define R92S_EVT_ADDBA 21 446 #define R92S_EVT_C2H_BCN 22 447 #define R92S_EVT_PWR_STATE 23 448 #define R92S_EVT_WPS_PBC 24 449 #define R92S_EVT_ADDBA_REQ_REPORT 25 450 451 /* Structure for R92S_CMD_SITE_SURVEY. */ 452 struct r92s_fw_cmd_sitesurvey { 453 uint32_t active; 454 uint32_t limit; 455 uint32_t ssidlen; 456 uint8_t ssid[32 + 1]; 457 } __packed; 458 459 /* Structure for R92S_CMD_SET_AUTH. */ 460 struct r92s_fw_cmd_auth { 461 uint8_t mode; 462 #define R92S_AUTHMODE_OPEN 0 463 #define R92S_AUTHMODE_SHARED 1 464 #define R92S_AUTHMODE_WPA 2 465 466 uint8_t dot1x; 467 } __packed; 468 469 /* Structure for R92S_CMD_SET_KEY. */ 470 struct r92s_fw_cmd_set_key { 471 uint8_t algo; 472 #define R92S_KEY_ALGO_NONE 0 473 #define R92S_KEY_ALGO_WEP40 1 474 #define R92S_KEY_ALGO_TKIP 2 475 #define R92S_KEY_ALGO_TKIP_MMIC 3 476 #define R92S_KEY_ALGO_AES 4 477 #define R92S_KEY_ALGO_WEP104 5 478 #define R92S_KEY_ALGO_INVALID 0xff /* for rsu_crypto_mode() only */ 479 480 uint8_t cam_id; 481 uint8_t grpkey; 482 uint8_t key[IEEE80211_KEYBUF_SIZE]; 483 } __packed; 484 485 /* Structure for R92S_CMD_SET_STA_KEY. */ 486 struct r92s_fw_cmd_set_key_mac { 487 uint8_t macaddr[IEEE80211_ADDR_LEN]; 488 uint8_t algo; 489 uint8_t key[IEEE80211_KEYBUF_SIZE]; 490 } __packed; 491 492 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 493 /* NDIS_802_11_SSID. */ 494 struct ndis_802_11_ssid { 495 uint32_t ssidlen; 496 uint8_t ssid[32]; 497 } __packed; 498 499 /* NDIS_802_11_CONFIGURATION_FH. */ 500 struct ndis_802_11_configuration_fh { 501 uint32_t len; 502 uint32_t hoppattern; 503 uint32_t hopset; 504 uint32_t dwelltime; 505 } __packed; 506 507 /* NDIS_802_11_CONFIGURATION. */ 508 struct ndis_802_11_configuration { 509 uint32_t len; 510 uint32_t bintval; 511 uint32_t atim; 512 uint32_t dsconfig; 513 struct ndis_802_11_configuration_fh fhconfig; 514 } __packed; 515 516 /* NDIS_WLAN_BSSID_EX. */ 517 struct ndis_wlan_bssid_ex { 518 uint32_t len; 519 uint8_t macaddr[IEEE80211_ADDR_LEN]; 520 uint8_t reserved[2]; 521 struct ndis_802_11_ssid ssid; 522 uint32_t privacy; 523 int32_t rssi; 524 uint32_t networktype; 525 #define NDIS802_11FH 0 526 #define NDIS802_11DS 1 527 #define NDIS802_11OFDM5 2 528 #define NDIS802_11OFDM24 3 529 #define NDIS802_11AUTOMODE 4 530 531 struct ndis_802_11_configuration config; 532 uint32_t inframode; 533 #define NDIS802_11IBSS 0 534 #define NDIS802_11INFRASTRUCTURE 1 535 #define NDIS802_11AUTOUNKNOWN 2 536 #define NDIS802_11MONITOR 3 537 #define NDIS802_11APMODE 4 538 539 uint8_t supprates[16]; 540 uint32_t ieslen; 541 /* Followed by ``ieslen'' bytes. */ 542 } __packed; 543 544 /* NDIS_802_11_FIXED_IEs. */ 545 struct ndis_802_11_fixed_ies { 546 uint8_t tstamp[8]; 547 uint16_t bintval; 548 uint16_t capabilities; 549 } __packed; 550 551 /* Structure for R92S_CMD_SET_PWR_MODE. */ 552 struct r92s_set_pwr_mode { 553 uint8_t mode; 554 #define R92S_PS_MODE_ACTIVE 0 555 #define R92S_PS_MODE_MIN 1 556 #define R92S_PS_MODE_MAX 2 557 #define R92S_PS_MODE_DTIM 3 558 #define R92S_PS_MODE_VOIP 4 559 #define R92S_PS_MODE_UAPSD_WMM 5 560 #define R92S_PS_MODE_UAPSD 6 561 #define R92S_PS_MODE_IBSS 7 562 #define R92S_PS_MODE_WWLAN 8 563 #define R92S_PS_MODE_RADIOOFF 9 564 #define R92S_PS_MODE_DISABLE 10 565 566 uint8_t low_traffic_en; 567 uint8_t lpnav_en; 568 uint8_t rf_low_snr_en; 569 uint8_t dps_en; 570 uint8_t bcn_rx_en; 571 uint8_t bcn_pass_cnt; 572 uint8_t bcn_to; 573 uint16_t bcn_itv; 574 uint8_t app_itv; 575 uint8_t awake_bcn_itv; 576 uint8_t smart_ps; 577 uint8_t bcn_pass_time; 578 } __packed; 579 580 /* Structure for R92S_CMD_SET_CHANNEL. */ 581 struct r92s_set_channel { 582 uint32_t channel; 583 } __packed; 584 585 /* Structure for event R92S_EVENT_JOIN_BSS. */ 586 struct r92s_event_join_bss { 587 uint32_t next; 588 uint32_t prev; 589 uint32_t networktype; 590 uint32_t fixed; 591 uint32_t lastscanned; 592 uint32_t associd; 593 uint32_t join_res; 594 struct ndis_wlan_bssid_ex bss; 595 } __packed; 596 597 #define R92S_MACID_BSS 5 /* XXX hardcoded somewhere */ 598 599 /* Rx MAC descriptor. */ 600 struct r92s_rx_stat { 601 uint32_t rxdw0; 602 #define R92S_RXDW0_PKTLEN_M 0x00003fff 603 #define R92S_RXDW0_PKTLEN_S 0 604 #define R92S_RXDW0_CRCERR 0x00004000 605 #define R92S_RXDW0_ICVERR 0x00008000 606 #define R92S_RXDW0_INFOSZ_M 0x000f0000 607 #define R92S_RXDW0_INFOSZ_S 16 608 #define R92S_RXDW0_CIPHER_M 0x00700000 609 #define R92S_RXDW0_CIPHER_S 20 610 #define R92S_RXDW0_QOS 0x00800000 611 #define R92S_RXDW0_SHIFT_M 0x03000000 612 #define R92S_RXDW0_SHIFT_S 24 613 #define R92S_RXDW0_PHYST 0x04000000 614 #define R92S_RXDW0_DECRYPTED 0x08000000 615 616 uint32_t rxdw1; 617 #define R92S_RXDW1_MOREFRAG 0x08000000 618 619 uint32_t rxdw2; 620 #define R92S_RXDW2_FRAG_M 0x0000f000 621 #define R92S_RXDW2_FRAG_S 12 622 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 623 #define R92S_RXDW2_PKTCNT_S 16 624 625 uint32_t rxdw3; 626 #define R92S_RXDW3_RATE_M 0x0000003f 627 #define R92S_RXDW3_RATE_S 0 628 #define R92S_RXDW3_TCPCHKRPT 0x00000800 629 #define R92S_RXDW3_IPCHKRPT 0x00001000 630 #define R92S_RXDW3_TCPCHKVALID 0x00002000 631 #define R92S_RXDW3_HTC 0x00004000 632 633 uint32_t rxdw4; 634 uint32_t tsf_low; 635 } __packed __aligned(4); 636 637 /* Rx PHY descriptor. */ 638 struct r92s_rx_phystat { 639 uint32_t phydw0; 640 uint32_t phydw1; 641 uint32_t phydw2; 642 uint32_t phydw3; 643 uint32_t phydw4; 644 uint32_t phydw5; 645 uint32_t phydw6; 646 uint32_t phydw7; 647 } __packed __aligned(4); 648 649 /* Rx PHY CCK descriptor. */ 650 struct r92s_rx_cck { 651 uint8_t adc_pwdb[4]; 652 uint8_t sq_rpt; 653 uint8_t agc_rpt; 654 } __packed; 655 656 /* Tx MAC descriptor. */ 657 struct r92s_tx_desc { 658 uint32_t txdw0; 659 #define R92S_TXDW0_PKTLEN_M 0x0000ffff 660 #define R92S_TXDW0_PKTLEN_S 0 661 #define R92S_TXDW0_OFFSET_M 0x00ff0000 662 #define R92S_TXDW0_OFFSET_S 16 663 #define R92S_TXDW0_TYPE_M 0x03000000 664 #define R92S_TXDW0_TYPE_S 24 665 #define R92S_TXDW0_LSG 0x04000000 666 #define R92S_TXDW0_FSG 0x08000000 667 #define R92S_TXDW0_LINIP 0x10000000 668 #define R92S_TXDW0_OWN 0x80000000 669 670 uint32_t txdw1; 671 #define R92S_TXDW1_MACID_M 0x0000001f 672 #define R92S_TXDW1_MACID_S 0 673 #define R92S_TXDW1_MOREDATA 0x00000020 674 #define R92S_TXDW1_MOREFRAG 0x00000040 675 #define R92S_TXDW1_QSEL_M 0x00001f00 676 #define R92S_TXDW1_QSEL_S 8 677 #define R92S_TXDW1_QSEL_BE 0x03 678 #define R92S_TXDW1_QSEL_H2C 0x13 679 #define R92S_TXDW1_NONQOS 0x00010000 680 #define R92S_TXDW1_KEYIDX_M 0x00060000 681 #define R92S_TXDW1_KEYIDX_S 17 682 #define R92S_TXDW1_CIPHER_M 0x00c00000 683 #define R92S_TXDW1_CIPHER_S 22 684 #define R92S_TXDW1_CIPHER_NONE 0 685 #define R92S_TXDW1_CIPHER_WEP 1 686 #define R92S_TXDW1_CIPHER_TKIP 2 687 #define R92S_TXDW1_CIPHER_AES 3 688 #define R92S_TXDW1_HWPC 0x80000000 689 690 uint32_t txdw2; 691 #define R92S_TXDW2_RTY_LMT_M 0x0000003f 692 #define R92S_TXDW2_RTY_LMT_S 0 693 #define R92S_TXDW2_RTY_LMT_ENA 0x00000040 694 #define R92S_TXDW2_BMCAST 0x00000080 695 #define R92S_TXDW2_AGGEN 0x20000000 696 #define R92S_TXDW2_BK 0x40000000 697 698 uint32_t txdw3; 699 #define R92S_TXDW3_SEQ_M 0x0fff0000 700 #define R92S_TXDW3_SEQ_S 16 701 #define R92S_TXDW3_FRAG_M 0xf0000000 702 #define R92S_TXDW3_FRAG_S 28 703 704 uint32_t txdw4; 705 #define R92S_TXDW4_TXBW 0x00040000 706 #define R92S_TXDW4_DRVRATE 0x80000000 707 708 uint32_t txdw5; 709 #define R92S_TXDW5_DATARATE_M 0x00007e00 710 #define R92S_TXDW5_DATARATE_S 9 711 #define R92S_TXDW5_DISFB 0x00008000 712 #define R92S_TXDW5_DATARATE_FB_LMT_M 0x001f0000 713 #define R92S_TXDW5_DATARATE_FB_LMT_S 16 714 715 uint16_t ipchksum; 716 uint16_t tcpchksum; 717 718 uint16_t txbufsize; 719 uint16_t reserved1; 720 } __packed __aligned(4); 721 722 struct r92s_add_ba_event { 723 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 724 uint16_t ssn; 725 uint8_t tid; 726 }; 727 728 struct r92s_add_ba_req { 729 uint32_t tid; 730 }; 731 732 /* 733 * Driver definitions. 734 */ 735 #define RSU_RX_LIST_COUNT 1 736 #define RSU_TX_LIST_COUNT 32 737 738 #define RSU_RXBUFSZ (30 * 1024) 739 #define RSU_TXBUFSZ \ 740 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 741 742 #define RSU_TX_TIMEOUT 5000 /* ms */ 743 #define RSU_CMD_TIMEOUT 2000 /* ms */ 744 745 /* Queue ids (used by soft only). */ 746 #define RSU_QID_BCN 0 747 #define RSU_QID_MGT 1 748 #define RSU_QID_BMC 2 749 #define RSU_QID_VO 3 750 #define RSU_QID_VI 4 751 #define RSU_QID_BE 5 752 #define RSU_QID_BK 6 753 #define RSU_QID_RXOFF 7 754 #define RSU_QID_H2C 8 755 #define RSU_QID_C2H 9 756 757 /* Map AC to queue id. */ 758 static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 759 RSU_QID_BE, 760 RSU_QID_BK, 761 RSU_QID_VI, 762 RSU_QID_VO 763 }; 764 765 /* Pipe index to endpoint address mapping. */ 766 static const uint8_t r92s_epaddr[] = 767 { 0x83, 0x04, 0x06, 0x0d, 768 0x05, 0x07, 769 0x89, 0x0a, 0x0b, 0x0c }; 770 771 /* Queue id to pipe index mapping for 4 endpoints configurations. */ 772 static const uint8_t rsu_qid2idx_4ep[] = 773 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 774 775 /* Queue id to pipe index mapping for 6 endpoints configurations. */ 776 static const uint8_t rsu_qid2idx_6ep[] = 777 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 778 779 /* Queue id to pipe index mapping for 11 endpoints configurations. */ 780 static const uint8_t rsu_qid2idx_11ep[] = 781 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 782 783 struct rsu_rx_radiotap_header { 784 struct ieee80211_radiotap_header wr_ihdr; 785 uint64_t wr_tsft; 786 uint8_t wr_flags; 787 uint8_t wr_rate; 788 uint16_t wr_chan_freq; 789 uint16_t wr_chan_flags; 790 uint8_t wr_dbm_antsignal; 791 } __packed __aligned(8); 792 793 #define RSU_RX_RADIOTAP_PRESENT \ 794 (1 << IEEE80211_RADIOTAP_TSFT | \ 795 1 << IEEE80211_RADIOTAP_FLAGS | \ 796 1 << IEEE80211_RADIOTAP_RATE | \ 797 1 << IEEE80211_RADIOTAP_CHANNEL | \ 798 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 799 800 struct rsu_tx_radiotap_header { 801 struct ieee80211_radiotap_header wt_ihdr; 802 uint8_t wt_flags; 803 uint8_t wt_pad; 804 uint16_t wt_chan_freq; 805 uint16_t wt_chan_flags; 806 } __packed; 807 808 #define RSU_TX_RADIOTAP_PRESENT \ 809 (1 << IEEE80211_RADIOTAP_FLAGS | \ 810 1 << IEEE80211_RADIOTAP_CHANNEL) 811 812 struct rsu_softc; 813 814 enum { 815 RSU_BULK_RX, 816 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ 817 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ 818 RSU_BULK_TX_H2C, /* H2C */ 819 RSU_N_TRANSFER, 820 }; 821 822 struct rsu_data { 823 struct rsu_softc *sc; 824 uint8_t *buf; 825 uint16_t buflen; 826 struct mbuf *m; 827 struct ieee80211_node *ni; 828 STAILQ_ENTRY(rsu_data) next; 829 }; 830 831 struct rsu_vap { 832 struct ieee80211vap vap; 833 834 int (*newstate)(struct ieee80211vap *, 835 enum ieee80211_state, int); 836 }; 837 #define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 838 839 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 840 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 841 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 842 843 #define RSU_DELKEY_BMAP_LOCK_INIT(_sc) \ 844 mtx_init(&(_sc)->free_keys_bmap_mtx, "bmap lock", NULL, MTX_DEF) 845 #define RSU_DELKEY_BMAP_LOCK(_sc) mtx_lock(&(_sc)->free_keys_bmap_mtx) 846 #define RSU_DELKEY_BMAP_UNLOCK(_sc) mtx_unlock(&(_sc)->free_keys_bmap_mtx) 847 #define RSU_DELKEY_BMAP_LOCK_DESTROY(_sc) \ 848 mtx_destroy(&(_sc)->free_keys_bmap_mtx) 849 850 struct rsu_softc { 851 struct ieee80211com sc_ic; 852 struct mbufq sc_snd; 853 device_t sc_dev; 854 struct usb_device *sc_udev; 855 856 struct timeout_task calib_task; 857 struct task tx_task; 858 struct mtx sc_mtx; 859 int sc_ht; 860 int sc_nendpoints; 861 int sc_curpwrstate; 862 int sc_currssi; 863 864 u_int sc_running:1, 865 sc_vap_is_running:1, 866 sc_rx_checksum_enable:1, 867 sc_calibrating:1, 868 sc_active_scan:1, 869 sc_extra_scan:1; 870 u_int cut; 871 uint8_t sc_rftype; 872 int8_t sc_nrxstream; 873 int8_t sc_ntxstream; 874 struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 875 struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 876 uint8_t cmd_seq; 877 uint8_t rom[128]; 878 struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 879 880 STAILQ_HEAD(, rsu_data) sc_rx_active; 881 STAILQ_HEAD(, rsu_data) sc_rx_inactive; 882 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; 883 STAILQ_HEAD(, rsu_data) sc_tx_inactive; 884 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; 885 886 struct task del_key_task; 887 uint8_t keys_bmap[R92S_CAM_ENTRY_BYTES]; 888 const struct ieee80211_key *group_keys[IEEE80211_WEP_NKID]; 889 890 struct mtx free_keys_bmap_mtx; 891 uint8_t free_keys_bmap[R92S_CAM_ENTRY_BYTES]; 892 893 union { 894 struct rsu_rx_radiotap_header th; 895 uint8_t pad[64]; 896 } sc_rxtapu; 897 #define sc_rxtap sc_rxtapu.th 898 899 union { 900 struct rsu_tx_radiotap_header th; 901 uint8_t pad[64]; 902 } sc_txtapu; 903 #define sc_txtap sc_txtapu.th 904 };
Cache object: 82565718dcab1679fe316265b1917374
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