Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/wlan/if_uathreg.h
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1 /* $OpenBSD: if_uathreg.h,v 1.2 2006/09/18 16:34:23 damien Exp $ */ 2 /* $FreeBSD$ */ 3 4 /*- 5 * Copyright (c) 2006 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * Copyright (c) 2006 Sam Leffler, Errno Consulting 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #define UATH_CONFIG_INDEX 0 23 #define UATH_IFACE_INDEX 0 24 25 /* all fields are big endian */ 26 struct uath_fwblock { 27 uint32_t flags; 28 #define UATH_WRITE_BLOCK (1 << 4) 29 30 uint32_t len; 31 #define UATH_MAX_FWBLOCK_SIZE 2048 32 33 uint32_t total; 34 uint32_t remain; 35 uint32_t rxtotal; 36 uint32_t pad[123]; 37 } __packed; 38 39 #define UATH_MAX_CMDSZ 512 40 41 /* 42 * Messages are passed in Target Endianness. All fixed-size 43 * fields of a WDS Control Message are treated as 32-bit 44 * values and Control Msgs are guaranteed to be 32-bit aligned. 45 * 46 * The format of a WDS Control Message is as follows: 47 * Message Length 32 bits 48 * Message Opcode 32 bits 49 * Message ID 32 bits 50 * parameter 1 51 * parameter 2 52 * ... 53 * 54 * A variable-length parameter, or a parmeter that is larger than 55 * 32 bits is passed as <length, data> pair, where length is a 56 * 32-bit quantity and data is padded to 32 bits. 57 */ 58 struct uath_cmd_hdr { 59 uint32_t len; /* msg length including header */ 60 uint32_t code; /* operation code */ 61 /* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ 62 /* messages from Host -> Target */ 63 #define WDCMSG_HOST_AVAILABLE 0x01 64 #define WDCMSG_BIND 0x02 65 #define WDCMSG_TARGET_RESET 0x03 66 #define WDCMSG_TARGET_GET_CAPABILITY 0x04 67 #define WDCMSG_TARGET_SET_CONFIG 0x05 68 #define WDCMSG_TARGET_GET_STATUS 0x06 69 #define WDCMSG_TARGET_GET_STATS 0x07 70 #define WDCMSG_TARGET_START 0x08 71 #define WDCMSG_TARGET_STOP 0x09 72 #define WDCMSG_TARGET_ENABLE 0x0a 73 #define WDCMSG_TARGET_DISABLE 0x0b 74 #define WDCMSG_CREATE_CONNECTION 0x0c 75 #define WDCMSG_UPDATE_CONNECT_ATTR 0x0d 76 #define WDCMSG_DELETE_CONNECT 0x0e 77 #define WDCMSG_SEND 0x0f 78 #define WDCMSG_FLUSH 0x10 79 /* messages from Target -> Host */ 80 #define WDCMSG_STATS_UPDATE 0x11 81 #define WDCMSG_BMISS 0x12 82 #define WDCMSG_DEVICE_AVAIL 0x13 83 #define WDCMSG_SEND_COMPLETE 0x14 84 #define WDCMSG_DATA_AVAIL 0x15 85 #define WDCMSG_SET_PWR_MODE 0x16 86 #define WDCMSG_BMISS_ACK 0x17 87 #define WDCMSG_SET_LED_STEADY 0x18 88 #define WDCMSG_SET_LED_BLINK 0x19 89 /* more messages */ 90 #define WDCMSG_SETUP_BEACON_DESC 0x1a 91 #define WDCMSG_BEACON_INIT 0x1b 92 #define WDCMSG_RESET_KEY_CACHE 0x1c 93 #define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d 94 #define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e 95 #define WDCMSG_SET_DECOMP_MASK 0x1f 96 #define WDCMSG_SET_REGULATORY_DOMAIN 0x20 97 #define WDCMSG_SET_LED_STATE 0x21 98 #define WDCMSG_WRITE_ASSOCID 0x22 99 #define WDCMSG_SET_STA_BEACON_TIMERS 0x23 100 #define WDCMSG_GET_TSF 0x24 101 #define WDCMSG_RESET_TSF 0x25 102 #define WDCMSG_SET_ADHOC_MODE 0x26 103 #define WDCMSG_SET_BASIC_RATE 0x27 104 #define WDCMSG_MIB_CONTROL 0x28 105 #define WDCMSG_GET_CHANNEL_DATA 0x29 106 #define WDCMSG_GET_CUR_RSSI 0x2a 107 #define WDCMSG_SET_ANTENNA_SWITCH 0x2b 108 #define WDCMSG_USE_SHORT_SLOT_TIME 0x2f 109 #define WDCMSG_SET_POWER_MODE 0x30 110 #define WDCMSG_SETUP_PSPOLL_DESC 0x31 111 #define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 112 #define WDCMSG_RX_FILTER 0x33 113 #define WDCMSG_PER_CALIBRATION 0x34 114 #define WDCMSG_RESET 0x35 115 #define WDCMSG_DISABLE 0x36 116 #define WDCMSG_PHY_DISABLE 0x37 117 #define WDCMSG_SET_TX_POWER_LIMIT 0x38 118 #define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 119 #define WDCMSG_SETUP_TX_QUEUE 0x3a 120 #define WDCMSG_RELEASE_TX_QUEUE 0x3b 121 #define WDCMSG_SET_DEFAULT_KEY 0x43 122 uint32_t msgid; /* msg id (supplied by host) */ 123 uint32_t magic; /* response desired/target status */ 124 uint32_t debug[4]; /* debug data area */ 125 /* msg data follows */ 126 } __packed; 127 128 struct uath_chunk { 129 uint8_t seqnum; /* sequence number for ordering */ 130 uint8_t flags; 131 #define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ 132 #define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ 133 #define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ 134 uint16_t length; /* chunk size in bytes */ 135 /* chunk data follows */ 136 } __packed; 137 138 #define UATH_RX_DUMMYSIZE 4 139 140 /* 141 * Message format for a WDCMSG_DATA_AVAIL message from Target to Host. 142 */ 143 struct uath_rx_desc { 144 uint32_t len; /* msg length including header */ 145 uint32_t code; /* WDCMSG_DATA_AVAIL */ 146 uint32_t gennum; /* generation number */ 147 uint32_t status; /* start of RECEIVE_INFO */ 148 #define UATH_STATUS_OK 0 149 #define UATH_STATUS_STOP_IN_PROGRESS 1 150 #define UATH_STATUS_CRC_ERR 2 151 #define UATH_STATUS_PHY_ERR 3 152 #define UATH_STATUS_DECRYPT_CRC_ERR 4 153 #define UATH_STATUS_DECRYPT_MIC_ERR 5 154 #define UATH_STATUS_DECOMP_ERR 6 155 #define UATH_STATUS_KEY_ERR 7 156 #define UATH_STATUS_ERR 8 157 uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */ 158 uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */ 159 uint32_t framelen; /* frame length */ 160 uint32_t rate; /* rx rate code */ 161 uint32_t antenna; 162 int32_t rssi; 163 uint32_t channel; 164 uint32_t phyerror; 165 uint32_t connix; /* key table ix for bss traffic */ 166 uint32_t decrypterror; 167 uint32_t keycachemiss; 168 uint32_t pad; /* XXX? */ 169 } __packed; 170 171 struct uath_tx_desc { 172 uint32_t msglen; 173 uint32_t msgid; /* msg id (supplied by host) */ 174 uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ 175 uint32_t txqid; /* tx queue id and flags */ 176 #define UATH_TXQID_MASK 0x0f 177 #define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ 178 #define UATH_TXQID_FF 0x20 /* content is fast frame */ 179 uint32_t connid; /* tx connection id */ 180 #define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ 181 uint32_t flags; /* non-zero if response desired */ 182 #define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ 183 uint32_t buflen; /* payload length */ 184 } __packed; 185 186 struct uath_cmd_host_available { 187 uint32_t sw_ver_major; 188 uint32_t sw_ver_minor; 189 uint32_t sw_ver_patch; 190 uint32_t sw_ver_build; 191 } __packed; 192 #define ATH_SW_VER_MAJOR 1 193 #define ATH_SW_VER_MINOR 5 194 #define ATH_SW_VER_PATCH 0 195 #define ATH_SW_VER_BUILD 9999 196 197 struct uath_cmd_bind { 198 uint32_t targethandle; 199 uint32_t hostapiversion; 200 } __packed; 201 202 /* structure for command WDCMSG_RESET */ 203 struct uath_cmd_reset { 204 uint32_t flags; /* channel flags */ 205 #define UATH_CHAN_TURBO 0x0100 206 #define UATH_CHAN_CCK 0x0200 207 #define UATH_CHAN_OFDM 0x0400 208 #define UATH_CHAN_2GHZ 0x1000 209 #define UATH_CHAN_5GHZ 0x2000 210 uint32_t freq; /* channel frequency */ 211 uint32_t maxrdpower; 212 uint32_t cfgctl; 213 uint32_t twiceantennareduction; 214 uint32_t channelchange; 215 uint32_t keeprccontent; 216 } __packed; 217 218 /* structure for commands UATH_CMD_READ_MAC and UATH_CMD_READ_EEPROM */ 219 struct uath_read_mac { 220 uint32_t len; 221 uint8_t data[32]; 222 } __packed; 223 224 /* structure for command UATH_CMD_WRITE_MAC */ 225 struct uath_write_mac { 226 uint32_t reg; 227 uint32_t len; 228 uint8_t data[32]; 229 } __packed; 230 231 /* structure for command UATH_CMD_STA_JOIN */ 232 struct uath_cmd_join_bss { 233 uint32_t bssid; /* NB: use zero */ 234 uint32_t bssmac[2]; /* bssid mac address */ 235 uint32_t bsstype; 236 uint32_t wlanmode; 237 uint32_t beaconinterval; 238 uint32_t dtiminterval; 239 uint32_t cfpinterval; 240 uint32_t atimwindow; 241 uint32_t defaultrateix; 242 uint32_t shortslottime11g; 243 uint32_t sleepduration; 244 uint32_t bmissthreshold; 245 uint32_t tcppowerlimit; 246 uint32_t quietduration; 247 uint32_t quietoffset; 248 uint32_t quietackctsallow; 249 uint32_t bssdefaultkey; /* XXX? */ 250 } __packed; 251 252 struct uath_cmd_assoc_bss { 253 uint32_t bssid; 254 uint32_t associd; 255 } __packed; 256 257 struct uath_cmd_start_bss { 258 uint32_t bssid; 259 } __packed; 260 261 /* structure for command UATH_CMD_0C */ 262 struct uath_cmd_0c { 263 uint32_t magic1; 264 uint32_t magic2; 265 uint32_t magic3; 266 } __packed; 267 268 struct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ 269 uint32_t lednum; 270 #define UATH_LED_LINK 0 271 #define UATH_LED_ACTIVITY 1 272 uint32_t ledmode; 273 #define UATH_LED_OFF 0 274 #define UATH_LED_ON 1 275 } __packed; 276 277 struct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ 278 uint32_t lednum; 279 uint32_t ledmode; 280 uint32_t blinkrate; 281 uint32_t slowmode; 282 } __packed; 283 284 struct uath_cmd_ledstate { /* WDCMSG_SET_LED_STATE */ 285 uint32_t connected; 286 } __packed; 287 288 struct uath_connkey_rec { 289 uint8_t bssid[IEEE80211_ADDR_LEN]; 290 uint32_t keyiv; 291 uint32_t extkeyiv; 292 uint16_t keyflags; 293 uint16_t keylen; 294 uint16_t keytype; /* WEP, TKIP or AES */ 295 /* As far as I know, MIPS 4Kp is 32-bit processor */ 296 uint32_t priv; 297 uint8_t keyval[32]; 298 uint16_t aes_keylen; 299 uint8_t aes_keyval[16]; 300 uint8_t mic_txkeyval[8]; 301 uint8_t mic_rxkeyval[8]; 302 int64_t keyrsc[17]; 303 int32_t keytsc[17]; 304 int32_t keyexttsc[17]; 305 } __packed; 306 307 /* structure for command UATH_CMD_CRYPTO */ 308 struct uath_cmd_crypto { 309 uint32_t keyidx; 310 #define UATH_DEFAULT_KEY 6 311 uint32_t xorkey; 312 uint32_t size; 313 struct uath_connkey_rec rec; 314 } __packed; 315 316 struct uath_cmd_rateset { 317 uint8_t length; 318 #define UATH_MAX_NRATES 32 319 uint8_t set[UATH_MAX_NRATES]; 320 }; 321 322 /* structure for command WDCMSG_SET_BASIC_RATE */ 323 struct uath_cmd_rates { 324 uint32_t connid; 325 uint32_t keeprccontent; 326 uint32_t size; 327 struct uath_cmd_rateset rateset; 328 } __packed; 329 330 enum { 331 WLAN_MODE_NONE = 0, 332 WLAN_MODE_11b, 333 WLAN_MODE_11a, 334 WLAN_MODE_11g, 335 WLAN_MODE_11a_TURBO, 336 WLAN_MODE_11g_TURBO, 337 WLAN_MODE_11a_TURBO_PRIME, 338 WLAN_MODE_11g_TURBO_PRIME, 339 WLAN_MODE_11a_XR, 340 WLAN_MODE_11g_XR, 341 }; 342 343 struct uath_cmd_connection_attr { 344 uint32_t longpreambleonly; 345 struct uath_cmd_rateset rateset; 346 uint32_t wlanmode; 347 } __packed; 348 349 /* structure for command WDCMSG_CREATE_CONNECTION */ 350 struct uath_cmd_create_connection { 351 uint32_t connid; 352 uint32_t bssid; 353 uint32_t size; 354 struct uath_cmd_connection_attr connattr; 355 } __packed; 356 357 struct uath_cmd_txq_setparams { /* WDCMSG_SET_TX_QUEUE_PARAMS */ 358 uint32_t qnum; 359 uint32_t aifs; 360 uint32_t logcwmin; 361 uint32_t logcwmax; 362 uint32_t bursttime; 363 uint32_t qflags; 364 } __packed; 365 366 struct uath_cmd_txq_attr { 367 uint32_t priority; 368 uint32_t aifs; 369 uint32_t logcwmin; 370 uint32_t logcwmax; 371 uint32_t bursttime; 372 uint32_t mode; 373 uint32_t qflags; 374 } __packed; 375 376 struct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ 377 uint32_t qid; 378 uint32_t len; 379 struct uath_cmd_txq_attr attr; 380 } __packed; 381 382 struct uath_cmd_stoptxdma { /* WDCMSG_STOP_TX_DMA */ 383 uint32_t qnum; 384 uint32_t msec; 385 } __packed; 386 387 /* structure for command UATH_CMD_31 */ 388 struct uath_cmd_31 { 389 uint32_t magic1; 390 uint32_t magic2; 391 } __packed; 392 393 struct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */ 394 uint32_t bits; 395 #define UATH_FILTER_RX_UCAST 0x00000001 396 #define UATH_FILTER_RX_MCAST 0x00000002 397 #define UATH_FILTER_RX_BCAST 0x00000004 398 #define UATH_FILTER_RX_CONTROL 0x00000008 399 #define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ 400 #define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ 401 #define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ 402 #define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ 403 #define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ 404 #define UATH_FILTER_RX_PROBE_REQ 0x00000800 405 uint32_t op; 406 #define UATH_FILTER_OP_INIT 0x0 407 #define UATH_FILTER_OP_SET 0x1 408 #define UATH_FILTER_OP_CLEAR 0x2 409 #define UATH_FILTER_OP_TEMP 0x3 410 #define UATH_FILTER_OP_RESTORE 0x4 411 } __packed; 412 413 struct uath_cmd_rx_mcast_filter { /* WDCMSG_SET_RX_MCAST_FILTER */ 414 uint32_t filter0; 415 uint32_t filter1; 416 } __packed; 417 418 struct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */ 419 uint32_t defaultrateix; 420 uint32_t associd; 421 uint32_t timoffset; 422 uint32_t turboprime; 423 uint32_t bssid[2]; 424 } __packed; 425 426 struct uath_cmd_set_stabeacon_timers { /* WDCMSG_SET_STA_BEACON_TIMERS */ 427 uint32_t nexttbtt; 428 uint32_t nextdtim; 429 uint32_t nextcfp; 430 uint32_t beaconperiod; 431 uint32_t dtimperiod; 432 uint32_t cfpperiod; 433 uint32_t cfpduration; 434 uint32_t sleepduration; 435 uint32_t bsmissthreshold; 436 } __packed; 437 438 enum { 439 CFG_NONE, /* Sentinal to indicate "no config" */ 440 CFG_REG_DOMAIN, /* Regulatory Domain */ 441 CFG_RATE_CONTROL_ENABLE, 442 CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ 443 CFG_HW_TX_RETRIES, 444 CFG_SW_TX_RETRIES, 445 CFG_SLOW_CLOCK_ENABLE, 446 CFG_COMP_PROC, 447 CFG_USER_RTS_THRESHOLD, 448 CFG_XR2NORM_RATE_THRESHOLD, 449 CFG_XRMODE_SWITCH_COUNT, 450 CFG_PROTECTION_TYPE, 451 CFG_BURST_SEQ_THRESHOLD, 452 CFG_ABOLT, 453 CFG_IQ_LOG_COUNT_MAX, 454 CFG_MODE_CTS, 455 CFG_WME_ENABLED, 456 CFG_GPRS_CBR_PERIOD, 457 CFG_SERVICE_TYPE, 458 /* MAC Address to use. Overrides EEPROM */ 459 CFG_MAC_ADDR, 460 CFG_DEBUG_EAR, 461 CFG_INIT_REGS, 462 /* An ID for use in error & debug messages */ 463 CFG_DEBUG_ID, 464 CFG_COMP_WIN_SZ, 465 CFG_DIVERSITY_CTL, 466 CFG_TP_SCALE, 467 CFG_TPC_HALF_DBM5, 468 CFG_TPC_HALF_DBM2, 469 CFG_OVERRD_TX_POWER, 470 CFG_USE_32KHZ_CLOCK, 471 CFG_GMODE_PROTECTION, 472 CFG_GMODE_PROTECT_RATE_INDEX, 473 CFG_GMODE_NON_ERP_PREAMBLE, 474 CFG_WDC_TRANSPORT_CHUNK_SIZE, 475 }; 476 477 enum { 478 /* Sentinal to indicate "no capability" */ 479 CAP_NONE, 480 CAP_ALL, /* ALL capabilities */ 481 CAP_TARGET_VERSION, 482 CAP_TARGET_REVISION, 483 CAP_MAC_VERSION, 484 CAP_MAC_REVISION, 485 CAP_PHY_REVISION, 486 CAP_ANALOG_5GHz_REVISION, 487 CAP_ANALOG_2GHz_REVISION, 488 /* Target supports WDC message debug features */ 489 CAP_DEBUG_WDCMSG_SUPPORT, 490 491 CAP_REG_DOMAIN, 492 CAP_COUNTRY_CODE, 493 CAP_REG_CAP_BITS, 494 495 CAP_WIRELESS_MODES, 496 CAP_CHAN_SPREAD_SUPPORT, 497 CAP_SLEEP_AFTER_BEACON_BROKEN, 498 CAP_COMPRESS_SUPPORT, 499 CAP_BURST_SUPPORT, 500 CAP_FAST_FRAMES_SUPPORT, 501 CAP_CHAP_TUNING_SUPPORT, 502 CAP_TURBOG_SUPPORT, 503 CAP_TURBO_PRIME_SUPPORT, 504 CAP_DEVICE_TYPE, 505 CAP_XR_SUPPORT, 506 CAP_WME_SUPPORT, 507 CAP_TOTAL_QUEUES, 508 CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ 509 510 CAP_LOW_5GHZ_CHAN, 511 CAP_HIGH_5GHZ_CHAN, 512 CAP_LOW_2GHZ_CHAN, 513 CAP_HIGH_2GHZ_CHAN, 514 515 CAP_MIC_AES_CCM, 516 CAP_MIC_CKIP, 517 CAP_MIC_TKIP, 518 CAP_MIC_TKIP_WME, 519 CAP_CIPHER_AES_CCM, 520 CAP_CIPHER_CKIP, 521 CAP_CIPHER_TKIP, 522 523 CAP_TWICE_ANTENNAGAIN_5G, 524 CAP_TWICE_ANTENNAGAIN_2G, 525 }; 526 527 enum { 528 ST_NONE, /* Sentinal to indicate "no status" */ 529 ST_ALL, 530 ST_SERVICE_TYPE, 531 ST_WLAN_MODE, 532 ST_FREQ, 533 ST_BAND, 534 ST_LAST_RSSI, 535 ST_PS_FRAMES_DROPPED, 536 ST_CACHED_DEF_ANT, 537 ST_COUNT_OTHER_RX_ANT, 538 ST_USE_FAST_DIVERSITY, 539 ST_MAC_ADDR, 540 ST_RX_GENERATION_NUM, 541 ST_TX_QUEUE_DEPTH, 542 ST_SERIAL_NUMBER, 543 ST_WDC_TRANSPORT_CHUNK_SIZE, 544 }; 545 546 enum { 547 BSS_ATTR_BEACON_INTERVAL, 548 BSS_ATTR_DTIM_INTERVAL, 549 BSS_ATTR_CFP_INTERVAL, 550 BSS_ATTR_CFP_MAX_DURATION, 551 BSS_ATTR_ATIM_WINDOW, 552 BSS_ATTR_DEFAULT_RATE_INDEX, 553 BSS_ATTR_SHORT_SLOT_TIME_11g, 554 BSS_ATTR_SLEEP_DURATION, 555 BSS_ATTR_BMISS_THRESHOLD, 556 BSS_ATTR_TPC_POWER_LIMIT, 557 BSS_ATTR_BSS_KEY_UPDATE, 558 }; 559 560 struct uath_cmd_update_bss_attribute { 561 uint32_t bssid; 562 uint32_t attribute; /* BSS_ATTR_BEACON_INTERVAL, et al. */ 563 uint32_t cfgsize; /* should be zero 0 */ 564 uint32_t cfgdata; 565 }; 566 567 struct uath_cmd_update_bss_attribute_key { 568 uint32_t bssid; 569 uint32_t attribute; /* BSS_ATTR_BSS_KEY_UPDATE */ 570 uint32_t cfgsize; /* size of remaining data */ 571 uint32_t bsskeyix; 572 uint32_t isdefaultkey; 573 uint32_t keyiv; /* IV generation control */ 574 uint32_t extkeyiv; /* extended IV for TKIP & CCM */ 575 uint32_t keyflags; 576 uint32_t keytype; 577 uint32_t initvalue; /* XXX */ 578 uint32_t keyval[4]; 579 uint32_t mictxkeyval[2]; 580 uint32_t micrxkeyval[2]; 581 uint32_t keyrsc[2]; 582 }; 583 584 enum { 585 TARGET_DEVICE_AWAKE, 586 TARGET_DEVICE_SLEEP, 587 TARGET_DEVICE_PWRDN, 588 TARGET_DEVICE_PWRSAVE, 589 TARGET_DEVICE_SUSPEND, 590 TARGET_DEVICE_RESUME, 591 }; 592 593 #define UATH_MAX_TXBUFSZ \ 594 (sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc) + \ 595 IEEE80211_MAX_LEN) 596 597 /* 598 * it's not easy to measure how the chunk is passed into the host if the target 599 * passed the multi-chunks so just we check a minimal size we can imagine. 600 */ 601 #define UATH_MIN_RXBUFSZ (sizeof(struct uath_chunk))
Cache object: 3d8595eba37205d8cf30c414b0e0f59f
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