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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/wlan/if_ural.c
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1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 /*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31 #include "opt_wlan.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 #include <sys/kdb.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/if_ether.h> 62 #include <netinet/ip.h> 63 #endif 64 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_regdomain.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_ratectl.h> 69 70 #include <dev/usb/usb.h> 71 #include <dev/usb/usbdi.h> 72 #include "usbdevs.h" 73 74 #define USB_DEBUG_VAR ural_debug 75 #include <dev/usb/usb_debug.h> 76 77 #include <dev/usb/wlan/if_uralreg.h> 78 #include <dev/usb/wlan/if_uralvar.h> 79 80 #ifdef USB_DEBUG 81 static int ural_debug = 0; 82 83 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 84 "USB ural"); 85 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 86 "Debug level"); 87 #endif 88 89 #define URAL_RSSI(rssi) \ 90 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 91 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 92 93 /* various supported device vendors/products */ 94 static const STRUCT_USB_HOST_ID ural_devs[] = { 95 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96 URAL_DEV(ASUS, WL167G), 97 URAL_DEV(ASUS, RT2570), 98 URAL_DEV(BELKIN, F5D7050), 99 URAL_DEV(BELKIN, F5D7051), 100 URAL_DEV(CISCOLINKSYS, HU200TS), 101 URAL_DEV(CISCOLINKSYS, WUSB54G), 102 URAL_DEV(CISCOLINKSYS, WUSB54GP), 103 URAL_DEV(CONCEPTRONIC2, C54RU), 104 URAL_DEV(DLINK, DWLG122), 105 URAL_DEV(GIGABYTE, GN54G), 106 URAL_DEV(GIGABYTE, GNWBKG), 107 URAL_DEV(GUILLEMOT, HWGUSB254), 108 URAL_DEV(MELCO, KG54), 109 URAL_DEV(MELCO, KG54AI), 110 URAL_DEV(MELCO, KG54YB), 111 URAL_DEV(MELCO, NINWIFI), 112 URAL_DEV(MSI, RT2570), 113 URAL_DEV(MSI, RT2570_2), 114 URAL_DEV(MSI, RT2570_3), 115 URAL_DEV(NOVATECH, NV902), 116 URAL_DEV(RALINK, RT2570), 117 URAL_DEV(RALINK, RT2570_2), 118 URAL_DEV(RALINK, RT2570_3), 119 URAL_DEV(SIEMENS2, WL54G), 120 URAL_DEV(SMC, 2862WG), 121 URAL_DEV(SPHAIRON, UB801R), 122 URAL_DEV(SURECOM, RT2570), 123 URAL_DEV(VTECH, RT2570), 124 URAL_DEV(ZINWELL, RT2570), 125 #undef URAL_DEV 126 }; 127 128 static usb_callback_t ural_bulk_read_callback; 129 static usb_callback_t ural_bulk_write_callback; 130 131 static usb_error_t ural_do_request(struct ural_softc *sc, 132 struct usb_device_request *req, void *data); 133 static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 134 const char [IFNAMSIZ], int, enum ieee80211_opmode, 135 int, const uint8_t [IEEE80211_ADDR_LEN], 136 const uint8_t [IEEE80211_ADDR_LEN]); 137 static void ural_vap_delete(struct ieee80211vap *); 138 static void ural_tx_free(struct ural_tx_data *, int); 139 static void ural_setup_tx_list(struct ural_softc *); 140 static void ural_unsetup_tx_list(struct ural_softc *); 141 static int ural_newstate(struct ieee80211vap *, 142 enum ieee80211_state, int); 143 static void ural_setup_tx_desc(struct ural_softc *, 144 struct ural_tx_desc *, uint32_t, int, int); 145 static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 146 struct ieee80211_node *); 147 static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 148 struct ieee80211_node *); 149 static int ural_tx_data(struct ural_softc *, struct mbuf *, 150 struct ieee80211_node *); 151 static int ural_transmit(struct ieee80211com *, struct mbuf *); 152 static void ural_start(struct ural_softc *); 153 static void ural_parent(struct ieee80211com *); 154 static void ural_set_testmode(struct ural_softc *); 155 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 156 int); 157 static uint16_t ural_read(struct ural_softc *, uint16_t); 158 static void ural_read_multi(struct ural_softc *, uint16_t, void *, 159 int); 160 static void ural_write(struct ural_softc *, uint16_t, uint16_t); 161 static void ural_write_multi(struct ural_softc *, uint16_t, void *, 162 int) __unused; 163 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 164 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 165 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 166 static void ural_scan_start(struct ieee80211com *); 167 static void ural_scan_end(struct ieee80211com *); 168 static void ural_getradiocaps(struct ieee80211com *, int, int *, 169 struct ieee80211_channel[]); 170 static void ural_set_channel(struct ieee80211com *); 171 static void ural_set_chan(struct ural_softc *, 172 struct ieee80211_channel *); 173 static void ural_disable_rf_tune(struct ural_softc *); 174 static void ural_enable_tsf_sync(struct ural_softc *); 175 static void ural_enable_tsf(struct ural_softc *); 176 static void ural_update_slot(struct ural_softc *); 177 static void ural_set_txpreamble(struct ural_softc *); 178 static void ural_set_basicrates(struct ural_softc *, 179 const struct ieee80211_channel *); 180 static void ural_set_bssid(struct ural_softc *, const uint8_t *); 181 static void ural_set_macaddr(struct ural_softc *, const uint8_t *); 182 static void ural_update_promisc(struct ieee80211com *); 183 static void ural_setpromisc(struct ural_softc *); 184 static const char *ural_get_rf(int); 185 static void ural_read_eeprom(struct ural_softc *); 186 static int ural_bbp_init(struct ural_softc *); 187 static void ural_set_txantenna(struct ural_softc *, int); 188 static void ural_set_rxantenna(struct ural_softc *, int); 189 static void ural_init(struct ural_softc *); 190 static void ural_stop(struct ural_softc *); 191 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 192 const struct ieee80211_bpf_params *); 193 static void ural_ratectl_start(struct ural_softc *, 194 struct ieee80211_node *); 195 static void ural_ratectl_timeout(void *); 196 static void ural_ratectl_task(void *, int); 197 static int ural_pause(struct ural_softc *sc, int timeout); 198 199 /* 200 * Default values for MAC registers; values taken from the reference driver. 201 */ 202 static const struct { 203 uint16_t reg; 204 uint16_t val; 205 } ural_def_mac[] = { 206 { RAL_TXRX_CSR5, 0x8c8d }, 207 { RAL_TXRX_CSR6, 0x8b8a }, 208 { RAL_TXRX_CSR7, 0x8687 }, 209 { RAL_TXRX_CSR8, 0x0085 }, 210 { RAL_MAC_CSR13, 0x1111 }, 211 { RAL_MAC_CSR14, 0x1e11 }, 212 { RAL_TXRX_CSR21, 0xe78f }, 213 { RAL_MAC_CSR9, 0xff1d }, 214 { RAL_MAC_CSR11, 0x0002 }, 215 { RAL_MAC_CSR22, 0x0053 }, 216 { RAL_MAC_CSR15, 0x0000 }, 217 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 218 { RAL_TXRX_CSR19, 0x0000 }, 219 { RAL_TXRX_CSR18, 0x005a }, 220 { RAL_PHY_CSR2, 0x0000 }, 221 { RAL_TXRX_CSR0, 0x1ec0 }, 222 { RAL_PHY_CSR4, 0x000f } 223 }; 224 225 /* 226 * Default values for BBP registers; values taken from the reference driver. 227 */ 228 static const struct { 229 uint8_t reg; 230 uint8_t val; 231 } ural_def_bbp[] = { 232 { 3, 0x02 }, 233 { 4, 0x19 }, 234 { 14, 0x1c }, 235 { 15, 0x30 }, 236 { 16, 0xac }, 237 { 17, 0x48 }, 238 { 18, 0x18 }, 239 { 19, 0xff }, 240 { 20, 0x1e }, 241 { 21, 0x08 }, 242 { 22, 0x08 }, 243 { 23, 0x08 }, 244 { 24, 0x80 }, 245 { 25, 0x50 }, 246 { 26, 0x08 }, 247 { 27, 0x23 }, 248 { 30, 0x10 }, 249 { 31, 0x2b }, 250 { 32, 0xb9 }, 251 { 34, 0x12 }, 252 { 35, 0x50 }, 253 { 39, 0xc4 }, 254 { 40, 0x02 }, 255 { 41, 0x60 }, 256 { 53, 0x10 }, 257 { 54, 0x18 }, 258 { 56, 0x08 }, 259 { 57, 0x10 }, 260 { 58, 0x08 }, 261 { 61, 0x60 }, 262 { 62, 0x10 }, 263 { 75, 0xff } 264 }; 265 266 /* 267 * Default values for RF register R2 indexed by channel numbers. 268 */ 269 static const uint32_t ural_rf2522_r2[] = { 270 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 271 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 272 }; 273 274 static const uint32_t ural_rf2523_r2[] = { 275 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 276 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 277 }; 278 279 static const uint32_t ural_rf2524_r2[] = { 280 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 281 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 282 }; 283 284 static const uint32_t ural_rf2525_r2[] = { 285 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 286 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 287 }; 288 289 static const uint32_t ural_rf2525_hi_r2[] = { 290 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 291 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 292 }; 293 294 static const uint32_t ural_rf2525e_r2[] = { 295 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 296 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 297 }; 298 299 static const uint32_t ural_rf2526_hi_r2[] = { 300 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 301 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 302 }; 303 304 static const uint32_t ural_rf2526_r2[] = { 305 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 306 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 307 }; 308 309 /* 310 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 311 * values taken from the reference driver. 312 */ 313 static const struct { 314 uint8_t chan; 315 uint32_t r1; 316 uint32_t r2; 317 uint32_t r4; 318 } ural_rf5222[] = { 319 { 1, 0x08808, 0x0044d, 0x00282 }, 320 { 2, 0x08808, 0x0044e, 0x00282 }, 321 { 3, 0x08808, 0x0044f, 0x00282 }, 322 { 4, 0x08808, 0x00460, 0x00282 }, 323 { 5, 0x08808, 0x00461, 0x00282 }, 324 { 6, 0x08808, 0x00462, 0x00282 }, 325 { 7, 0x08808, 0x00463, 0x00282 }, 326 { 8, 0x08808, 0x00464, 0x00282 }, 327 { 9, 0x08808, 0x00465, 0x00282 }, 328 { 10, 0x08808, 0x00466, 0x00282 }, 329 { 11, 0x08808, 0x00467, 0x00282 }, 330 { 12, 0x08808, 0x00468, 0x00282 }, 331 { 13, 0x08808, 0x00469, 0x00282 }, 332 { 14, 0x08808, 0x0046b, 0x00286 }, 333 334 { 36, 0x08804, 0x06225, 0x00287 }, 335 { 40, 0x08804, 0x06226, 0x00287 }, 336 { 44, 0x08804, 0x06227, 0x00287 }, 337 { 48, 0x08804, 0x06228, 0x00287 }, 338 { 52, 0x08804, 0x06229, 0x00287 }, 339 { 56, 0x08804, 0x0622a, 0x00287 }, 340 { 60, 0x08804, 0x0622b, 0x00287 }, 341 { 64, 0x08804, 0x0622c, 0x00287 }, 342 343 { 100, 0x08804, 0x02200, 0x00283 }, 344 { 104, 0x08804, 0x02201, 0x00283 }, 345 { 108, 0x08804, 0x02202, 0x00283 }, 346 { 112, 0x08804, 0x02203, 0x00283 }, 347 { 116, 0x08804, 0x02204, 0x00283 }, 348 { 120, 0x08804, 0x02205, 0x00283 }, 349 { 124, 0x08804, 0x02206, 0x00283 }, 350 { 128, 0x08804, 0x02207, 0x00283 }, 351 { 132, 0x08804, 0x02208, 0x00283 }, 352 { 136, 0x08804, 0x02209, 0x00283 }, 353 { 140, 0x08804, 0x0220a, 0x00283 }, 354 355 { 149, 0x08808, 0x02429, 0x00281 }, 356 { 153, 0x08808, 0x0242b, 0x00281 }, 357 { 157, 0x08808, 0x0242d, 0x00281 }, 358 { 161, 0x08808, 0x0242f, 0x00281 } 359 }; 360 361 static const uint8_t ural_chan_5ghz[] = 362 { 36, 40, 44, 48, 52, 56, 60, 64, 363 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 364 149, 153, 157, 161 }; 365 366 static const struct usb_config ural_config[URAL_N_TRANSFER] = { 367 [URAL_BULK_WR] = { 368 .type = UE_BULK, 369 .endpoint = UE_ADDR_ANY, 370 .direction = UE_DIR_OUT, 371 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 372 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 373 .callback = ural_bulk_write_callback, 374 .timeout = 5000, /* ms */ 375 }, 376 [URAL_BULK_RD] = { 377 .type = UE_BULK, 378 .endpoint = UE_ADDR_ANY, 379 .direction = UE_DIR_IN, 380 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 381 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 382 .callback = ural_bulk_read_callback, 383 }, 384 }; 385 386 static device_probe_t ural_match; 387 static device_attach_t ural_attach; 388 static device_detach_t ural_detach; 389 390 static device_method_t ural_methods[] = { 391 /* Device interface */ 392 DEVMETHOD(device_probe, ural_match), 393 DEVMETHOD(device_attach, ural_attach), 394 DEVMETHOD(device_detach, ural_detach), 395 DEVMETHOD_END 396 }; 397 398 static driver_t ural_driver = { 399 .name = "ural", 400 .methods = ural_methods, 401 .size = sizeof(struct ural_softc), 402 }; 403 404 DRIVER_MODULE(ural, uhub, ural_driver, NULL, NULL); 405 MODULE_DEPEND(ural, usb, 1, 1, 1); 406 MODULE_DEPEND(ural, wlan, 1, 1, 1); 407 MODULE_VERSION(ural, 1); 408 USB_PNP_HOST_INFO(ural_devs); 409 410 static int 411 ural_match(device_t self) 412 { 413 struct usb_attach_arg *uaa = device_get_ivars(self); 414 415 if (uaa->usb_mode != USB_MODE_HOST) 416 return (ENXIO); 417 if (uaa->info.bConfigIndex != 0) 418 return (ENXIO); 419 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 420 return (ENXIO); 421 422 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 423 } 424 425 static int 426 ural_attach(device_t self) 427 { 428 struct usb_attach_arg *uaa = device_get_ivars(self); 429 struct ural_softc *sc = device_get_softc(self); 430 struct ieee80211com *ic = &sc->sc_ic; 431 uint8_t iface_index; 432 int error; 433 434 device_set_usb_desc(self); 435 sc->sc_udev = uaa->device; 436 sc->sc_dev = self; 437 438 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 439 MTX_NETWORK_LOCK, MTX_DEF); 440 mbufq_init(&sc->sc_snd, ifqmaxlen); 441 442 iface_index = RAL_IFACE_INDEX; 443 error = usbd_transfer_setup(uaa->device, 444 &iface_index, sc->sc_xfer, ural_config, 445 URAL_N_TRANSFER, sc, &sc->sc_mtx); 446 if (error) { 447 device_printf(self, "could not allocate USB transfers, " 448 "err=%s\n", usbd_errstr(error)); 449 goto detach; 450 } 451 452 RAL_LOCK(sc); 453 /* retrieve RT2570 rev. no */ 454 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 455 456 /* retrieve MAC address and various other things from EEPROM */ 457 ural_read_eeprom(sc); 458 RAL_UNLOCK(sc); 459 460 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 461 sc->asic_rev, ural_get_rf(sc->rf_rev)); 462 463 ic->ic_softc = sc; 464 ic->ic_name = device_get_nameunit(self); 465 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 466 467 /* set device capabilities */ 468 ic->ic_caps = 469 IEEE80211_C_STA /* station mode supported */ 470 | IEEE80211_C_IBSS /* IBSS mode supported */ 471 | IEEE80211_C_MONITOR /* monitor mode supported */ 472 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 473 | IEEE80211_C_TXPMGT /* tx power management */ 474 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 475 | IEEE80211_C_SHSLOT /* short slot time supported */ 476 | IEEE80211_C_BGSCAN /* bg scanning supported */ 477 | IEEE80211_C_WPA /* 802.11i */ 478 ; 479 480 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 481 ic->ic_channels); 482 483 ieee80211_ifattach(ic); 484 ic->ic_update_promisc = ural_update_promisc; 485 ic->ic_raw_xmit = ural_raw_xmit; 486 ic->ic_scan_start = ural_scan_start; 487 ic->ic_scan_end = ural_scan_end; 488 ic->ic_getradiocaps = ural_getradiocaps; 489 ic->ic_set_channel = ural_set_channel; 490 ic->ic_parent = ural_parent; 491 ic->ic_transmit = ural_transmit; 492 ic->ic_vap_create = ural_vap_create; 493 ic->ic_vap_delete = ural_vap_delete; 494 495 ieee80211_radiotap_attach(ic, 496 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 497 RAL_TX_RADIOTAP_PRESENT, 498 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 499 RAL_RX_RADIOTAP_PRESENT); 500 501 if (bootverbose) 502 ieee80211_announce(ic); 503 504 return (0); 505 506 detach: 507 ural_detach(self); 508 return (ENXIO); /* failure */ 509 } 510 511 static int 512 ural_detach(device_t self) 513 { 514 struct ural_softc *sc = device_get_softc(self); 515 struct ieee80211com *ic = &sc->sc_ic; 516 517 /* prevent further ioctls */ 518 RAL_LOCK(sc); 519 sc->sc_detached = 1; 520 RAL_UNLOCK(sc); 521 522 /* stop all USB transfers */ 523 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 524 525 /* free TX list, if any */ 526 RAL_LOCK(sc); 527 ural_unsetup_tx_list(sc); 528 RAL_UNLOCK(sc); 529 530 if (ic->ic_softc == sc) 531 ieee80211_ifdetach(ic); 532 mbufq_drain(&sc->sc_snd); 533 mtx_destroy(&sc->sc_mtx); 534 535 return (0); 536 } 537 538 static usb_error_t 539 ural_do_request(struct ural_softc *sc, 540 struct usb_device_request *req, void *data) 541 { 542 usb_error_t err; 543 int ntries = 10; 544 545 while (ntries--) { 546 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 547 req, data, 0, NULL, 250 /* ms */); 548 if (err == 0) 549 break; 550 551 DPRINTFN(1, "Control request failed, %s (retrying)\n", 552 usbd_errstr(err)); 553 if (ural_pause(sc, hz / 100)) 554 break; 555 } 556 return (err); 557 } 558 559 static struct ieee80211vap * 560 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 561 enum ieee80211_opmode opmode, int flags, 562 const uint8_t bssid[IEEE80211_ADDR_LEN], 563 const uint8_t mac[IEEE80211_ADDR_LEN]) 564 { 565 struct ural_softc *sc = ic->ic_softc; 566 struct ural_vap *uvp; 567 struct ieee80211vap *vap; 568 569 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 570 return NULL; 571 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO); 572 vap = &uvp->vap; 573 /* enable s/w bmiss handling for sta mode */ 574 575 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 576 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 577 /* out of memory */ 578 free(uvp, M_80211_VAP); 579 return (NULL); 580 } 581 582 /* override state transition machine */ 583 uvp->newstate = vap->iv_newstate; 584 vap->iv_newstate = ural_newstate; 585 586 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 587 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 588 ieee80211_ratectl_init(vap); 589 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 590 591 /* complete setup */ 592 ieee80211_vap_attach(vap, ieee80211_media_change, 593 ieee80211_media_status, mac); 594 ic->ic_opmode = opmode; 595 return vap; 596 } 597 598 static void 599 ural_vap_delete(struct ieee80211vap *vap) 600 { 601 struct ural_vap *uvp = URAL_VAP(vap); 602 struct ieee80211com *ic = vap->iv_ic; 603 604 usb_callout_drain(&uvp->ratectl_ch); 605 ieee80211_draintask(ic, &uvp->ratectl_task); 606 ieee80211_ratectl_deinit(vap); 607 ieee80211_vap_detach(vap); 608 free(uvp, M_80211_VAP); 609 } 610 611 static void 612 ural_tx_free(struct ural_tx_data *data, int txerr) 613 { 614 struct ural_softc *sc = data->sc; 615 616 if (data->m != NULL) { 617 ieee80211_tx_complete(data->ni, data->m, txerr); 618 data->m = NULL; 619 data->ni = NULL; 620 } 621 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 622 sc->tx_nfree++; 623 } 624 625 static void 626 ural_setup_tx_list(struct ural_softc *sc) 627 { 628 struct ural_tx_data *data; 629 int i; 630 631 sc->tx_nfree = 0; 632 STAILQ_INIT(&sc->tx_q); 633 STAILQ_INIT(&sc->tx_free); 634 635 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 636 data = &sc->tx_data[i]; 637 638 data->sc = sc; 639 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 640 sc->tx_nfree++; 641 } 642 } 643 644 static void 645 ural_unsetup_tx_list(struct ural_softc *sc) 646 { 647 struct ural_tx_data *data; 648 int i; 649 650 /* make sure any subsequent use of the queues will fail */ 651 sc->tx_nfree = 0; 652 STAILQ_INIT(&sc->tx_q); 653 STAILQ_INIT(&sc->tx_free); 654 655 /* free up all node references and mbufs */ 656 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 657 data = &sc->tx_data[i]; 658 659 if (data->m != NULL) { 660 m_freem(data->m); 661 data->m = NULL; 662 } 663 if (data->ni != NULL) { 664 ieee80211_free_node(data->ni); 665 data->ni = NULL; 666 } 667 } 668 } 669 670 static int 671 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 672 { 673 struct ural_vap *uvp = URAL_VAP(vap); 674 struct ieee80211com *ic = vap->iv_ic; 675 struct ural_softc *sc = ic->ic_softc; 676 const struct ieee80211_txparam *tp; 677 struct ieee80211_node *ni; 678 struct mbuf *m; 679 680 DPRINTF("%s -> %s\n", 681 ieee80211_state_name[vap->iv_state], 682 ieee80211_state_name[nstate]); 683 684 IEEE80211_UNLOCK(ic); 685 RAL_LOCK(sc); 686 usb_callout_stop(&uvp->ratectl_ch); 687 688 switch (nstate) { 689 case IEEE80211_S_INIT: 690 if (vap->iv_state == IEEE80211_S_RUN) { 691 /* abort TSF synchronization */ 692 ural_write(sc, RAL_TXRX_CSR19, 0); 693 694 /* force tx led to stop blinking */ 695 ural_write(sc, RAL_MAC_CSR20, 0); 696 } 697 break; 698 699 case IEEE80211_S_RUN: 700 ni = ieee80211_ref_node(vap->iv_bss); 701 702 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 703 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) 704 goto fail; 705 706 ural_update_slot(sc); 707 ural_set_txpreamble(sc); 708 ural_set_basicrates(sc, ic->ic_bsschan); 709 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 710 ural_set_bssid(sc, sc->sc_bssid); 711 } 712 713 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 714 vap->iv_opmode == IEEE80211_M_IBSS) { 715 m = ieee80211_beacon_alloc(ni); 716 if (m == NULL) { 717 device_printf(sc->sc_dev, 718 "could not allocate beacon\n"); 719 goto fail; 720 } 721 ieee80211_ref_node(ni); 722 if (ural_tx_bcn(sc, m, ni) != 0) { 723 device_printf(sc->sc_dev, 724 "could not send beacon\n"); 725 goto fail; 726 } 727 } 728 729 /* make tx led blink on tx (controlled by ASIC) */ 730 ural_write(sc, RAL_MAC_CSR20, 1); 731 732 if (vap->iv_opmode != IEEE80211_M_MONITOR) 733 ural_enable_tsf_sync(sc); 734 else 735 ural_enable_tsf(sc); 736 737 /* enable automatic rate adaptation */ 738 /* XXX should use ic_bsschan but not valid until after newstate call below */ 739 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 740 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 741 ural_ratectl_start(sc, ni); 742 ieee80211_free_node(ni); 743 break; 744 745 default: 746 break; 747 } 748 RAL_UNLOCK(sc); 749 IEEE80211_LOCK(ic); 750 return (uvp->newstate(vap, nstate, arg)); 751 752 fail: 753 RAL_UNLOCK(sc); 754 IEEE80211_LOCK(ic); 755 ieee80211_free_node(ni); 756 return (-1); 757 } 758 759 static void 760 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 761 { 762 struct ural_softc *sc = usbd_xfer_softc(xfer); 763 struct ieee80211vap *vap; 764 struct ural_tx_data *data; 765 struct mbuf *m; 766 struct usb_page_cache *pc; 767 int len; 768 769 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 770 771 switch (USB_GET_STATE(xfer)) { 772 case USB_ST_TRANSFERRED: 773 DPRINTFN(11, "transfer complete, %d bytes\n", len); 774 775 /* free resources */ 776 data = usbd_xfer_get_priv(xfer); 777 ural_tx_free(data, 0); 778 usbd_xfer_set_priv(xfer, NULL); 779 780 /* FALLTHROUGH */ 781 case USB_ST_SETUP: 782 tr_setup: 783 data = STAILQ_FIRST(&sc->tx_q); 784 if (data) { 785 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 786 m = data->m; 787 788 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 789 DPRINTFN(0, "data overflow, %u bytes\n", 790 m->m_pkthdr.len); 791 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 792 } 793 pc = usbd_xfer_get_frame(xfer, 0); 794 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 795 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 796 m->m_pkthdr.len); 797 798 vap = data->ni->ni_vap; 799 if (ieee80211_radiotap_active_vap(vap)) { 800 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 801 802 tap->wt_flags = 0; 803 tap->wt_rate = data->rate; 804 tap->wt_antenna = sc->tx_ant; 805 806 ieee80211_radiotap_tx(vap, m); 807 } 808 809 /* xfer length needs to be a multiple of two! */ 810 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 811 if ((len % 64) == 0) 812 len += 2; 813 814 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 815 m->m_pkthdr.len, len); 816 817 usbd_xfer_set_frame_len(xfer, 0, len); 818 usbd_xfer_set_priv(xfer, data); 819 820 usbd_transfer_submit(xfer); 821 } 822 ural_start(sc); 823 break; 824 825 default: /* Error */ 826 DPRINTFN(11, "transfer error, %s\n", 827 usbd_errstr(error)); 828 829 data = usbd_xfer_get_priv(xfer); 830 if (data != NULL) { 831 ural_tx_free(data, error); 832 usbd_xfer_set_priv(xfer, NULL); 833 } 834 835 if (error == USB_ERR_STALLED) { 836 /* try to clear stall first */ 837 usbd_xfer_set_stall(xfer); 838 goto tr_setup; 839 } 840 if (error == USB_ERR_TIMEOUT) 841 device_printf(sc->sc_dev, "device timeout\n"); 842 break; 843 } 844 } 845 846 static void 847 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 848 { 849 struct ural_softc *sc = usbd_xfer_softc(xfer); 850 struct ieee80211com *ic = &sc->sc_ic; 851 struct ieee80211_node *ni; 852 struct epoch_tracker et; 853 struct mbuf *m = NULL; 854 struct usb_page_cache *pc; 855 uint32_t flags; 856 int8_t rssi = 0, nf = 0; 857 int len; 858 859 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 860 861 switch (USB_GET_STATE(xfer)) { 862 case USB_ST_TRANSFERRED: 863 864 DPRINTFN(15, "rx done, actlen=%d\n", len); 865 866 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 867 DPRINTF("%s: xfer too short %d\n", 868 device_get_nameunit(sc->sc_dev), len); 869 counter_u64_add(ic->ic_ierrors, 1); 870 goto tr_setup; 871 } 872 873 len -= RAL_RX_DESC_SIZE; 874 /* rx descriptor is located at the end */ 875 pc = usbd_xfer_get_frame(xfer, 0); 876 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 877 878 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 879 nf = RAL_NOISE_FLOOR; 880 flags = le32toh(sc->sc_rx_desc.flags); 881 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 882 /* 883 * This should not happen since we did not 884 * request to receive those frames when we 885 * filled RAL_TXRX_CSR2: 886 */ 887 DPRINTFN(5, "PHY or CRC error\n"); 888 counter_u64_add(ic->ic_ierrors, 1); 889 goto tr_setup; 890 } 891 892 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 893 if (m == NULL) { 894 DPRINTF("could not allocate mbuf\n"); 895 counter_u64_add(ic->ic_ierrors, 1); 896 goto tr_setup; 897 } 898 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 899 900 /* finalize mbuf */ 901 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 902 903 if (ieee80211_radiotap_active(ic)) { 904 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 905 906 /* XXX set once */ 907 tap->wr_flags = 0; 908 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 909 (flags & RAL_RX_OFDM) ? 910 IEEE80211_T_OFDM : IEEE80211_T_CCK); 911 tap->wr_antenna = sc->rx_ant; 912 tap->wr_antsignal = nf + rssi; 913 tap->wr_antnoise = nf; 914 } 915 /* Strip trailing 802.11 MAC FCS. */ 916 m_adj(m, -IEEE80211_CRC_LEN); 917 918 /* FALLTHROUGH */ 919 case USB_ST_SETUP: 920 tr_setup: 921 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 922 usbd_transfer_submit(xfer); 923 924 /* 925 * At the end of a USB callback it is always safe to unlock 926 * the private mutex of a device! That is why we do the 927 * "ieee80211_input" here, and not some lines up! 928 */ 929 RAL_UNLOCK(sc); 930 if (m) { 931 ni = ieee80211_find_rxnode(ic, 932 mtod(m, struct ieee80211_frame_min *)); 933 NET_EPOCH_ENTER(et); 934 if (ni != NULL) { 935 (void) ieee80211_input(ni, m, rssi, nf); 936 ieee80211_free_node(ni); 937 } else 938 (void) ieee80211_input_all(ic, m, rssi, nf); 939 NET_EPOCH_EXIT(et); 940 } 941 RAL_LOCK(sc); 942 ural_start(sc); 943 return; 944 945 default: /* Error */ 946 if (error != USB_ERR_CANCELLED) { 947 /* try to clear stall first */ 948 usbd_xfer_set_stall(xfer); 949 goto tr_setup; 950 } 951 return; 952 } 953 } 954 955 static uint8_t 956 ural_plcp_signal(int rate) 957 { 958 switch (rate) { 959 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 960 case 12: return 0xb; 961 case 18: return 0xf; 962 case 24: return 0xa; 963 case 36: return 0xe; 964 case 48: return 0x9; 965 case 72: return 0xd; 966 case 96: return 0x8; 967 case 108: return 0xc; 968 969 /* CCK rates (NB: not IEEE std, device-specific) */ 970 case 2: return 0x0; 971 case 4: return 0x1; 972 case 11: return 0x2; 973 case 22: return 0x3; 974 } 975 return 0xff; /* XXX unsupported/unknown rate */ 976 } 977 978 static void 979 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 980 uint32_t flags, int len, int rate) 981 { 982 struct ieee80211com *ic = &sc->sc_ic; 983 uint16_t plcp_length; 984 int remainder; 985 986 desc->flags = htole32(flags); 987 desc->flags |= htole32(RAL_TX_NEWSEQ); 988 desc->flags |= htole32(len << 16); 989 990 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 991 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 992 993 /* setup PLCP fields */ 994 desc->plcp_signal = ural_plcp_signal(rate); 995 desc->plcp_service = 4; 996 997 len += IEEE80211_CRC_LEN; 998 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 999 desc->flags |= htole32(RAL_TX_OFDM); 1000 1001 plcp_length = len & 0xfff; 1002 desc->plcp_length_hi = plcp_length >> 6; 1003 desc->plcp_length_lo = plcp_length & 0x3f; 1004 } else { 1005 if (rate == 0) 1006 rate = 2; /* avoid division by zero */ 1007 plcp_length = howmany(16 * len, rate); 1008 if (rate == 22) { 1009 remainder = (16 * len) % 22; 1010 if (remainder != 0 && remainder < 7) 1011 desc->plcp_service |= RAL_PLCP_LENGEXT; 1012 } 1013 desc->plcp_length_hi = plcp_length >> 8; 1014 desc->plcp_length_lo = plcp_length & 0xff; 1015 1016 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1017 desc->plcp_signal |= 0x08; 1018 } 1019 1020 desc->iv = 0; 1021 desc->eiv = 0; 1022 } 1023 1024 #define RAL_TX_TIMEOUT 5000 1025 1026 static int 1027 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1028 { 1029 struct ieee80211vap *vap = ni->ni_vap; 1030 struct ieee80211com *ic = ni->ni_ic; 1031 const struct ieee80211_txparam *tp; 1032 struct ural_tx_data *data; 1033 1034 if (sc->tx_nfree == 0) { 1035 m_freem(m0); 1036 ieee80211_free_node(ni); 1037 return (EIO); 1038 } 1039 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1040 m_freem(m0); 1041 ieee80211_free_node(ni); 1042 return (ENXIO); 1043 } 1044 data = STAILQ_FIRST(&sc->tx_free); 1045 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1046 sc->tx_nfree--; 1047 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1048 1049 data->m = m0; 1050 data->ni = ni; 1051 data->rate = tp->mgmtrate; 1052 1053 ural_setup_tx_desc(sc, &data->desc, 1054 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1055 tp->mgmtrate); 1056 1057 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1058 m0->m_pkthdr.len, tp->mgmtrate); 1059 1060 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1061 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1062 1063 return (0); 1064 } 1065 1066 static int 1067 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1068 { 1069 const struct ieee80211_txparam *tp = ni->ni_txparms; 1070 struct ieee80211com *ic = ni->ni_ic; 1071 struct ural_tx_data *data; 1072 struct ieee80211_frame *wh; 1073 struct ieee80211_key *k; 1074 uint32_t flags; 1075 uint16_t dur; 1076 1077 RAL_LOCK_ASSERT(sc, MA_OWNED); 1078 1079 data = STAILQ_FIRST(&sc->tx_free); 1080 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1081 sc->tx_nfree--; 1082 1083 wh = mtod(m0, struct ieee80211_frame *); 1084 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1085 k = ieee80211_crypto_encap(ni, m0); 1086 if (k == NULL) { 1087 m_freem(m0); 1088 return ENOBUFS; 1089 } 1090 wh = mtod(m0, struct ieee80211_frame *); 1091 } 1092 1093 data->m = m0; 1094 data->ni = ni; 1095 data->rate = tp->mgmtrate; 1096 1097 flags = 0; 1098 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1099 flags |= RAL_TX_ACK; 1100 1101 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1102 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1103 USETW(wh->i_dur, dur); 1104 1105 /* tell hardware to add timestamp for probe responses */ 1106 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1107 IEEE80211_FC0_TYPE_MGT && 1108 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1109 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1110 flags |= RAL_TX_TIMESTAMP; 1111 } 1112 1113 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1114 1115 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1116 m0->m_pkthdr.len, tp->mgmtrate); 1117 1118 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1119 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1120 1121 return 0; 1122 } 1123 1124 static int 1125 ural_sendprot(struct ural_softc *sc, 1126 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1127 { 1128 struct ieee80211com *ic = ni->ni_ic; 1129 struct ural_tx_data *data; 1130 struct mbuf *mprot; 1131 int protrate, flags; 1132 1133 mprot = ieee80211_alloc_prot(ni, m, rate, prot); 1134 if (mprot == NULL) { 1135 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 1136 device_printf(sc->sc_dev, 1137 "could not allocate mbuf for protection mode %d\n", prot); 1138 return ENOBUFS; 1139 } 1140 1141 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1142 flags = RAL_TX_RETRY(7); 1143 if (prot == IEEE80211_PROT_RTSCTS) 1144 flags |= RAL_TX_ACK; 1145 1146 data = STAILQ_FIRST(&sc->tx_free); 1147 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1148 sc->tx_nfree--; 1149 1150 data->m = mprot; 1151 data->ni = ieee80211_ref_node(ni); 1152 data->rate = protrate; 1153 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1154 1155 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1156 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1157 1158 return 0; 1159 } 1160 1161 static int 1162 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1163 const struct ieee80211_bpf_params *params) 1164 { 1165 struct ieee80211com *ic = ni->ni_ic; 1166 struct ural_tx_data *data; 1167 uint32_t flags; 1168 int error; 1169 int rate; 1170 1171 RAL_LOCK_ASSERT(sc, MA_OWNED); 1172 KASSERT(params != NULL, ("no raw xmit params")); 1173 1174 rate = params->ibp_rate0; 1175 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1176 m_freem(m0); 1177 return EINVAL; 1178 } 1179 flags = 0; 1180 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1181 flags |= RAL_TX_ACK; 1182 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1183 error = ural_sendprot(sc, m0, ni, 1184 params->ibp_flags & IEEE80211_BPF_RTS ? 1185 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1186 rate); 1187 if (error || sc->tx_nfree == 0) { 1188 m_freem(m0); 1189 return ENOBUFS; 1190 } 1191 flags |= RAL_TX_IFS_SIFS; 1192 } 1193 1194 data = STAILQ_FIRST(&sc->tx_free); 1195 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1196 sc->tx_nfree--; 1197 1198 data->m = m0; 1199 data->ni = ni; 1200 data->rate = rate; 1201 1202 /* XXX need to setup descriptor ourself */ 1203 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1204 1205 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1206 m0->m_pkthdr.len, rate); 1207 1208 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1209 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1210 1211 return 0; 1212 } 1213 1214 static int 1215 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1216 { 1217 struct ieee80211vap *vap = ni->ni_vap; 1218 struct ieee80211com *ic = ni->ni_ic; 1219 struct ural_tx_data *data; 1220 struct ieee80211_frame *wh; 1221 const struct ieee80211_txparam *tp = ni->ni_txparms; 1222 struct ieee80211_key *k; 1223 uint32_t flags = 0; 1224 uint16_t dur; 1225 int error, rate; 1226 1227 RAL_LOCK_ASSERT(sc, MA_OWNED); 1228 1229 wh = mtod(m0, struct ieee80211_frame *); 1230 1231 if (m0->m_flags & M_EAPOL) 1232 rate = tp->mgmtrate; 1233 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1234 rate = tp->mcastrate; 1235 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1236 rate = tp->ucastrate; 1237 else { 1238 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1239 rate = ni->ni_txrate; 1240 } 1241 1242 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1243 k = ieee80211_crypto_encap(ni, m0); 1244 if (k == NULL) { 1245 m_freem(m0); 1246 return ENOBUFS; 1247 } 1248 /* packet header may have moved, reset our local pointer */ 1249 wh = mtod(m0, struct ieee80211_frame *); 1250 } 1251 1252 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1253 int prot = IEEE80211_PROT_NONE; 1254 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1255 prot = IEEE80211_PROT_RTSCTS; 1256 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1257 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1258 prot = ic->ic_protmode; 1259 if (prot != IEEE80211_PROT_NONE) { 1260 error = ural_sendprot(sc, m0, ni, prot, rate); 1261 if (error || sc->tx_nfree == 0) { 1262 m_freem(m0); 1263 return ENOBUFS; 1264 } 1265 flags |= RAL_TX_IFS_SIFS; 1266 } 1267 } 1268 1269 data = STAILQ_FIRST(&sc->tx_free); 1270 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1271 sc->tx_nfree--; 1272 1273 data->m = m0; 1274 data->ni = ni; 1275 data->rate = rate; 1276 1277 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1278 flags |= RAL_TX_ACK; 1279 flags |= RAL_TX_RETRY(7); 1280 1281 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1282 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1283 USETW(wh->i_dur, dur); 1284 } 1285 1286 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1287 1288 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1289 m0->m_pkthdr.len, rate); 1290 1291 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1292 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1293 1294 return 0; 1295 } 1296 1297 static int 1298 ural_transmit(struct ieee80211com *ic, struct mbuf *m) 1299 { 1300 struct ural_softc *sc = ic->ic_softc; 1301 int error; 1302 1303 RAL_LOCK(sc); 1304 if (!sc->sc_running) { 1305 RAL_UNLOCK(sc); 1306 return (ENXIO); 1307 } 1308 error = mbufq_enqueue(&sc->sc_snd, m); 1309 if (error) { 1310 RAL_UNLOCK(sc); 1311 return (error); 1312 } 1313 ural_start(sc); 1314 RAL_UNLOCK(sc); 1315 1316 return (0); 1317 } 1318 1319 static void 1320 ural_start(struct ural_softc *sc) 1321 { 1322 struct ieee80211_node *ni; 1323 struct mbuf *m; 1324 1325 RAL_LOCK_ASSERT(sc, MA_OWNED); 1326 1327 if (sc->sc_running == 0) 1328 return; 1329 1330 while (sc->tx_nfree >= RAL_TX_MINFREE && 1331 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1332 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1333 if (ural_tx_data(sc, m, ni) != 0) { 1334 if_inc_counter(ni->ni_vap->iv_ifp, 1335 IFCOUNTER_OERRORS, 1); 1336 ieee80211_free_node(ni); 1337 break; 1338 } 1339 } 1340 } 1341 1342 static void 1343 ural_parent(struct ieee80211com *ic) 1344 { 1345 struct ural_softc *sc = ic->ic_softc; 1346 int startall = 0; 1347 1348 RAL_LOCK(sc); 1349 if (sc->sc_detached) { 1350 RAL_UNLOCK(sc); 1351 return; 1352 } 1353 if (ic->ic_nrunning > 0) { 1354 if (sc->sc_running == 0) { 1355 ural_init(sc); 1356 startall = 1; 1357 } else 1358 ural_setpromisc(sc); 1359 } else if (sc->sc_running) 1360 ural_stop(sc); 1361 RAL_UNLOCK(sc); 1362 if (startall) 1363 ieee80211_start_all(ic); 1364 } 1365 1366 static void 1367 ural_set_testmode(struct ural_softc *sc) 1368 { 1369 struct usb_device_request req; 1370 usb_error_t error; 1371 1372 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1373 req.bRequest = RAL_VENDOR_REQUEST; 1374 USETW(req.wValue, 4); 1375 USETW(req.wIndex, 1); 1376 USETW(req.wLength, 0); 1377 1378 error = ural_do_request(sc, &req, NULL); 1379 if (error != 0) { 1380 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1381 usbd_errstr(error)); 1382 } 1383 } 1384 1385 static void 1386 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1387 { 1388 struct usb_device_request req; 1389 usb_error_t error; 1390 1391 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1392 req.bRequest = RAL_READ_EEPROM; 1393 USETW(req.wValue, 0); 1394 USETW(req.wIndex, addr); 1395 USETW(req.wLength, len); 1396 1397 error = ural_do_request(sc, &req, buf); 1398 if (error != 0) { 1399 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1400 usbd_errstr(error)); 1401 } 1402 } 1403 1404 static uint16_t 1405 ural_read(struct ural_softc *sc, uint16_t reg) 1406 { 1407 struct usb_device_request req; 1408 usb_error_t error; 1409 uint16_t val; 1410 1411 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1412 req.bRequest = RAL_READ_MAC; 1413 USETW(req.wValue, 0); 1414 USETW(req.wIndex, reg); 1415 USETW(req.wLength, sizeof (uint16_t)); 1416 1417 error = ural_do_request(sc, &req, &val); 1418 if (error != 0) { 1419 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1420 usbd_errstr(error)); 1421 return 0; 1422 } 1423 1424 return le16toh(val); 1425 } 1426 1427 static void 1428 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1429 { 1430 struct usb_device_request req; 1431 usb_error_t error; 1432 1433 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1434 req.bRequest = RAL_READ_MULTI_MAC; 1435 USETW(req.wValue, 0); 1436 USETW(req.wIndex, reg); 1437 USETW(req.wLength, len); 1438 1439 error = ural_do_request(sc, &req, buf); 1440 if (error != 0) { 1441 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1442 usbd_errstr(error)); 1443 } 1444 } 1445 1446 static void 1447 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1448 { 1449 struct usb_device_request req; 1450 usb_error_t error; 1451 1452 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1453 req.bRequest = RAL_WRITE_MAC; 1454 USETW(req.wValue, val); 1455 USETW(req.wIndex, reg); 1456 USETW(req.wLength, 0); 1457 1458 error = ural_do_request(sc, &req, NULL); 1459 if (error != 0) { 1460 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1461 usbd_errstr(error)); 1462 } 1463 } 1464 1465 static void 1466 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1467 { 1468 struct usb_device_request req; 1469 usb_error_t error; 1470 1471 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1472 req.bRequest = RAL_WRITE_MULTI_MAC; 1473 USETW(req.wValue, 0); 1474 USETW(req.wIndex, reg); 1475 USETW(req.wLength, len); 1476 1477 error = ural_do_request(sc, &req, buf); 1478 if (error != 0) { 1479 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1480 usbd_errstr(error)); 1481 } 1482 } 1483 1484 static void 1485 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1486 { 1487 uint16_t tmp; 1488 int ntries; 1489 1490 for (ntries = 0; ntries < 100; ntries++) { 1491 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1492 break; 1493 if (ural_pause(sc, hz / 100)) 1494 break; 1495 } 1496 if (ntries == 100) { 1497 device_printf(sc->sc_dev, "could not write to BBP\n"); 1498 return; 1499 } 1500 1501 tmp = reg << 8 | val; 1502 ural_write(sc, RAL_PHY_CSR7, tmp); 1503 } 1504 1505 static uint8_t 1506 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1507 { 1508 uint16_t val; 1509 int ntries; 1510 1511 val = RAL_BBP_WRITE | reg << 8; 1512 ural_write(sc, RAL_PHY_CSR7, val); 1513 1514 for (ntries = 0; ntries < 100; ntries++) { 1515 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1516 break; 1517 if (ural_pause(sc, hz / 100)) 1518 break; 1519 } 1520 if (ntries == 100) { 1521 device_printf(sc->sc_dev, "could not read BBP\n"); 1522 return 0; 1523 } 1524 1525 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1526 } 1527 1528 static void 1529 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1530 { 1531 uint32_t tmp; 1532 int ntries; 1533 1534 for (ntries = 0; ntries < 100; ntries++) { 1535 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1536 break; 1537 if (ural_pause(sc, hz / 100)) 1538 break; 1539 } 1540 if (ntries == 100) { 1541 device_printf(sc->sc_dev, "could not write to RF\n"); 1542 return; 1543 } 1544 1545 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1546 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1547 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1548 1549 /* remember last written value in sc */ 1550 sc->rf_regs[reg] = val; 1551 1552 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1553 } 1554 1555 static void 1556 ural_scan_start(struct ieee80211com *ic) 1557 { 1558 struct ural_softc *sc = ic->ic_softc; 1559 1560 RAL_LOCK(sc); 1561 ural_write(sc, RAL_TXRX_CSR19, 0); 1562 ural_set_bssid(sc, ieee80211broadcastaddr); 1563 RAL_UNLOCK(sc); 1564 } 1565 1566 static void 1567 ural_scan_end(struct ieee80211com *ic) 1568 { 1569 struct ural_softc *sc = ic->ic_softc; 1570 1571 RAL_LOCK(sc); 1572 ural_enable_tsf_sync(sc); 1573 ural_set_bssid(sc, sc->sc_bssid); 1574 RAL_UNLOCK(sc); 1575 1576 } 1577 1578 static void 1579 ural_getradiocaps(struct ieee80211com *ic, 1580 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1581 { 1582 struct ural_softc *sc = ic->ic_softc; 1583 uint8_t bands[IEEE80211_MODE_BYTES]; 1584 1585 memset(bands, 0, sizeof(bands)); 1586 setbit(bands, IEEE80211_MODE_11B); 1587 setbit(bands, IEEE80211_MODE_11G); 1588 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1589 1590 if (sc->rf_rev == RAL_RF_5222) { 1591 setbit(bands, IEEE80211_MODE_11A); 1592 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 1593 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0); 1594 } 1595 } 1596 1597 static void 1598 ural_set_channel(struct ieee80211com *ic) 1599 { 1600 struct ural_softc *sc = ic->ic_softc; 1601 1602 RAL_LOCK(sc); 1603 ural_set_chan(sc, ic->ic_curchan); 1604 RAL_UNLOCK(sc); 1605 } 1606 1607 static void 1608 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1609 { 1610 struct ieee80211com *ic = &sc->sc_ic; 1611 uint8_t power, tmp; 1612 int i, chan; 1613 1614 chan = ieee80211_chan2ieee(ic, c); 1615 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1616 return; 1617 1618 if (IEEE80211_IS_CHAN_2GHZ(c)) 1619 power = min(sc->txpow[chan - 1], 31); 1620 else 1621 power = 31; 1622 1623 /* adjust txpower using ifconfig settings */ 1624 power -= (100 - ic->ic_txpowlimit) / 8; 1625 1626 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1627 1628 switch (sc->rf_rev) { 1629 case RAL_RF_2522: 1630 ural_rf_write(sc, RAL_RF1, 0x00814); 1631 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1632 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1633 break; 1634 1635 case RAL_RF_2523: 1636 ural_rf_write(sc, RAL_RF1, 0x08804); 1637 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1638 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1639 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1640 break; 1641 1642 case RAL_RF_2524: 1643 ural_rf_write(sc, RAL_RF1, 0x0c808); 1644 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1645 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1646 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1647 break; 1648 1649 case RAL_RF_2525: 1650 ural_rf_write(sc, RAL_RF1, 0x08808); 1651 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1652 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1653 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1654 1655 ural_rf_write(sc, RAL_RF1, 0x08808); 1656 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1657 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1658 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1659 break; 1660 1661 case RAL_RF_2525E: 1662 ural_rf_write(sc, RAL_RF1, 0x08808); 1663 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1664 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1665 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1666 break; 1667 1668 case RAL_RF_2526: 1669 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1670 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1671 ural_rf_write(sc, RAL_RF1, 0x08804); 1672 1673 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1674 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1675 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1676 break; 1677 1678 /* dual-band RF */ 1679 case RAL_RF_5222: 1680 for (i = 0; ural_rf5222[i].chan != chan; i++); 1681 1682 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1683 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1684 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1685 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1686 break; 1687 } 1688 1689 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1690 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1691 /* set Japan filter bit for channel 14 */ 1692 tmp = ural_bbp_read(sc, 70); 1693 1694 tmp &= ~RAL_JAPAN_FILTER; 1695 if (chan == 14) 1696 tmp |= RAL_JAPAN_FILTER; 1697 1698 ural_bbp_write(sc, 70, tmp); 1699 1700 /* clear CRC errors */ 1701 ural_read(sc, RAL_STA_CSR0); 1702 1703 ural_pause(sc, hz / 100); 1704 ural_disable_rf_tune(sc); 1705 } 1706 1707 /* XXX doesn't belong here */ 1708 /* update basic rate set */ 1709 ural_set_basicrates(sc, c); 1710 1711 /* give the hardware some time to do the switchover */ 1712 ural_pause(sc, hz / 100); 1713 } 1714 1715 /* 1716 * Disable RF auto-tuning. 1717 */ 1718 static void 1719 ural_disable_rf_tune(struct ural_softc *sc) 1720 { 1721 uint32_t tmp; 1722 1723 if (sc->rf_rev != RAL_RF_2523) { 1724 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1725 ural_rf_write(sc, RAL_RF1, tmp); 1726 } 1727 1728 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1729 ural_rf_write(sc, RAL_RF3, tmp); 1730 1731 DPRINTFN(2, "disabling RF autotune\n"); 1732 } 1733 1734 /* 1735 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1736 * synchronization. 1737 */ 1738 static void 1739 ural_enable_tsf_sync(struct ural_softc *sc) 1740 { 1741 struct ieee80211com *ic = &sc->sc_ic; 1742 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1743 uint16_t logcwmin, preload, tmp; 1744 1745 /* first, disable TSF synchronization */ 1746 ural_write(sc, RAL_TXRX_CSR19, 0); 1747 1748 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1749 ural_write(sc, RAL_TXRX_CSR18, tmp); 1750 1751 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1752 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1753 tmp = logcwmin << 12 | preload; 1754 ural_write(sc, RAL_TXRX_CSR20, tmp); 1755 1756 /* finally, enable TSF synchronization */ 1757 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1758 if (ic->ic_opmode == IEEE80211_M_STA) 1759 tmp |= RAL_ENABLE_TSF_SYNC(1); 1760 else 1761 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1762 ural_write(sc, RAL_TXRX_CSR19, tmp); 1763 1764 DPRINTF("enabling TSF synchronization\n"); 1765 } 1766 1767 static void 1768 ural_enable_tsf(struct ural_softc *sc) 1769 { 1770 /* first, disable TSF synchronization */ 1771 ural_write(sc, RAL_TXRX_CSR19, 0); 1772 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1773 } 1774 1775 #define RAL_RXTX_TURNAROUND 5 /* us */ 1776 static void 1777 ural_update_slot(struct ural_softc *sc) 1778 { 1779 struct ieee80211com *ic = &sc->sc_ic; 1780 uint16_t slottime, sifs, eifs; 1781 1782 slottime = IEEE80211_GET_SLOTTIME(ic); 1783 1784 /* 1785 * These settings may sound a bit inconsistent but this is what the 1786 * reference driver does. 1787 */ 1788 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1789 sifs = 16 - RAL_RXTX_TURNAROUND; 1790 eifs = 364; 1791 } else { 1792 sifs = 10 - RAL_RXTX_TURNAROUND; 1793 eifs = 64; 1794 } 1795 1796 ural_write(sc, RAL_MAC_CSR10, slottime); 1797 ural_write(sc, RAL_MAC_CSR11, sifs); 1798 ural_write(sc, RAL_MAC_CSR12, eifs); 1799 } 1800 1801 static void 1802 ural_set_txpreamble(struct ural_softc *sc) 1803 { 1804 struct ieee80211com *ic = &sc->sc_ic; 1805 uint16_t tmp; 1806 1807 tmp = ural_read(sc, RAL_TXRX_CSR10); 1808 1809 tmp &= ~RAL_SHORT_PREAMBLE; 1810 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1811 tmp |= RAL_SHORT_PREAMBLE; 1812 1813 ural_write(sc, RAL_TXRX_CSR10, tmp); 1814 } 1815 1816 static void 1817 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1818 { 1819 /* XXX wrong, take from rate set */ 1820 /* update basic rate set */ 1821 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1822 /* 11a basic rates: 6, 12, 24Mbps */ 1823 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1824 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1825 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1826 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1827 } else { 1828 /* 11b basic rates: 1, 2Mbps */ 1829 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1830 } 1831 } 1832 1833 static void 1834 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1835 { 1836 uint16_t tmp; 1837 1838 tmp = bssid[0] | bssid[1] << 8; 1839 ural_write(sc, RAL_MAC_CSR5, tmp); 1840 1841 tmp = bssid[2] | bssid[3] << 8; 1842 ural_write(sc, RAL_MAC_CSR6, tmp); 1843 1844 tmp = bssid[4] | bssid[5] << 8; 1845 ural_write(sc, RAL_MAC_CSR7, tmp); 1846 1847 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1848 } 1849 1850 static void 1851 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr) 1852 { 1853 uint16_t tmp; 1854 1855 tmp = addr[0] | addr[1] << 8; 1856 ural_write(sc, RAL_MAC_CSR2, tmp); 1857 1858 tmp = addr[2] | addr[3] << 8; 1859 ural_write(sc, RAL_MAC_CSR3, tmp); 1860 1861 tmp = addr[4] | addr[5] << 8; 1862 ural_write(sc, RAL_MAC_CSR4, tmp); 1863 1864 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1865 } 1866 1867 static void 1868 ural_setpromisc(struct ural_softc *sc) 1869 { 1870 uint32_t tmp; 1871 1872 tmp = ural_read(sc, RAL_TXRX_CSR2); 1873 1874 tmp &= ~RAL_DROP_NOT_TO_ME; 1875 if (sc->sc_ic.ic_promisc == 0) 1876 tmp |= RAL_DROP_NOT_TO_ME; 1877 1878 ural_write(sc, RAL_TXRX_CSR2, tmp); 1879 1880 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ? 1881 "entering" : "leaving"); 1882 } 1883 1884 static void 1885 ural_update_promisc(struct ieee80211com *ic) 1886 { 1887 struct ural_softc *sc = ic->ic_softc; 1888 1889 RAL_LOCK(sc); 1890 if (sc->sc_running) 1891 ural_setpromisc(sc); 1892 RAL_UNLOCK(sc); 1893 } 1894 1895 static const char * 1896 ural_get_rf(int rev) 1897 { 1898 switch (rev) { 1899 case RAL_RF_2522: return "RT2522"; 1900 case RAL_RF_2523: return "RT2523"; 1901 case RAL_RF_2524: return "RT2524"; 1902 case RAL_RF_2525: return "RT2525"; 1903 case RAL_RF_2525E: return "RT2525e"; 1904 case RAL_RF_2526: return "RT2526"; 1905 case RAL_RF_5222: return "RT5222"; 1906 default: return "unknown"; 1907 } 1908 } 1909 1910 static void 1911 ural_read_eeprom(struct ural_softc *sc) 1912 { 1913 struct ieee80211com *ic = &sc->sc_ic; 1914 uint16_t val; 1915 1916 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1917 val = le16toh(val); 1918 sc->rf_rev = (val >> 11) & 0x7; 1919 sc->hw_radio = (val >> 10) & 0x1; 1920 sc->led_mode = (val >> 6) & 0x7; 1921 sc->rx_ant = (val >> 4) & 0x3; 1922 sc->tx_ant = (val >> 2) & 0x3; 1923 sc->nb_ant = val & 0x3; 1924 1925 /* read MAC address */ 1926 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1927 1928 /* read default values for BBP registers */ 1929 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1930 1931 /* read Tx power for all b/g channels */ 1932 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1933 } 1934 1935 static int 1936 ural_bbp_init(struct ural_softc *sc) 1937 { 1938 int i, ntries; 1939 1940 /* wait for BBP to be ready */ 1941 for (ntries = 0; ntries < 100; ntries++) { 1942 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1943 break; 1944 if (ural_pause(sc, hz / 100)) 1945 break; 1946 } 1947 if (ntries == 100) { 1948 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1949 return EIO; 1950 } 1951 1952 /* initialize BBP registers to default values */ 1953 for (i = 0; i < nitems(ural_def_bbp); i++) 1954 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1955 1956 #if 0 1957 /* initialize BBP registers to values stored in EEPROM */ 1958 for (i = 0; i < 16; i++) { 1959 if (sc->bbp_prom[i].reg == 0xff) 1960 continue; 1961 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1962 } 1963 #endif 1964 1965 return 0; 1966 } 1967 1968 static void 1969 ural_set_txantenna(struct ural_softc *sc, int antenna) 1970 { 1971 uint16_t tmp; 1972 uint8_t tx; 1973 1974 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1975 if (antenna == 1) 1976 tx |= RAL_BBP_ANTA; 1977 else if (antenna == 2) 1978 tx |= RAL_BBP_ANTB; 1979 else 1980 tx |= RAL_BBP_DIVERSITY; 1981 1982 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1983 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1984 sc->rf_rev == RAL_RF_5222) 1985 tx |= RAL_BBP_FLIPIQ; 1986 1987 ural_bbp_write(sc, RAL_BBP_TX, tx); 1988 1989 /* update values in PHY_CSR5 and PHY_CSR6 */ 1990 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1991 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1992 1993 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 1994 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1995 } 1996 1997 static void 1998 ural_set_rxantenna(struct ural_softc *sc, int antenna) 1999 { 2000 uint8_t rx; 2001 2002 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2003 if (antenna == 1) 2004 rx |= RAL_BBP_ANTA; 2005 else if (antenna == 2) 2006 rx |= RAL_BBP_ANTB; 2007 else 2008 rx |= RAL_BBP_DIVERSITY; 2009 2010 /* need to force no I/Q flip for RF 2525e and 2526 */ 2011 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2012 rx &= ~RAL_BBP_FLIPIQ; 2013 2014 ural_bbp_write(sc, RAL_BBP_RX, rx); 2015 } 2016 2017 static void 2018 ural_init(struct ural_softc *sc) 2019 { 2020 struct ieee80211com *ic = &sc->sc_ic; 2021 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2022 uint16_t tmp; 2023 int i, ntries; 2024 2025 RAL_LOCK_ASSERT(sc, MA_OWNED); 2026 2027 ural_set_testmode(sc); 2028 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2029 2030 ural_stop(sc); 2031 2032 /* initialize MAC registers to default values */ 2033 for (i = 0; i < nitems(ural_def_mac); i++) 2034 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2035 2036 /* wait for BBP and RF to wake up (this can take a long time!) */ 2037 for (ntries = 0; ntries < 100; ntries++) { 2038 tmp = ural_read(sc, RAL_MAC_CSR17); 2039 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2040 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2041 break; 2042 if (ural_pause(sc, hz / 100)) 2043 break; 2044 } 2045 if (ntries == 100) { 2046 device_printf(sc->sc_dev, 2047 "timeout waiting for BBP/RF to wakeup\n"); 2048 goto fail; 2049 } 2050 2051 /* we're ready! */ 2052 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2053 2054 /* set basic rate set (will be updated later) */ 2055 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2056 2057 if (ural_bbp_init(sc) != 0) 2058 goto fail; 2059 2060 ural_set_chan(sc, ic->ic_curchan); 2061 2062 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2063 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2064 2065 ural_set_txantenna(sc, sc->tx_ant); 2066 ural_set_rxantenna(sc, sc->rx_ant); 2067 2068 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2069 2070 /* 2071 * Allocate Tx and Rx xfer queues. 2072 */ 2073 ural_setup_tx_list(sc); 2074 2075 /* kick Rx */ 2076 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2077 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2078 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2079 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2080 tmp |= RAL_DROP_TODS; 2081 if (ic->ic_promisc == 0) 2082 tmp |= RAL_DROP_NOT_TO_ME; 2083 } 2084 ural_write(sc, RAL_TXRX_CSR2, tmp); 2085 2086 sc->sc_running = 1; 2087 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2088 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2089 return; 2090 2091 fail: ural_stop(sc); 2092 } 2093 2094 static void 2095 ural_stop(struct ural_softc *sc) 2096 { 2097 2098 RAL_LOCK_ASSERT(sc, MA_OWNED); 2099 2100 sc->sc_running = 0; 2101 2102 /* 2103 * Drain all the transfers, if not already drained: 2104 */ 2105 RAL_UNLOCK(sc); 2106 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2107 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2108 RAL_LOCK(sc); 2109 2110 ural_unsetup_tx_list(sc); 2111 2112 /* disable Rx */ 2113 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2114 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2115 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2116 /* wait a little */ 2117 ural_pause(sc, hz / 10); 2118 ural_write(sc, RAL_MAC_CSR1, 0); 2119 /* wait a little */ 2120 ural_pause(sc, hz / 10); 2121 } 2122 2123 static int 2124 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2125 const struct ieee80211_bpf_params *params) 2126 { 2127 struct ieee80211com *ic = ni->ni_ic; 2128 struct ural_softc *sc = ic->ic_softc; 2129 2130 RAL_LOCK(sc); 2131 /* prevent management frames from being sent if we're not ready */ 2132 if (!sc->sc_running) { 2133 RAL_UNLOCK(sc); 2134 m_freem(m); 2135 return ENETDOWN; 2136 } 2137 if (sc->tx_nfree < RAL_TX_MINFREE) { 2138 RAL_UNLOCK(sc); 2139 m_freem(m); 2140 return EIO; 2141 } 2142 2143 if (params == NULL) { 2144 /* 2145 * Legacy path; interpret frame contents to decide 2146 * precisely how to send the frame. 2147 */ 2148 if (ural_tx_mgt(sc, m, ni) != 0) 2149 goto bad; 2150 } else { 2151 /* 2152 * Caller supplied explicit parameters to use in 2153 * sending the frame. 2154 */ 2155 if (ural_tx_raw(sc, m, ni, params) != 0) 2156 goto bad; 2157 } 2158 RAL_UNLOCK(sc); 2159 return 0; 2160 bad: 2161 RAL_UNLOCK(sc); 2162 return EIO; /* XXX */ 2163 } 2164 2165 static void 2166 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2167 { 2168 struct ieee80211vap *vap = ni->ni_vap; 2169 struct ural_vap *uvp = URAL_VAP(vap); 2170 2171 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2172 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2173 2174 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2175 } 2176 2177 static void 2178 ural_ratectl_timeout(void *arg) 2179 { 2180 struct ural_vap *uvp = arg; 2181 struct ieee80211vap *vap = &uvp->vap; 2182 struct ieee80211com *ic = vap->iv_ic; 2183 2184 ieee80211_runtask(ic, &uvp->ratectl_task); 2185 } 2186 2187 static void 2188 ural_ratectl_task(void *arg, int pending) 2189 { 2190 struct ural_vap *uvp = arg; 2191 struct ieee80211vap *vap = &uvp->vap; 2192 struct ural_softc *sc = vap->iv_ic->ic_softc; 2193 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs; 2194 int fail; 2195 2196 RAL_LOCK(sc); 2197 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2198 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2199 2200 txs->flags = IEEE80211_RATECTL_TX_STATS_RETRIES; 2201 txs->nsuccess = sc->sta[7] + /* TX ok w/o retry */ 2202 sc->sta[8]; /* TX ok w/ retry */ 2203 fail = sc->sta[9]; /* TX retry-fail count */ 2204 txs->nframes = txs->nsuccess + fail; 2205 /* XXX fail * maxretry */ 2206 txs->nretries = sc->sta[8] + fail; 2207 2208 ieee80211_ratectl_tx_update(vap, txs); 2209 2210 /* count TX retry-fail as Tx errors */ 2211 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, fail); 2212 2213 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2214 RAL_UNLOCK(sc); 2215 } 2216 2217 static int 2218 ural_pause(struct ural_softc *sc, int timeout) 2219 { 2220 2221 usb_pause_mtx(&sc->sc_mtx, timeout); 2222 return (0); 2223 }
Cache object: 0011051d9c3616b43f8a1ff76c94f061
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