Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/wlan/if_urtw.c
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1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 20 #include "opt_wlan.h" 21 22 #include <sys/param.h> 23 #include <sys/sockio.h> 24 #include <sys/sysctl.h> 25 #include <sys/lock.h> 26 #include <sys/mutex.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/module.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kdb.h> 36 37 #include <net/if.h> 38 #include <net/if_var.h> 39 #include <net/if_arp.h> 40 #include <net/ethernet.h> 41 #include <net/if_dl.h> 42 #include <net/if_media.h> 43 #include <net/if_types.h> 44 45 #ifdef INET 46 #include <netinet/in.h> 47 #include <netinet/in_systm.h> 48 #include <netinet/in_var.h> 49 #include <netinet/if_ether.h> 50 #include <netinet/ip.h> 51 #endif 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_regdomain.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include "usbdevs.h" 60 61 #include <dev/usb/wlan/if_urtwreg.h> 62 #include <dev/usb/wlan/if_urtwvar.h> 63 64 /* copy some rate indices from if_rtwn_ridx.h */ 65 #define URTW_RIDX_CCK5 2 66 #define URTW_RIDX_CCK11 3 67 #define URTW_RIDX_OFDM6 4 68 #define URTW_RIDX_OFDM24 8 69 70 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 71 "USB Realtek 8187L"); 72 #ifdef URTW_DEBUG 73 int urtw_debug = 0; 74 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 75 "control debugging printfs"); 76 enum { 77 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 78 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 79 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 80 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 81 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 82 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 83 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 84 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 85 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 86 URTW_DEBUG_ANY = 0xffffffff 87 }; 88 #define DPRINTF(sc, m, fmt, ...) do { \ 89 if (sc->sc_debug & (m)) \ 90 printf(fmt, __VA_ARGS__); \ 91 } while (0) 92 #else 93 #define DPRINTF(sc, m, fmt, ...) do { \ 94 (void) sc; \ 95 } while (0) 96 #endif 97 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 98 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 99 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 100 101 /* recognized device vendors/products */ 102 #define urtw_lookup(v, p) \ 103 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 104 #define URTW_DEV_B(v,p) \ 105 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 106 #define URTW_DEV_L(v,p) \ 107 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 108 #define URTW_REV_RTL8187B 0 109 #define URTW_REV_RTL8187L 1 110 static const STRUCT_USB_HOST_ID urtw_devs[] = { 111 URTW_DEV_B(NETGEAR, WG111V3), 112 URTW_DEV_B(REALTEK, RTL8187B_0), 113 URTW_DEV_B(REALTEK, RTL8187B_1), 114 URTW_DEV_B(REALTEK, RTL8187B_2), 115 URTW_DEV_B(SITECOMEU, WL168V4), 116 URTW_DEV_L(ASUS, P5B_WIFI), 117 URTW_DEV_L(BELKIN, F5D7050E), 118 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 119 URTW_DEV_L(NETGEAR, WG111V2), 120 URTW_DEV_L(REALTEK, RTL8187), 121 URTW_DEV_L(SITECOMEU, WL168V1), 122 URTW_DEV_L(SURECOM, EP9001G2A), 123 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 124 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 125 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 126 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 127 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 128 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 129 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 130 #undef URTW_DEV_L 131 #undef URTW_DEV_B 132 }; 133 134 #define urtw_read8_m(sc, val, data) do { \ 135 error = urtw_read8_c(sc, val, data); \ 136 if (error != 0) \ 137 goto fail; \ 138 } while (0) 139 #define urtw_write8_m(sc, val, data) do { \ 140 error = urtw_write8_c(sc, val, data); \ 141 if (error != 0) \ 142 goto fail; \ 143 } while (0) 144 #define urtw_read16_m(sc, val, data) do { \ 145 error = urtw_read16_c(sc, val, data); \ 146 if (error != 0) \ 147 goto fail; \ 148 } while (0) 149 #define urtw_write16_m(sc, val, data) do { \ 150 error = urtw_write16_c(sc, val, data); \ 151 if (error != 0) \ 152 goto fail; \ 153 } while (0) 154 #define urtw_read32_m(sc, val, data) do { \ 155 error = urtw_read32_c(sc, val, data); \ 156 if (error != 0) \ 157 goto fail; \ 158 } while (0) 159 #define urtw_write32_m(sc, val, data) do { \ 160 error = urtw_write32_c(sc, val, data); \ 161 if (error != 0) \ 162 goto fail; \ 163 } while (0) 164 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 165 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 166 if (error != 0) \ 167 goto fail; \ 168 } while (0) 169 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 170 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 171 if (error != 0) \ 172 goto fail; \ 173 } while (0) 174 #define urtw_8225_write(sc, val, data) do { \ 175 error = urtw_8225_write_c(sc, val, data); \ 176 if (error != 0) \ 177 goto fail; \ 178 } while (0) 179 180 struct urtw_pair { 181 uint32_t reg; 182 uint32_t val; 183 }; 184 185 static uint8_t urtw_8225_agc[] = { 186 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 187 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 188 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 189 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 190 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 191 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 192 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 193 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 194 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 195 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 196 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 197 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 198 }; 199 200 static uint8_t urtw_8225z2_agc[] = { 201 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 202 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 203 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 204 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 205 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 206 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 207 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 208 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 209 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 210 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 211 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 212 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 213 }; 214 215 static uint32_t urtw_8225_channel[] = { 216 0x0000, /* dummy channel 0 */ 217 0x085c, /* 1 */ 218 0x08dc, /* 2 */ 219 0x095c, /* 3 */ 220 0x09dc, /* 4 */ 221 0x0a5c, /* 5 */ 222 0x0adc, /* 6 */ 223 0x0b5c, /* 7 */ 224 0x0bdc, /* 8 */ 225 0x0c5c, /* 9 */ 226 0x0cdc, /* 10 */ 227 0x0d5c, /* 11 */ 228 0x0ddc, /* 12 */ 229 0x0e5c, /* 13 */ 230 0x0f72, /* 14 */ 231 }; 232 233 static uint8_t urtw_8225_gain[] = { 234 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 235 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 236 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 237 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 238 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 239 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 240 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 241 }; 242 243 static struct urtw_pair urtw_8225_rf_part1[] = { 244 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 245 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 246 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 247 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 248 }; 249 250 static struct urtw_pair urtw_8225_rf_part2[] = { 251 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 252 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 253 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 254 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 255 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 256 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 257 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 258 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 259 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 260 { 0x27, 0x88 } 261 }; 262 263 static struct urtw_pair urtw_8225_rf_part3[] = { 264 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 265 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 266 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 267 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 268 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 269 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 270 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 271 }; 272 273 static uint16_t urtw_8225_rxgain[] = { 274 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 275 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 276 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 277 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 278 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 279 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 280 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 281 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 282 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 283 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 284 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 285 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 286 }; 287 288 static uint8_t urtw_8225_threshold[] = { 289 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 290 }; 291 292 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 293 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 294 }; 295 296 static uint8_t urtw_8225_txpwr_cck[] = { 297 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 298 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 299 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 300 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 301 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 302 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 303 }; 304 305 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 306 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 307 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 308 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 309 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 310 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 311 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 312 }; 313 314 static uint8_t urtw_8225_txpwr_ofdm[]={ 315 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 316 }; 317 318 static uint8_t urtw_8225v2_gain_bg[]={ 319 0x23, 0x15, 0xa5, /* -82-1dbm */ 320 0x23, 0x15, 0xb5, /* -82-2dbm */ 321 0x23, 0x15, 0xc5, /* -82-3dbm */ 322 0x33, 0x15, 0xc5, /* -78dbm */ 323 0x43, 0x15, 0xc5, /* -74dbm */ 324 0x53, 0x15, 0xc5, /* -70dbm */ 325 0x63, 0x15, 0xc5, /* -66dbm */ 326 }; 327 328 static struct urtw_pair urtw_8225v2_rf_part1[] = { 329 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 330 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 331 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 332 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 333 }; 334 335 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 336 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 337 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 338 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 339 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 340 }; 341 342 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 343 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 344 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 345 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 346 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 347 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 348 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 349 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 350 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 351 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 352 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 353 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 354 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 355 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 356 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 357 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 358 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 359 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 360 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 361 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 362 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 363 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 364 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 365 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 366 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 367 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 368 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 369 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 370 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 371 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 372 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 373 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 374 }; 375 376 static struct urtw_pair urtw_8225v2_rf_part2[] = { 377 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 378 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 379 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 380 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 381 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 382 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 383 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 384 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 385 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 386 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 387 }; 388 389 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 390 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 391 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 392 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 393 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 394 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 395 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 396 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 397 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 398 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 399 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 400 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 401 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 402 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 403 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 404 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 405 }; 406 407 static struct urtw_pair urtw_8225v2_rf_part3[] = { 408 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 409 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 410 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 411 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 412 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 413 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 414 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 415 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 416 }; 417 418 static uint16_t urtw_8225v2_rxgain[] = { 419 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 420 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 421 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 422 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 423 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 424 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 425 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 426 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 427 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 428 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 429 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 430 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 431 }; 432 433 static uint16_t urtw_8225v2b_rxgain[] = { 434 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 435 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 436 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 437 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 438 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 439 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 440 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 441 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 442 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 443 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 444 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 445 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 446 }; 447 448 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 449 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 450 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 451 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 452 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 453 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 454 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 455 }; 456 457 static uint8_t urtw_8225v2_txpwr_cck[] = { 458 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 459 }; 460 461 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 462 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 463 }; 464 465 static uint8_t urtw_8225v2b_txpwr_cck[] = { 466 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 467 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 468 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 469 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 470 }; 471 472 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 473 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 474 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 475 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 476 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 477 }; 478 479 static struct urtw_pair urtw_ratetable[] = { 480 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 481 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 482 { 96, 10 }, { 108, 11 } 483 }; 484 485 #if 0 486 static const uint8_t urtw_8187b_reg_table[][3] = { 487 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 488 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 489 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 490 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 491 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 492 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 493 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 494 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 495 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 496 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 497 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 498 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 499 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 500 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 501 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 502 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 503 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 504 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 505 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 506 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 507 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 508 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 509 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 510 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 511 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 512 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 513 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 514 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 515 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 516 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 517 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 518 }; 519 #endif 520 521 static usb_callback_t urtw_bulk_rx_callback; 522 static usb_callback_t urtw_bulk_tx_callback; 523 static usb_callback_t urtw_bulk_tx_status_callback; 524 525 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 526 [URTW_8187B_BULK_RX] = { 527 .type = UE_BULK, 528 .endpoint = 0x83, 529 .direction = UE_DIR_IN, 530 .bufsize = MCLBYTES, 531 .flags = { 532 .ext_buffer = 1, 533 .pipe_bof = 1, 534 .short_xfer_ok = 1 535 }, 536 .callback = urtw_bulk_rx_callback 537 }, 538 [URTW_8187B_BULK_TX_STATUS] = { 539 .type = UE_BULK, 540 .endpoint = 0x89, 541 .direction = UE_DIR_IN, 542 .bufsize = sizeof(uint64_t), 543 .flags = { 544 .pipe_bof = 1, 545 .short_xfer_ok = 1 546 }, 547 .callback = urtw_bulk_tx_status_callback 548 }, 549 [URTW_8187B_BULK_TX_BE] = { 550 .type = UE_BULK, 551 .endpoint = URTW_8187B_TXPIPE_BE, 552 .direction = UE_DIR_OUT, 553 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 554 .flags = { 555 .force_short_xfer = 1, 556 .pipe_bof = 1, 557 }, 558 .callback = urtw_bulk_tx_callback, 559 .timeout = URTW_DATA_TIMEOUT 560 }, 561 [URTW_8187B_BULK_TX_BK] = { 562 .type = UE_BULK, 563 .endpoint = URTW_8187B_TXPIPE_BK, 564 .direction = UE_DIR_OUT, 565 .bufsize = URTW_TX_MAXSIZE, 566 .flags = { 567 .ext_buffer = 1, 568 .force_short_xfer = 1, 569 .pipe_bof = 1, 570 }, 571 .callback = urtw_bulk_tx_callback, 572 .timeout = URTW_DATA_TIMEOUT 573 }, 574 [URTW_8187B_BULK_TX_VI] = { 575 .type = UE_BULK, 576 .endpoint = URTW_8187B_TXPIPE_VI, 577 .direction = UE_DIR_OUT, 578 .bufsize = URTW_TX_MAXSIZE, 579 .flags = { 580 .ext_buffer = 1, 581 .force_short_xfer = 1, 582 .pipe_bof = 1, 583 }, 584 .callback = urtw_bulk_tx_callback, 585 .timeout = URTW_DATA_TIMEOUT 586 }, 587 [URTW_8187B_BULK_TX_VO] = { 588 .type = UE_BULK, 589 .endpoint = URTW_8187B_TXPIPE_VO, 590 .direction = UE_DIR_OUT, 591 .bufsize = URTW_TX_MAXSIZE, 592 .flags = { 593 .ext_buffer = 1, 594 .force_short_xfer = 1, 595 .pipe_bof = 1, 596 }, 597 .callback = urtw_bulk_tx_callback, 598 .timeout = URTW_DATA_TIMEOUT 599 }, 600 [URTW_8187B_BULK_TX_EP12] = { 601 .type = UE_BULK, 602 .endpoint = 0xc, 603 .direction = UE_DIR_OUT, 604 .bufsize = URTW_TX_MAXSIZE, 605 .flags = { 606 .ext_buffer = 1, 607 .force_short_xfer = 1, 608 .pipe_bof = 1, 609 }, 610 .callback = urtw_bulk_tx_callback, 611 .timeout = URTW_DATA_TIMEOUT 612 } 613 }; 614 615 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 616 [URTW_8187L_BULK_RX] = { 617 .type = UE_BULK, 618 .endpoint = 0x81, 619 .direction = UE_DIR_IN, 620 .bufsize = MCLBYTES, 621 .flags = { 622 .ext_buffer = 1, 623 .pipe_bof = 1, 624 .short_xfer_ok = 1 625 }, 626 .callback = urtw_bulk_rx_callback 627 }, 628 [URTW_8187L_BULK_TX_LOW] = { 629 .type = UE_BULK, 630 .endpoint = 0x2, 631 .direction = UE_DIR_OUT, 632 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 633 .flags = { 634 .force_short_xfer = 1, 635 .pipe_bof = 1, 636 }, 637 .callback = urtw_bulk_tx_callback, 638 .timeout = URTW_DATA_TIMEOUT 639 }, 640 [URTW_8187L_BULK_TX_NORMAL] = { 641 .type = UE_BULK, 642 .endpoint = 0x3, 643 .direction = UE_DIR_OUT, 644 .bufsize = URTW_TX_MAXSIZE, 645 .flags = { 646 .ext_buffer = 1, 647 .force_short_xfer = 1, 648 .pipe_bof = 1, 649 }, 650 .callback = urtw_bulk_tx_callback, 651 .timeout = URTW_DATA_TIMEOUT 652 }, 653 }; 654 655 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 656 const char [IFNAMSIZ], int, enum ieee80211_opmode, 657 int, const uint8_t [IEEE80211_ADDR_LEN], 658 const uint8_t [IEEE80211_ADDR_LEN]); 659 static void urtw_vap_delete(struct ieee80211vap *); 660 static void urtw_init(struct urtw_softc *); 661 static void urtw_stop(struct urtw_softc *); 662 static void urtw_parent(struct ieee80211com *); 663 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 664 static void urtw_start(struct urtw_softc *); 665 static int urtw_alloc_rx_data_list(struct urtw_softc *); 666 static int urtw_alloc_tx_data_list(struct urtw_softc *); 667 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 668 const struct ieee80211_bpf_params *); 669 static void urtw_scan_start(struct ieee80211com *); 670 static void urtw_scan_end(struct ieee80211com *); 671 static void urtw_getradiocaps(struct ieee80211com *, int, int *, 672 struct ieee80211_channel[]); 673 static void urtw_set_channel(struct ieee80211com *); 674 static void urtw_update_promisc(struct ieee80211com *); 675 static void urtw_update_mcast(struct ieee80211com *); 676 static int urtw_tx_start(struct urtw_softc *, 677 struct ieee80211_node *, struct mbuf *, 678 struct urtw_data *, int); 679 static int urtw_newstate(struct ieee80211vap *, 680 enum ieee80211_state, int); 681 static void urtw_led_ch(void *); 682 static void urtw_ledtask(void *, int); 683 static void urtw_watchdog(void *); 684 static void urtw_set_multi(void *); 685 static int urtw_isbmode(uint16_t); 686 static uint16_t urtw_rtl2rate(uint32_t); 687 static usb_error_t urtw_set_rate(struct urtw_softc *); 688 static usb_error_t urtw_update_msr(struct urtw_softc *); 689 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 690 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 691 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 692 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 693 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 694 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 695 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 696 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 697 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 698 int); 699 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 700 uint32_t *); 701 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 702 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 703 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 704 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 705 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 706 static usb_error_t urtw_led_init(struct urtw_softc *); 707 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 708 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 709 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 710 uint32_t); 711 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 712 uint8_t, uint32_t); 713 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 714 uint32_t); 715 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 716 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 717 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 718 uint16_t); 719 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 720 uint16_t *); 721 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 722 uint32_t *); 723 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 724 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 725 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 726 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 727 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 728 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 729 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 730 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 731 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 732 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 733 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 734 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 735 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 736 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 737 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 738 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 739 static usb_error_t urtw_intr_enable(struct urtw_softc *); 740 static usb_error_t urtw_intr_disable(struct urtw_softc *); 741 static usb_error_t urtw_reset(struct urtw_softc *); 742 static usb_error_t urtw_led_on(struct urtw_softc *, int); 743 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 744 static usb_error_t urtw_led_blink(struct urtw_softc *); 745 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 746 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 747 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 748 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 749 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 750 static usb_error_t urtw_rx_enable(struct urtw_softc *); 751 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 752 static void urtw_free_tx_data_list(struct urtw_softc *); 753 static void urtw_free_rx_data_list(struct urtw_softc *); 754 static void urtw_free_data_list(struct urtw_softc *, 755 struct urtw_data data[], int, int); 756 static usb_error_t urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 757 static usb_error_t urtw_adapter_start(struct urtw_softc *); 758 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 759 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 760 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 761 static usb_error_t urtw_do_request(struct urtw_softc *, 762 struct usb_device_request *, void *); 763 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 764 static usb_error_t urtw_led_off(struct urtw_softc *, int); 765 static void urtw_abort_xfers(struct urtw_softc *); 766 static struct urtw_data * 767 urtw_getbuf(struct urtw_softc *sc); 768 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 769 uint8_t); 770 static void urtw_updateslot(struct ieee80211com *); 771 static void urtw_updateslottask(void *, int); 772 static void urtw_sysctl_node(struct urtw_softc *); 773 774 static int 775 urtw_match(device_t dev) 776 { 777 struct usb_attach_arg *uaa = device_get_ivars(dev); 778 779 if (uaa->usb_mode != USB_MODE_HOST) 780 return (ENXIO); 781 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 782 return (ENXIO); 783 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 784 return (ENXIO); 785 786 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 787 } 788 789 static int 790 urtw_attach(device_t dev) 791 { 792 const struct usb_config *setup_start; 793 int ret = ENXIO; 794 struct urtw_softc *sc = device_get_softc(dev); 795 struct usb_attach_arg *uaa = device_get_ivars(dev); 796 struct ieee80211com *ic = &sc->sc_ic; 797 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 798 uint16_t n_setup; 799 uint32_t data; 800 usb_error_t error; 801 802 device_set_usb_desc(dev); 803 804 sc->sc_dev = dev; 805 sc->sc_udev = uaa->device; 806 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 807 sc->sc_flags |= URTW_RTL8187B; 808 #ifdef URTW_DEBUG 809 sc->sc_debug = urtw_debug; 810 #endif 811 812 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 813 MTX_DEF); 814 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 815 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 816 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 817 callout_init(&sc->sc_watchdog_ch, 0); 818 mbufq_init(&sc->sc_snd, ifqmaxlen); 819 820 if (sc->sc_flags & URTW_RTL8187B) { 821 setup_start = urtw_8187b_usbconfig; 822 n_setup = URTW_8187B_N_XFERS; 823 } else { 824 setup_start = urtw_8187l_usbconfig; 825 n_setup = URTW_8187L_N_XFERS; 826 } 827 828 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 829 setup_start, n_setup, sc, &sc->sc_mtx); 830 if (error) { 831 device_printf(dev, "could not allocate USB transfers, " 832 "err=%s\n", usbd_errstr(error)); 833 ret = ENXIO; 834 goto fail0; 835 } 836 837 if (sc->sc_flags & URTW_RTL8187B) { 838 sc->sc_tx_dma_buf = 839 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 840 URTW_8187B_BULK_TX_BE], 0); 841 } else { 842 sc->sc_tx_dma_buf = 843 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 844 URTW_8187L_BULK_TX_LOW], 0); 845 } 846 847 URTW_LOCK(sc); 848 849 urtw_read32_m(sc, URTW_RX, &data); 850 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 851 URTW_EEPROM_93C46; 852 853 error = urtw_get_rfchip(sc); 854 if (error != 0) 855 goto fail; 856 error = urtw_get_macaddr(sc); 857 if (error != 0) 858 goto fail; 859 error = urtw_get_txpwr(sc); 860 if (error != 0) 861 goto fail; 862 error = urtw_led_init(sc); 863 if (error != 0) 864 goto fail; 865 866 URTW_UNLOCK(sc); 867 868 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 869 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 870 sc->sc_currate = URTW_RIDX_CCK11; 871 sc->sc_preamble_mode = urtw_preamble_mode; 872 873 ic->ic_softc = sc; 874 ic->ic_name = device_get_nameunit(dev); 875 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 876 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 877 878 /* set device capabilities */ 879 ic->ic_caps = 880 IEEE80211_C_STA | /* station mode */ 881 IEEE80211_C_MONITOR | /* monitor mode supported */ 882 IEEE80211_C_TXPMGT | /* tx power management */ 883 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 884 IEEE80211_C_SHSLOT | /* short slot time supported */ 885 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 886 IEEE80211_C_WPA; /* 802.11i */ 887 888 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/ 889 890 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 891 ic->ic_channels); 892 893 ieee80211_ifattach(ic); 894 ic->ic_raw_xmit = urtw_raw_xmit; 895 ic->ic_scan_start = urtw_scan_start; 896 ic->ic_scan_end = urtw_scan_end; 897 ic->ic_getradiocaps = urtw_getradiocaps; 898 ic->ic_set_channel = urtw_set_channel; 899 ic->ic_updateslot = urtw_updateslot; 900 ic->ic_vap_create = urtw_vap_create; 901 ic->ic_vap_delete = urtw_vap_delete; 902 ic->ic_update_promisc = urtw_update_promisc; 903 ic->ic_update_mcast = urtw_update_mcast; 904 ic->ic_parent = urtw_parent; 905 ic->ic_transmit = urtw_transmit; 906 907 ieee80211_radiotap_attach(ic, 908 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 909 URTW_TX_RADIOTAP_PRESENT, 910 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 911 URTW_RX_RADIOTAP_PRESENT); 912 913 urtw_sysctl_node(sc); 914 915 if (bootverbose) 916 ieee80211_announce(ic); 917 return (0); 918 919 fail: 920 URTW_UNLOCK(sc); 921 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 922 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 923 fail0: 924 return (ret); 925 } 926 927 static int 928 urtw_detach(device_t dev) 929 { 930 struct urtw_softc *sc = device_get_softc(dev); 931 struct ieee80211com *ic = &sc->sc_ic; 932 unsigned x; 933 unsigned n_xfers; 934 935 /* Prevent further ioctls */ 936 URTW_LOCK(sc); 937 sc->sc_flags |= URTW_DETACHED; 938 urtw_stop(sc); 939 URTW_UNLOCK(sc); 940 941 ieee80211_draintask(ic, &sc->sc_updateslot_task); 942 ieee80211_draintask(ic, &sc->sc_led_task); 943 944 usb_callout_drain(&sc->sc_led_ch); 945 callout_drain(&sc->sc_watchdog_ch); 946 947 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 948 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 949 950 /* prevent further allocations from RX/TX data lists */ 951 URTW_LOCK(sc); 952 STAILQ_INIT(&sc->sc_tx_active); 953 STAILQ_INIT(&sc->sc_tx_inactive); 954 STAILQ_INIT(&sc->sc_tx_pending); 955 956 STAILQ_INIT(&sc->sc_rx_active); 957 STAILQ_INIT(&sc->sc_rx_inactive); 958 URTW_UNLOCK(sc); 959 960 /* drain USB transfers */ 961 for (x = 0; x != n_xfers; x++) 962 usbd_transfer_drain(sc->sc_xfer[x]); 963 964 /* free data buffers */ 965 URTW_LOCK(sc); 966 urtw_free_tx_data_list(sc); 967 urtw_free_rx_data_list(sc); 968 URTW_UNLOCK(sc); 969 970 /* free USB transfers and some data buffers */ 971 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 972 973 ieee80211_ifdetach(ic); 974 mbufq_drain(&sc->sc_snd); 975 mtx_destroy(&sc->sc_mtx); 976 return (0); 977 } 978 979 static void 980 urtw_free_tx_data_list(struct urtw_softc *sc) 981 { 982 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 983 } 984 985 static void 986 urtw_free_rx_data_list(struct urtw_softc *sc) 987 { 988 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 989 } 990 991 static void 992 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 993 int fillmbuf) 994 { 995 int i; 996 997 for (i = 0; i < ndata; i++) { 998 struct urtw_data *dp = &data[i]; 999 1000 if (fillmbuf == 1) { 1001 if (dp->m != NULL) { 1002 m_freem(dp->m); 1003 dp->m = NULL; 1004 dp->buf = NULL; 1005 } 1006 } else { 1007 dp->buf = NULL; 1008 } 1009 if (dp->ni != NULL) { 1010 ieee80211_free_node(dp->ni); 1011 dp->ni = NULL; 1012 } 1013 } 1014 } 1015 1016 static struct ieee80211vap * 1017 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1018 enum ieee80211_opmode opmode, int flags, 1019 const uint8_t bssid[IEEE80211_ADDR_LEN], 1020 const uint8_t mac[IEEE80211_ADDR_LEN]) 1021 { 1022 struct urtw_vap *uvp; 1023 struct ieee80211vap *vap; 1024 1025 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1026 return (NULL); 1027 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1028 vap = &uvp->vap; 1029 /* enable s/w bmiss handling for sta mode */ 1030 1031 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1032 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1033 /* out of memory */ 1034 free(uvp, M_80211_VAP); 1035 return (NULL); 1036 } 1037 1038 /* override state transition machine */ 1039 uvp->newstate = vap->iv_newstate; 1040 vap->iv_newstate = urtw_newstate; 1041 1042 /* complete setup */ 1043 ieee80211_vap_attach(vap, ieee80211_media_change, 1044 ieee80211_media_status, mac); 1045 ic->ic_opmode = opmode; 1046 return (vap); 1047 } 1048 1049 static void 1050 urtw_vap_delete(struct ieee80211vap *vap) 1051 { 1052 struct urtw_vap *uvp = URTW_VAP(vap); 1053 1054 ieee80211_vap_detach(vap); 1055 free(uvp, M_80211_VAP); 1056 } 1057 1058 static void 1059 urtw_init(struct urtw_softc *sc) 1060 { 1061 usb_error_t error; 1062 int ret; 1063 1064 URTW_ASSERT_LOCKED(sc); 1065 1066 if (sc->sc_flags & URTW_RUNNING) 1067 urtw_stop(sc); 1068 1069 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1070 urtw_adapter_start(sc); 1071 if (error != 0) 1072 goto fail; 1073 1074 /* reset softc variables */ 1075 sc->sc_txtimer = 0; 1076 1077 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1078 ret = urtw_alloc_rx_data_list(sc); 1079 if (ret != 0) 1080 goto fail; 1081 ret = urtw_alloc_tx_data_list(sc); 1082 if (ret != 0) 1083 goto fail; 1084 sc->sc_flags |= URTW_INIT_ONCE; 1085 } 1086 1087 error = urtw_rx_enable(sc); 1088 if (error != 0) 1089 goto fail; 1090 error = urtw_tx_enable(sc); 1091 if (error != 0) 1092 goto fail; 1093 1094 if (sc->sc_flags & URTW_RTL8187B) 1095 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1096 1097 sc->sc_flags |= URTW_RUNNING; 1098 1099 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1100 fail: 1101 return; 1102 } 1103 1104 static usb_error_t 1105 urtw_adapter_start_b(struct urtw_softc *sc) 1106 { 1107 uint8_t data8; 1108 usb_error_t error; 1109 1110 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1111 if (error) 1112 goto fail; 1113 1114 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1115 urtw_write8_m(sc, URTW_CONFIG3, 1116 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1117 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1118 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1119 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1120 1121 urtw_write8_m(sc, 0x61, 0x10); 1122 urtw_read8_m(sc, 0x62, &data8); 1123 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1124 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1125 1126 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1127 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1128 urtw_write8_m(sc, URTW_CONFIG3, data8); 1129 1130 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1131 if (error) 1132 goto fail; 1133 1134 error = urtw_8187b_cmd_reset(sc); 1135 if (error) 1136 goto fail; 1137 1138 error = sc->sc_rf_init(sc); 1139 if (error != 0) 1140 goto fail; 1141 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1142 1143 /* fix RTL8187B RX stall */ 1144 error = urtw_intr_enable(sc); 1145 if (error) 1146 goto fail; 1147 1148 error = urtw_write8e(sc, 0x41, 0xf4); 1149 if (error) 1150 goto fail; 1151 error = urtw_write8e(sc, 0x40, 0x00); 1152 if (error) 1153 goto fail; 1154 error = urtw_write8e(sc, 0x42, 0x00); 1155 if (error) 1156 goto fail; 1157 error = urtw_write8e(sc, 0x42, 0x01); 1158 if (error) 1159 goto fail; 1160 error = urtw_write8e(sc, 0x40, 0x0f); 1161 if (error) 1162 goto fail; 1163 error = urtw_write8e(sc, 0x42, 0x00); 1164 if (error) 1165 goto fail; 1166 error = urtw_write8e(sc, 0x42, 0x01); 1167 if (error) 1168 goto fail; 1169 1170 urtw_read8_m(sc, 0xdb, &data8); 1171 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1172 urtw_write16_m(sc, 0x372, 0x59fa); 1173 urtw_write16_m(sc, 0x374, 0x59d2); 1174 urtw_write16_m(sc, 0x376, 0x59d2); 1175 urtw_write16_m(sc, 0x378, 0x19fa); 1176 urtw_write16_m(sc, 0x37a, 0x19fa); 1177 urtw_write16_m(sc, 0x37c, 0x00d0); 1178 urtw_write8_m(sc, 0x61, 0); 1179 1180 urtw_write8_m(sc, 0x180, 0x0f); 1181 urtw_write8_m(sc, 0x183, 0x03); 1182 urtw_write8_m(sc, 0xda, 0x10); 1183 urtw_write8_m(sc, 0x24d, 0x08); 1184 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1185 1186 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1187 fail: 1188 return (error); 1189 } 1190 1191 static usb_error_t 1192 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *macaddr) 1193 { 1194 usb_error_t error; 1195 1196 urtw_write32_m(sc, URTW_MAC0, ((const uint32_t *)macaddr)[0]); 1197 urtw_write16_m(sc, URTW_MAC4, ((const uint32_t *)macaddr)[1] & 0xffff); 1198 1199 fail: 1200 return (error); 1201 } 1202 1203 static usb_error_t 1204 urtw_adapter_start(struct urtw_softc *sc) 1205 { 1206 struct ieee80211com *ic = &sc->sc_ic; 1207 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1208 const uint8_t *macaddr; 1209 usb_error_t error; 1210 1211 error = urtw_reset(sc); 1212 if (error) 1213 goto fail; 1214 1215 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1216 urtw_write8_m(sc, URTW_GPIO, 0); 1217 1218 /* for led */ 1219 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1220 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1221 if (error != 0) 1222 goto fail; 1223 1224 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1225 if (error) 1226 goto fail; 1227 /* applying MAC address again. */ 1228 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 1229 urtw_set_macaddr(sc, macaddr); 1230 if (error) 1231 goto fail; 1232 1233 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1234 if (error) 1235 goto fail; 1236 1237 error = urtw_update_msr(sc); 1238 if (error) 1239 goto fail; 1240 1241 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1242 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1243 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1244 error = urtw_set_rate(sc); 1245 if (error != 0) 1246 goto fail; 1247 1248 error = sc->sc_rf_init(sc); 1249 if (error != 0) 1250 goto fail; 1251 if (sc->sc_rf_set_sens != NULL) 1252 sc->sc_rf_set_sens(sc, sc->sc_sens); 1253 1254 /* XXX correct? to call write16 */ 1255 urtw_write16_m(sc, URTW_PSR, 1); 1256 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1257 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1258 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1259 /* XXX correct? to call write16 */ 1260 urtw_write16_m(sc, URTW_PSR, 0); 1261 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1262 1263 error = urtw_intr_enable(sc); 1264 if (error != 0) 1265 goto fail; 1266 1267 fail: 1268 return (error); 1269 } 1270 1271 static usb_error_t 1272 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1273 { 1274 uint8_t data; 1275 usb_error_t error; 1276 1277 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1278 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1279 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1280 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1281 fail: 1282 return (error); 1283 } 1284 1285 static void 1286 urtw_pause_ms(struct urtw_softc *sc, int delay) 1287 { 1288 usb_pause_mtx(&sc->sc_mtx, USB_MS_TO_TICKS(delay)); 1289 } 1290 1291 static usb_error_t 1292 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1293 { 1294 int i; 1295 uint8_t data8; 1296 usb_error_t error; 1297 1298 /* XXX the code can be duplicate with urtw_reset(). */ 1299 urtw_read8_m(sc, URTW_CMD, &data8); 1300 data8 = (data8 & 0x2) | URTW_CMD_RST; 1301 urtw_write8_m(sc, URTW_CMD, data8); 1302 1303 for (i = 0; i < 20; i++) { 1304 urtw_pause_ms(sc, 2); 1305 urtw_read8_m(sc, URTW_CMD, &data8); 1306 if (!(data8 & URTW_CMD_RST)) 1307 break; 1308 } 1309 if (i >= 20) { 1310 device_printf(sc->sc_dev, "reset timeout\n"); 1311 goto fail; 1312 } 1313 fail: 1314 return (error); 1315 } 1316 1317 static usb_error_t 1318 urtw_do_request(struct urtw_softc *sc, 1319 struct usb_device_request *req, void *data) 1320 { 1321 usb_error_t err; 1322 int ntries = 10; 1323 1324 URTW_ASSERT_LOCKED(sc); 1325 1326 while (ntries--) { 1327 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1328 req, data, 0, NULL, 250 /* ms */); 1329 if (err == 0) 1330 break; 1331 1332 DPRINTF(sc, URTW_DEBUG_INIT, 1333 "Control request failed, %s (retrying)\n", 1334 usbd_errstr(err)); 1335 urtw_pause_ms(sc, 10); 1336 } 1337 return (err); 1338 } 1339 1340 static void 1341 urtw_stop(struct urtw_softc *sc) 1342 { 1343 uint8_t data8; 1344 usb_error_t error; 1345 1346 URTW_ASSERT_LOCKED(sc); 1347 1348 sc->sc_flags &= ~URTW_RUNNING; 1349 1350 error = urtw_intr_disable(sc); 1351 if (error) 1352 goto fail; 1353 urtw_read8_m(sc, URTW_CMD, &data8); 1354 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1355 urtw_write8_m(sc, URTW_CMD, data8); 1356 1357 error = sc->sc_rf_stop(sc); 1358 if (error != 0) 1359 goto fail; 1360 1361 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1362 if (error) 1363 goto fail; 1364 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1365 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1366 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1367 if (error) 1368 goto fail; 1369 fail: 1370 if (error) 1371 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1372 usbd_errstr(error)); 1373 1374 usb_callout_stop(&sc->sc_led_ch); 1375 callout_stop(&sc->sc_watchdog_ch); 1376 1377 urtw_abort_xfers(sc); 1378 } 1379 1380 static void 1381 urtw_abort_xfers(struct urtw_softc *sc) 1382 { 1383 int i, max; 1384 1385 URTW_ASSERT_LOCKED(sc); 1386 1387 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1388 URTW_8187L_N_XFERS; 1389 1390 /* abort any pending transfers */ 1391 for (i = 0; i < max; i++) 1392 usbd_transfer_stop(sc->sc_xfer[i]); 1393 } 1394 1395 static void 1396 urtw_parent(struct ieee80211com *ic) 1397 { 1398 struct urtw_softc *sc = ic->ic_softc; 1399 int startall = 0; 1400 1401 URTW_LOCK(sc); 1402 if (sc->sc_flags & URTW_DETACHED) { 1403 URTW_UNLOCK(sc); 1404 return; 1405 } 1406 1407 if (ic->ic_nrunning > 0) { 1408 if (sc->sc_flags & URTW_RUNNING) { 1409 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1410 urtw_set_multi(sc); 1411 } else { 1412 urtw_init(sc); 1413 startall = 1; 1414 } 1415 } else if (sc->sc_flags & URTW_RUNNING) 1416 urtw_stop(sc); 1417 URTW_UNLOCK(sc); 1418 if (startall) 1419 ieee80211_start_all(ic); 1420 } 1421 1422 static int 1423 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1424 { 1425 struct urtw_softc *sc = ic->ic_softc; 1426 int error; 1427 1428 URTW_LOCK(sc); 1429 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1430 URTW_UNLOCK(sc); 1431 return (ENXIO); 1432 } 1433 error = mbufq_enqueue(&sc->sc_snd, m); 1434 if (error) { 1435 URTW_UNLOCK(sc); 1436 return (error); 1437 } 1438 urtw_start(sc); 1439 URTW_UNLOCK(sc); 1440 1441 return (0); 1442 } 1443 1444 static void 1445 urtw_start(struct urtw_softc *sc) 1446 { 1447 struct urtw_data *bf; 1448 struct ieee80211_node *ni; 1449 struct mbuf *m; 1450 1451 URTW_ASSERT_LOCKED(sc); 1452 1453 if ((sc->sc_flags & URTW_RUNNING) == 0) 1454 return; 1455 1456 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1457 bf = urtw_getbuf(sc); 1458 if (bf == NULL) { 1459 mbufq_prepend(&sc->sc_snd, m); 1460 break; 1461 } 1462 1463 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1464 m->m_pkthdr.rcvif = NULL; 1465 1466 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1467 if_inc_counter(ni->ni_vap->iv_ifp, 1468 IFCOUNTER_OERRORS, 1); 1469 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1470 ieee80211_free_node(ni); 1471 break; 1472 } 1473 1474 sc->sc_txtimer = 5; 1475 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1476 } 1477 } 1478 1479 static int 1480 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1481 int ndata, int maxsz, void *dma_buf) 1482 { 1483 int i, error; 1484 1485 for (i = 0; i < ndata; i++) { 1486 struct urtw_data *dp = &data[i]; 1487 1488 dp->sc = sc; 1489 if (dma_buf == NULL) { 1490 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1491 if (dp->m == NULL) { 1492 device_printf(sc->sc_dev, 1493 "could not allocate rx mbuf\n"); 1494 error = ENOMEM; 1495 goto fail; 1496 } 1497 dp->buf = mtod(dp->m, uint8_t *); 1498 } else { 1499 dp->m = NULL; 1500 dp->buf = ((uint8_t *)dma_buf) + 1501 (i * maxsz); 1502 } 1503 dp->ni = NULL; 1504 } 1505 return (0); 1506 1507 fail: urtw_free_data_list(sc, data, ndata, 1); 1508 return (error); 1509 } 1510 1511 static int 1512 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1513 { 1514 int error, i; 1515 1516 error = urtw_alloc_data_list(sc, 1517 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1518 MCLBYTES, NULL /* mbufs */); 1519 if (error != 0) 1520 return (error); 1521 1522 STAILQ_INIT(&sc->sc_rx_active); 1523 STAILQ_INIT(&sc->sc_rx_inactive); 1524 1525 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1526 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1527 1528 return (0); 1529 } 1530 1531 static int 1532 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1533 { 1534 int error, i; 1535 1536 error = urtw_alloc_data_list(sc, 1537 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1538 sc->sc_tx_dma_buf /* no mbufs */); 1539 if (error != 0) 1540 return (error); 1541 1542 STAILQ_INIT(&sc->sc_tx_active); 1543 STAILQ_INIT(&sc->sc_tx_inactive); 1544 STAILQ_INIT(&sc->sc_tx_pending); 1545 1546 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1547 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1548 next); 1549 1550 return (0); 1551 } 1552 1553 static int 1554 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1555 const struct ieee80211_bpf_params *params) 1556 { 1557 struct ieee80211com *ic = ni->ni_ic; 1558 struct urtw_softc *sc = ic->ic_softc; 1559 struct urtw_data *bf; 1560 1561 /* prevent management frames from being sent if we're not ready */ 1562 if (!(sc->sc_flags & URTW_RUNNING)) { 1563 m_freem(m); 1564 return ENETDOWN; 1565 } 1566 URTW_LOCK(sc); 1567 bf = urtw_getbuf(sc); 1568 if (bf == NULL) { 1569 m_freem(m); 1570 URTW_UNLOCK(sc); 1571 return (ENOBUFS); /* XXX */ 1572 } 1573 1574 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1575 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1576 URTW_UNLOCK(sc); 1577 return (EIO); 1578 } 1579 URTW_UNLOCK(sc); 1580 1581 sc->sc_txtimer = 5; 1582 return (0); 1583 } 1584 1585 static void 1586 urtw_scan_start(struct ieee80211com *ic) 1587 { 1588 1589 /* XXX do nothing? */ 1590 } 1591 1592 static void 1593 urtw_scan_end(struct ieee80211com *ic) 1594 { 1595 1596 /* XXX do nothing? */ 1597 } 1598 1599 static void 1600 urtw_getradiocaps(struct ieee80211com *ic, 1601 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1602 { 1603 uint8_t bands[IEEE80211_MODE_BYTES]; 1604 1605 memset(bands, 0, sizeof(bands)); 1606 setbit(bands, IEEE80211_MODE_11B); 1607 setbit(bands, IEEE80211_MODE_11G); 1608 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1609 } 1610 1611 static void 1612 urtw_set_channel(struct ieee80211com *ic) 1613 { 1614 struct urtw_softc *sc = ic->ic_softc; 1615 uint32_t data, orig; 1616 usb_error_t error; 1617 1618 /* 1619 * if the user set a channel explicitly using ifconfig(8) this function 1620 * can be called earlier than we're expected that in some cases the 1621 * initialization would be failed if setting a channel is called before 1622 * the init have done. 1623 */ 1624 if (!(sc->sc_flags & URTW_RUNNING)) 1625 return; 1626 1627 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1628 return; 1629 1630 URTW_LOCK(sc); 1631 1632 /* 1633 * during changing th channel we need to temporarily be disable 1634 * TX. 1635 */ 1636 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1637 data = orig & ~URTW_TX_LOOPBACK_MASK; 1638 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1639 1640 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1641 if (error != 0) 1642 goto fail; 1643 urtw_pause_ms(sc, 10); 1644 urtw_write32_m(sc, URTW_TX_CONF, orig); 1645 1646 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1647 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1648 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1649 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1650 1651 fail: 1652 URTW_UNLOCK(sc); 1653 1654 sc->sc_curchan = ic->ic_curchan; 1655 1656 if (error != 0) 1657 device_printf(sc->sc_dev, "could not change the channel\n"); 1658 } 1659 1660 static void 1661 urtw_update_promisc(struct ieee80211com *ic) 1662 { 1663 struct urtw_softc *sc = ic->ic_softc; 1664 1665 URTW_LOCK(sc); 1666 if (sc->sc_flags & URTW_RUNNING) 1667 urtw_rx_setconf(sc); 1668 URTW_UNLOCK(sc); 1669 } 1670 1671 static void 1672 urtw_update_mcast(struct ieee80211com *ic) 1673 { 1674 1675 /* XXX do nothing? */ 1676 } 1677 1678 static int 1679 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1680 struct urtw_data *data, int prior) 1681 { 1682 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1683 struct ieee80211_key *k; 1684 const struct ieee80211_txparam *tp = ni->ni_txparms; 1685 struct ieee80211com *ic = &sc->sc_ic; 1686 struct ieee80211vap *vap = ni->ni_vap; 1687 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1688 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1689 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1690 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1691 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1692 }; 1693 struct usb_xfer *xfer; 1694 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type, 1695 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast; 1696 uint16_t acktime, rtstime, ctstime; 1697 uint32_t flags; 1698 usb_error_t error; 1699 1700 URTW_ASSERT_LOCKED(sc); 1701 1702 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1703 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1704 1705 /* 1706 * Software crypto. 1707 */ 1708 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1709 k = ieee80211_crypto_encap(ni, m0); 1710 if (k == NULL) { 1711 device_printf(sc->sc_dev, 1712 "ieee80211_crypto_encap returns NULL.\n"); 1713 /* XXX we don't expect the fragmented frames */ 1714 m_freem(m0); 1715 return (ENOBUFS); 1716 } 1717 1718 /* in case packet header moved, reset pointer */ 1719 wh = mtod(m0, struct ieee80211_frame *); 1720 } 1721 1722 if (ieee80211_radiotap_active_vap(vap)) { 1723 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1724 1725 tap->wt_flags = 0; 1726 ieee80211_radiotap_tx(vap, m0); 1727 } 1728 1729 if (type == IEEE80211_FC0_TYPE_MGT || 1730 type == IEEE80211_FC0_TYPE_CTL || 1731 (m0->m_flags & M_EAPOL) != 0) { 1732 rate = tp->mgmtrate; 1733 } else { 1734 /* for data frames */ 1735 if (ismcast) 1736 rate = tp->mcastrate; 1737 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1738 rate = tp->ucastrate; 1739 else 1740 rate = urtw_rtl2rate(sc->sc_currate); 1741 } 1742 1743 sc->sc_stats.txrates[sc->sc_currate]++; 1744 1745 if (ismcast) 1746 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1747 IEEE80211_CRC_LEN, rate, 0, 0); 1748 else { 1749 acktime = urtw_compute_txtime(14, 2,0, 0); 1750 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1751 rtsenable = 1; 1752 ctsenable = 0; 1753 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1754 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1755 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1756 IEEE80211_CRC_LEN, rate, 0, isshort); 1757 rtsdur = ctstime + pkttime + acktime + 1758 3 * URTW_ASIFS_TIME; 1759 txdur = rtstime + rtsdur; 1760 } else { 1761 rtsenable = ctsenable = rtsdur = 0; 1762 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1763 IEEE80211_CRC_LEN, rate, 0, isshort); 1764 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1765 } 1766 1767 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1768 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1769 IEEE80211_CRC_LEN, rate, 0, isshort) + 1770 3 * URTW_ASIFS_TIME + 1771 2 * acktime; 1772 else 1773 dur = URTW_ASIFS_TIME + acktime; 1774 } 1775 USETW(wh->i_dur, dur); 1776 1777 xferlen = m0->m_pkthdr.len; 1778 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1779 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1780 xferlen += 1; 1781 1782 memset(data->buf, 0, URTW_TX_MAXSIZE); 1783 flags = m0->m_pkthdr.len & 0xfff; 1784 flags |= URTW_TX_FLAG_NO_ENC; 1785 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1786 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1787 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1788 (sc->sc_currate != 0)) 1789 flags |= URTW_TX_FLAG_SPLCP; 1790 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1791 flags |= URTW_TX_FLAG_MOREFRAG; 1792 1793 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1794 1795 if (sc->sc_flags & URTW_RTL8187B) { 1796 struct urtw_8187b_txhdr *tx; 1797 1798 tx = (struct urtw_8187b_txhdr *)data->buf; 1799 if (ctsenable) 1800 flags |= URTW_TX_FLAG_CTS; 1801 if (rtsenable) { 1802 flags |= URTW_TX_FLAG_RTS; 1803 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1804 tx->rtsdur = rtsdur; 1805 } 1806 tx->flag = htole32(flags); 1807 tx->txdur = txdur; 1808 if (type == IEEE80211_FC0_TYPE_MGT && 1809 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1810 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1811 tx->retry = 1; 1812 else 1813 tx->retry = URTW_TX_MAXRETRY; 1814 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1815 } else { 1816 struct urtw_8187l_txhdr *tx; 1817 1818 tx = (struct urtw_8187l_txhdr *)data->buf; 1819 if (rtsenable) { 1820 flags |= URTW_TX_FLAG_RTS; 1821 tx->rtsdur = rtsdur; 1822 } 1823 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1824 tx->flag = htole32(flags); 1825 tx->retry = 3; /* CW minimum */ 1826 tx->retry |= 7 << 4; /* CW maximum */ 1827 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */ 1828 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1829 } 1830 1831 data->buflen = xferlen; 1832 data->ni = ni; 1833 data->m = m0; 1834 1835 if (sc->sc_flags & URTW_RTL8187B) { 1836 switch (type) { 1837 case IEEE80211_FC0_TYPE_CTL: 1838 case IEEE80211_FC0_TYPE_MGT: 1839 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1840 break; 1841 default: 1842 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1843 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1844 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1845 break; 1846 } 1847 } else 1848 xfer = (prior == URTW_PRIORITY_LOW) ? 1849 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1850 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1851 1852 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1853 usbd_transfer_start(xfer); 1854 1855 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1856 if (error != 0) 1857 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1858 error); 1859 return (0); 1860 } 1861 1862 static int 1863 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1864 { 1865 struct ieee80211com *ic = vap->iv_ic; 1866 struct urtw_softc *sc = ic->ic_softc; 1867 struct urtw_vap *uvp = URTW_VAP(vap); 1868 struct ieee80211_node *ni; 1869 usb_error_t error = 0; 1870 1871 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1872 ieee80211_state_name[vap->iv_state], 1873 ieee80211_state_name[nstate]); 1874 1875 sc->sc_state = nstate; 1876 1877 IEEE80211_UNLOCK(ic); 1878 URTW_LOCK(sc); 1879 usb_callout_stop(&sc->sc_led_ch); 1880 callout_stop(&sc->sc_watchdog_ch); 1881 1882 switch (nstate) { 1883 case IEEE80211_S_INIT: 1884 case IEEE80211_S_SCAN: 1885 case IEEE80211_S_AUTH: 1886 case IEEE80211_S_ASSOC: 1887 break; 1888 case IEEE80211_S_RUN: 1889 ni = ieee80211_ref_node(vap->iv_bss); 1890 /* setting bssid. */ 1891 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1892 urtw_write16_m(sc, URTW_BSSID + 4, 1893 ((uint16_t *)ni->ni_bssid)[2]); 1894 urtw_update_msr(sc); 1895 /* XXX maybe the below would be incorrect. */ 1896 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1897 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1898 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1899 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1900 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1901 if (error != 0) 1902 device_printf(sc->sc_dev, 1903 "could not control LED (%d)\n", error); 1904 ieee80211_free_node(ni); 1905 break; 1906 default: 1907 break; 1908 } 1909 fail: 1910 URTW_UNLOCK(sc); 1911 IEEE80211_LOCK(ic); 1912 return (uvp->newstate(vap, nstate, arg)); 1913 } 1914 1915 static void 1916 urtw_watchdog(void *arg) 1917 { 1918 struct urtw_softc *sc = arg; 1919 struct ieee80211com *ic = &sc->sc_ic; 1920 1921 if (sc->sc_txtimer > 0) { 1922 if (--sc->sc_txtimer == 0) { 1923 device_printf(sc->sc_dev, "device timeout\n"); 1924 counter_u64_add(ic->ic_oerrors, 1); 1925 ieee80211_restart_all(ic); 1926 return; 1927 } 1928 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1929 } 1930 } 1931 1932 static void 1933 urtw_set_multi(void *arg) 1934 { 1935 /* XXX don't know how to set a device. Lack of docs. */ 1936 } 1937 1938 static usb_error_t 1939 urtw_set_rate(struct urtw_softc *sc) 1940 { 1941 int i, basic_rate, min_rr_rate, max_rr_rate; 1942 uint16_t data; 1943 usb_error_t error; 1944 1945 basic_rate = URTW_RIDX_OFDM24; 1946 min_rr_rate = URTW_RIDX_OFDM6; 1947 max_rr_rate = URTW_RIDX_OFDM24; 1948 1949 urtw_write8_m(sc, URTW_RESP_RATE, 1950 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1951 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1952 1953 urtw_read16_m(sc, URTW_BRSR, &data); 1954 data &= ~URTW_BRSR_MBR_8185; 1955 1956 for (i = 0; i <= basic_rate; i++) 1957 data |= (1 << i); 1958 1959 urtw_write16_m(sc, URTW_BRSR, data); 1960 fail: 1961 return (error); 1962 } 1963 1964 static uint16_t 1965 urtw_rtl2rate(uint32_t rate) 1966 { 1967 unsigned i; 1968 1969 for (i = 0; i < nitems(urtw_ratetable); i++) { 1970 if (rate == urtw_ratetable[i].val) 1971 return urtw_ratetable[i].reg; 1972 } 1973 1974 return (0); 1975 } 1976 1977 static usb_error_t 1978 urtw_update_msr(struct urtw_softc *sc) 1979 { 1980 struct ieee80211com *ic = &sc->sc_ic; 1981 uint8_t data; 1982 usb_error_t error; 1983 1984 urtw_read8_m(sc, URTW_MSR, &data); 1985 data &= ~URTW_MSR_LINK_MASK; 1986 1987 if (sc->sc_state == IEEE80211_S_RUN) { 1988 switch (ic->ic_opmode) { 1989 case IEEE80211_M_STA: 1990 case IEEE80211_M_MONITOR: 1991 data |= URTW_MSR_LINK_STA; 1992 if (sc->sc_flags & URTW_RTL8187B) 1993 data |= URTW_MSR_LINK_ENEDCA; 1994 break; 1995 case IEEE80211_M_IBSS: 1996 data |= URTW_MSR_LINK_ADHOC; 1997 break; 1998 case IEEE80211_M_HOSTAP: 1999 data |= URTW_MSR_LINK_HOSTAP; 2000 break; 2001 default: 2002 DPRINTF(sc, URTW_DEBUG_STATE, 2003 "unsupported operation mode 0x%x\n", 2004 ic->ic_opmode); 2005 error = USB_ERR_INVAL; 2006 goto fail; 2007 } 2008 } else 2009 data |= URTW_MSR_LINK_NONE; 2010 2011 urtw_write8_m(sc, URTW_MSR, data); 2012 fail: 2013 return (error); 2014 } 2015 2016 static usb_error_t 2017 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 2018 { 2019 struct usb_device_request req; 2020 usb_error_t error; 2021 2022 URTW_ASSERT_LOCKED(sc); 2023 2024 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2025 req.bRequest = URTW_8187_GETREGS_REQ; 2026 USETW(req.wValue, (val & 0xff) | 0xff00); 2027 USETW(req.wIndex, (val >> 8) & 0x3); 2028 USETW(req.wLength, sizeof(uint8_t)); 2029 2030 error = urtw_do_request(sc, &req, data); 2031 return (error); 2032 } 2033 2034 static usb_error_t 2035 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 2036 { 2037 struct usb_device_request req; 2038 usb_error_t error; 2039 2040 URTW_ASSERT_LOCKED(sc); 2041 2042 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2043 req.bRequest = URTW_8187_GETREGS_REQ; 2044 USETW(req.wValue, (val & 0xff) | 0xff00); 2045 USETW(req.wIndex, (val >> 8) & 0x3); 2046 USETW(req.wLength, sizeof(uint16_t)); 2047 2048 error = urtw_do_request(sc, &req, data); 2049 return (error); 2050 } 2051 2052 static usb_error_t 2053 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2054 { 2055 struct usb_device_request req; 2056 usb_error_t error; 2057 2058 URTW_ASSERT_LOCKED(sc); 2059 2060 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2061 req.bRequest = URTW_8187_GETREGS_REQ; 2062 USETW(req.wValue, (val & 0xff) | 0xff00); 2063 USETW(req.wIndex, (val >> 8) & 0x3); 2064 USETW(req.wLength, sizeof(uint32_t)); 2065 2066 error = urtw_do_request(sc, &req, data); 2067 return (error); 2068 } 2069 2070 static usb_error_t 2071 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2072 { 2073 struct usb_device_request req; 2074 2075 URTW_ASSERT_LOCKED(sc); 2076 2077 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2078 req.bRequest = URTW_8187_SETREGS_REQ; 2079 USETW(req.wValue, (val & 0xff) | 0xff00); 2080 USETW(req.wIndex, (val >> 8) & 0x3); 2081 USETW(req.wLength, sizeof(uint8_t)); 2082 2083 return (urtw_do_request(sc, &req, &data)); 2084 } 2085 2086 static usb_error_t 2087 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2088 { 2089 struct usb_device_request req; 2090 2091 URTW_ASSERT_LOCKED(sc); 2092 2093 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2094 req.bRequest = URTW_8187_SETREGS_REQ; 2095 USETW(req.wValue, (val & 0xff) | 0xff00); 2096 USETW(req.wIndex, (val >> 8) & 0x3); 2097 USETW(req.wLength, sizeof(uint16_t)); 2098 2099 return (urtw_do_request(sc, &req, &data)); 2100 } 2101 2102 static usb_error_t 2103 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2104 { 2105 struct usb_device_request req; 2106 2107 URTW_ASSERT_LOCKED(sc); 2108 2109 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2110 req.bRequest = URTW_8187_SETREGS_REQ; 2111 USETW(req.wValue, (val & 0xff) | 0xff00); 2112 USETW(req.wIndex, (val >> 8) & 0x3); 2113 USETW(req.wLength, sizeof(uint32_t)); 2114 2115 return (urtw_do_request(sc, &req, &data)); 2116 } 2117 2118 static usb_error_t 2119 urtw_get_macaddr(struct urtw_softc *sc) 2120 { 2121 struct ieee80211com *ic = &sc->sc_ic; 2122 uint32_t data; 2123 usb_error_t error; 2124 2125 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2126 if (error != 0) 2127 goto fail; 2128 ic->ic_macaddr[0] = data & 0xff; 2129 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2130 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2131 if (error != 0) 2132 goto fail; 2133 ic->ic_macaddr[2] = data & 0xff; 2134 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2135 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2136 if (error != 0) 2137 goto fail; 2138 ic->ic_macaddr[4] = data & 0xff; 2139 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2140 fail: 2141 return (error); 2142 } 2143 2144 static usb_error_t 2145 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2146 { 2147 #define URTW_READCMD_LEN 3 2148 int addrlen, i; 2149 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2150 usb_error_t error; 2151 2152 /* NB: make sure the buffer is initialized */ 2153 *data = 0; 2154 2155 /* enable EPROM programming */ 2156 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2157 DELAY(URTW_EPROM_DELAY); 2158 2159 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2160 if (error != 0) 2161 goto fail; 2162 error = urtw_eprom_ck(sc); 2163 if (error != 0) 2164 goto fail; 2165 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2166 if (error != 0) 2167 goto fail; 2168 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2169 addrlen = 8; 2170 addrstr[0] = addr & (1 << 7); 2171 addrstr[1] = addr & (1 << 6); 2172 addrstr[2] = addr & (1 << 5); 2173 addrstr[3] = addr & (1 << 4); 2174 addrstr[4] = addr & (1 << 3); 2175 addrstr[5] = addr & (1 << 2); 2176 addrstr[6] = addr & (1 << 1); 2177 addrstr[7] = addr & (1 << 0); 2178 } else { 2179 addrlen=6; 2180 addrstr[0] = addr & (1 << 5); 2181 addrstr[1] = addr & (1 << 4); 2182 addrstr[2] = addr & (1 << 3); 2183 addrstr[3] = addr & (1 << 2); 2184 addrstr[4] = addr & (1 << 1); 2185 addrstr[5] = addr & (1 << 0); 2186 } 2187 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2188 if (error != 0) 2189 goto fail; 2190 2191 error = urtw_eprom_writebit(sc, 0); 2192 if (error != 0) 2193 goto fail; 2194 2195 for (i = 0; i < 16; i++) { 2196 error = urtw_eprom_ck(sc); 2197 if (error != 0) 2198 goto fail; 2199 error = urtw_eprom_readbit(sc, &data16); 2200 if (error != 0) 2201 goto fail; 2202 2203 (*data) |= (data16 << (15 - i)); 2204 } 2205 2206 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2207 if (error != 0) 2208 goto fail; 2209 error = urtw_eprom_ck(sc); 2210 if (error != 0) 2211 goto fail; 2212 2213 /* now disable EPROM programming */ 2214 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2215 fail: 2216 return (error); 2217 #undef URTW_READCMD_LEN 2218 } 2219 2220 static usb_error_t 2221 urtw_eprom_cs(struct urtw_softc *sc, int able) 2222 { 2223 uint8_t data; 2224 usb_error_t error; 2225 2226 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2227 if (able == URTW_EPROM_ENABLE) 2228 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2229 else 2230 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2231 DELAY(URTW_EPROM_DELAY); 2232 fail: 2233 return (error); 2234 } 2235 2236 static usb_error_t 2237 urtw_eprom_ck(struct urtw_softc *sc) 2238 { 2239 uint8_t data; 2240 usb_error_t error; 2241 2242 /* masking */ 2243 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2244 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2245 DELAY(URTW_EPROM_DELAY); 2246 /* unmasking */ 2247 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2248 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2249 DELAY(URTW_EPROM_DELAY); 2250 fail: 2251 return (error); 2252 } 2253 2254 static usb_error_t 2255 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2256 { 2257 uint8_t data8; 2258 usb_error_t error; 2259 2260 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2261 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2262 DELAY(URTW_EPROM_DELAY); 2263 2264 fail: 2265 return (error); 2266 } 2267 2268 static usb_error_t 2269 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2270 { 2271 uint8_t data; 2272 usb_error_t error; 2273 2274 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2275 if (bit != 0) 2276 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2277 else 2278 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2279 DELAY(URTW_EPROM_DELAY); 2280 fail: 2281 return (error); 2282 } 2283 2284 static usb_error_t 2285 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2286 { 2287 int i = 0; 2288 usb_error_t error = 0; 2289 2290 for (i = 0; i < buflen; i++) { 2291 error = urtw_eprom_writebit(sc, buf[i]); 2292 if (error != 0) 2293 goto fail; 2294 error = urtw_eprom_ck(sc); 2295 if (error != 0) 2296 goto fail; 2297 } 2298 fail: 2299 return (error); 2300 } 2301 2302 static usb_error_t 2303 urtw_get_txpwr(struct urtw_softc *sc) 2304 { 2305 int i, j; 2306 uint32_t data; 2307 usb_error_t error; 2308 2309 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2310 if (error != 0) 2311 goto fail; 2312 sc->sc_txpwr_cck_base = data & 0xf; 2313 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2314 2315 for (i = 1, j = 0; i < 6; i += 2, j++) { 2316 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2317 if (error != 0) 2318 goto fail; 2319 sc->sc_txpwr_cck[i] = data & 0xf; 2320 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2321 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2322 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2323 } 2324 for (i = 1, j = 0; i < 4; i += 2, j++) { 2325 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2326 if (error != 0) 2327 goto fail; 2328 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2329 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2330 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2331 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2332 } 2333 if (sc->sc_flags & URTW_RTL8187B) { 2334 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2335 if (error != 0) 2336 goto fail; 2337 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2338 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2339 error = urtw_eprom_read32(sc, 0x0a, &data); 2340 if (error != 0) 2341 goto fail; 2342 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2343 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2344 error = urtw_eprom_read32(sc, 0x1c, &data); 2345 if (error != 0) 2346 goto fail; 2347 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2348 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2349 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2350 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2351 } else { 2352 for (i = 1, j = 0; i < 4; i += 2, j++) { 2353 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2354 &data); 2355 if (error != 0) 2356 goto fail; 2357 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2358 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2359 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2360 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2361 } 2362 } 2363 fail: 2364 return (error); 2365 } 2366 2367 static usb_error_t 2368 urtw_get_rfchip(struct urtw_softc *sc) 2369 { 2370 int ret; 2371 uint8_t data8; 2372 uint32_t data; 2373 usb_error_t error; 2374 2375 if (sc->sc_flags & URTW_RTL8187B) { 2376 urtw_read8_m(sc, 0xe1, &data8); 2377 switch (data8) { 2378 case 0: 2379 sc->sc_flags |= URTW_RTL8187B_REV_B; 2380 break; 2381 case 1: 2382 sc->sc_flags |= URTW_RTL8187B_REV_D; 2383 break; 2384 case 2: 2385 sc->sc_flags |= URTW_RTL8187B_REV_E; 2386 break; 2387 default: 2388 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2389 sc->sc_flags |= URTW_RTL8187B_REV_B; 2390 break; 2391 } 2392 } else { 2393 urtw_read32_m(sc, URTW_TX_CONF, &data); 2394 switch (data & URTW_TX_HWMASK) { 2395 case URTW_TX_R8187vD_B: 2396 sc->sc_flags |= URTW_RTL8187B; 2397 break; 2398 case URTW_TX_R8187vD: 2399 break; 2400 default: 2401 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2402 data & URTW_TX_HWMASK); 2403 break; 2404 } 2405 } 2406 2407 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2408 if (error != 0) 2409 goto fail; 2410 switch (data & 0xff) { 2411 case URTW_EPROM_RFCHIPID_RTL8225U: 2412 error = urtw_8225_isv2(sc, &ret); 2413 if (error != 0) 2414 goto fail; 2415 if (ret == 0) { 2416 sc->sc_rf_init = urtw_8225_rf_init; 2417 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2418 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2419 sc->sc_rf_stop = urtw_8225_rf_stop; 2420 } else { 2421 sc->sc_rf_init = urtw_8225v2_rf_init; 2422 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2423 sc->sc_rf_stop = urtw_8225_rf_stop; 2424 } 2425 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2426 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2427 break; 2428 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2429 sc->sc_rf_init = urtw_8225v2b_rf_init; 2430 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2431 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2432 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2433 sc->sc_rf_stop = urtw_8225_rf_stop; 2434 break; 2435 default: 2436 DPRINTF(sc, URTW_DEBUG_STATE, 2437 "unsupported RF chip %d\n", data & 0xff); 2438 error = USB_ERR_INVAL; 2439 goto fail; 2440 } 2441 2442 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2443 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2444 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2445 "rtl8225z2", 2446 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2447 (data8 == 1) ? "d" : "e") : "none"); 2448 2449 fail: 2450 return (error); 2451 } 2452 2453 static usb_error_t 2454 urtw_led_init(struct urtw_softc *sc) 2455 { 2456 uint32_t rev; 2457 usb_error_t error; 2458 2459 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2460 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2461 if (error != 0) 2462 goto fail; 2463 2464 switch (rev & URTW_EPROM_CID_MASK) { 2465 case URTW_EPROM_CID_ALPHA0: 2466 sc->sc_strategy = URTW_SW_LED_MODE1; 2467 break; 2468 case URTW_EPROM_CID_SERCOMM_PS: 2469 sc->sc_strategy = URTW_SW_LED_MODE3; 2470 break; 2471 case URTW_EPROM_CID_HW_LED: 2472 sc->sc_strategy = URTW_HW_LED; 2473 break; 2474 case URTW_EPROM_CID_RSVD0: 2475 case URTW_EPROM_CID_RSVD1: 2476 default: 2477 sc->sc_strategy = URTW_SW_LED_MODE0; 2478 break; 2479 } 2480 2481 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2482 2483 fail: 2484 return (error); 2485 } 2486 2487 static usb_error_t 2488 urtw_8225_rf_init(struct urtw_softc *sc) 2489 { 2490 unsigned i; 2491 uint16_t data; 2492 usb_error_t error; 2493 2494 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2495 if (error) 2496 goto fail; 2497 2498 error = urtw_8225_usb_init(sc); 2499 if (error) 2500 goto fail; 2501 2502 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2503 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2504 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2505 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2506 2507 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2508 if (error) 2509 goto fail; 2510 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2511 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2512 if (error) 2513 goto fail; 2514 2515 error = urtw_8185_rf_pins_enable(sc); 2516 if (error) 2517 goto fail; 2518 urtw_pause_ms(sc, 1000); 2519 2520 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2521 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2522 urtw_8225_rf_part1[i].val); 2523 urtw_pause_ms(sc, 1); 2524 } 2525 urtw_pause_ms(sc, 100); 2526 urtw_8225_write(sc, 2527 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2528 urtw_pause_ms(sc, 200); 2529 urtw_8225_write(sc, 2530 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2531 urtw_pause_ms(sc, 200); 2532 urtw_8225_write(sc, 2533 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2534 2535 for (i = 0; i < 95; i++) { 2536 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2537 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2538 } 2539 2540 urtw_8225_write(sc, 2541 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2542 urtw_8225_write(sc, 2543 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2544 2545 for (i = 0; i < 128; i++) { 2546 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2547 urtw_pause_ms(sc, 1); 2548 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2549 urtw_pause_ms(sc, 1); 2550 } 2551 2552 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2553 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2554 urtw_8225_rf_part2[i].val); 2555 urtw_pause_ms(sc, 1); 2556 } 2557 2558 error = urtw_8225_setgain(sc, 4); 2559 if (error) 2560 goto fail; 2561 2562 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2563 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2564 urtw_8225_rf_part3[i].val); 2565 urtw_pause_ms(sc, 1); 2566 } 2567 2568 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2569 2570 error = urtw_8225_set_txpwrlvl(sc, 1); 2571 if (error) 2572 goto fail; 2573 2574 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2575 urtw_pause_ms(sc, 1); 2576 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2577 urtw_pause_ms(sc, 1); 2578 2579 /* TX ant A, 0x0 for B */ 2580 error = urtw_8185_tx_antenna(sc, 0x3); 2581 if (error) 2582 goto fail; 2583 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2584 2585 error = urtw_8225_rf_set_chan(sc, 1); 2586 fail: 2587 return (error); 2588 } 2589 2590 static usb_error_t 2591 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2592 { 2593 usb_error_t error = 0; 2594 2595 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2596 fail: 2597 return (error); 2598 } 2599 2600 static usb_error_t 2601 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2602 { 2603 usb_error_t error; 2604 2605 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2606 urtw_pause_ms(sc, 1); 2607 fail: 2608 return (error); 2609 } 2610 2611 static usb_error_t 2612 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2613 { 2614 2615 data = data & 0xff; 2616 return urtw_8187_write_phy(sc, addr, data); 2617 } 2618 2619 static usb_error_t 2620 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2621 { 2622 2623 data = data & 0xff; 2624 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2625 } 2626 2627 static usb_error_t 2628 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2629 { 2630 uint32_t phyw; 2631 usb_error_t error; 2632 2633 phyw = ((data << 8) | (addr | 0x80)); 2634 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2635 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2636 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2637 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2638 urtw_pause_ms(sc, 1); 2639 fail: 2640 return (error); 2641 } 2642 2643 static usb_error_t 2644 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2645 { 2646 usb_error_t error; 2647 2648 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2649 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2650 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2651 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2652 fail: 2653 return (error); 2654 } 2655 2656 static usb_error_t 2657 urtw_8225_usb_init(struct urtw_softc *sc) 2658 { 2659 uint8_t data; 2660 usb_error_t error; 2661 2662 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2663 urtw_write8_m(sc, URTW_GPIO, 0); 2664 error = urtw_read8e(sc, 0x53, &data); 2665 if (error) 2666 goto fail; 2667 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2668 if (error) 2669 goto fail; 2670 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2671 urtw_write8_m(sc, URTW_GPIO, 0x20); 2672 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2673 2674 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2675 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2676 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2677 2678 urtw_pause_ms(sc, 500); 2679 fail: 2680 return (error); 2681 } 2682 2683 static usb_error_t 2684 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2685 { 2686 uint16_t d80, d82, d84; 2687 usb_error_t error; 2688 2689 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2690 d80 &= URTW_RF_PINS_MAGIC1; 2691 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2692 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2693 d84 &= URTW_RF_PINS_MAGIC2; 2694 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2695 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2696 DELAY(10); 2697 2698 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2699 DELAY(2); 2700 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2701 DELAY(10); 2702 2703 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2704 if (error != 0) 2705 goto fail; 2706 2707 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2708 DELAY(10); 2709 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2710 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2711 urtw_pause_ms(sc, 2); 2712 fail: 2713 return (error); 2714 } 2715 2716 static usb_error_t 2717 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2718 uint16_t *data) 2719 { 2720 uint8_t buf[2]; 2721 uint16_t data16; 2722 struct usb_device_request req; 2723 usb_error_t error = 0; 2724 2725 data16 = *data; 2726 2727 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2728 req.bRequest = URTW_8187_SETREGS_REQ; 2729 USETW(req.wValue, addr); 2730 USETW(req.wIndex, index); 2731 USETW(req.wLength, sizeof(uint16_t)); 2732 buf[0] = (data16 & 0x00ff); 2733 buf[1] = (data16 & 0xff00) >> 8; 2734 2735 error = urtw_do_request(sc, &req, buf); 2736 2737 return (error); 2738 } 2739 2740 static usb_error_t 2741 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2742 { 2743 usb_error_t error; 2744 2745 error = urtw_8225_set_txpwrlvl(sc, chan); 2746 if (error) 2747 goto fail; 2748 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2749 urtw_pause_ms(sc, 10); 2750 fail: 2751 return (error); 2752 } 2753 2754 static usb_error_t 2755 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2756 { 2757 usb_error_t error; 2758 2759 if (sens < 0 || sens > 6) 2760 return -1; 2761 2762 if (sens > 4) 2763 urtw_8225_write(sc, 2764 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2765 else 2766 urtw_8225_write(sc, 2767 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2768 2769 sens = 6 - sens; 2770 error = urtw_8225_setgain(sc, sens); 2771 if (error) 2772 goto fail; 2773 2774 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2775 2776 fail: 2777 return (error); 2778 } 2779 2780 static usb_error_t 2781 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2782 { 2783 int i, idx, set; 2784 uint8_t *cck_pwltable; 2785 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2786 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2787 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2788 usb_error_t error; 2789 2790 cck_pwrlvl_max = 11; 2791 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2792 ofdm_pwrlvl_min = 10; 2793 2794 /* CCK power setting */ 2795 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2796 idx = cck_pwrlvl % 6; 2797 set = cck_pwrlvl / 6; 2798 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2799 urtw_8225_txpwr_cck; 2800 2801 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2802 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2803 for (i = 0; i < 8; i++) { 2804 urtw_8187_write_phy_cck(sc, 0x44 + i, 2805 cck_pwltable[idx * 8 + i]); 2806 } 2807 urtw_pause_ms(sc, 1); 2808 2809 /* OFDM power setting */ 2810 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2811 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2812 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2813 2814 idx = ofdm_pwrlvl % 6; 2815 set = ofdm_pwrlvl / 6; 2816 2817 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2818 if (error) 2819 goto fail; 2820 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2821 urtw_8187_write_phy_ofdm(sc, 6, 0); 2822 urtw_8187_write_phy_ofdm(sc, 8, 0); 2823 2824 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2825 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2826 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2827 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2828 urtw_pause_ms(sc, 1); 2829 fail: 2830 return (error); 2831 } 2832 2833 static usb_error_t 2834 urtw_8225_rf_stop(struct urtw_softc *sc) 2835 { 2836 uint8_t data; 2837 usb_error_t error; 2838 2839 urtw_8225_write(sc, 0x4, 0x1f); 2840 2841 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2842 if (error) 2843 goto fail; 2844 2845 urtw_read8_m(sc, URTW_CONFIG3, &data); 2846 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2847 if (sc->sc_flags & URTW_RTL8187B) { 2848 urtw_write32_m(sc, URTW_ANAPARAM2, 2849 URTW_8187B_8225_ANAPARAM2_OFF); 2850 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2851 urtw_write32_m(sc, URTW_ANAPARAM3, 2852 URTW_8187B_8225_ANAPARAM3_OFF); 2853 } else { 2854 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2855 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2856 } 2857 2858 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2859 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2860 if (error) 2861 goto fail; 2862 2863 fail: 2864 return (error); 2865 } 2866 2867 static usb_error_t 2868 urtw_8225v2_rf_init(struct urtw_softc *sc) 2869 { 2870 unsigned i; 2871 uint16_t data; 2872 uint32_t data32; 2873 usb_error_t error; 2874 2875 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2876 if (error) 2877 goto fail; 2878 2879 error = urtw_8225_usb_init(sc); 2880 if (error) 2881 goto fail; 2882 2883 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2884 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2885 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2886 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2887 2888 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2889 if (error) 2890 goto fail; 2891 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2892 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2893 if (error) 2894 goto fail; 2895 2896 error = urtw_8185_rf_pins_enable(sc); 2897 if (error) 2898 goto fail; 2899 2900 urtw_pause_ms(sc, 500); 2901 2902 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2903 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2904 urtw_8225v2_rf_part1[i].val); 2905 } 2906 urtw_pause_ms(sc, 50); 2907 2908 urtw_8225_write(sc, 2909 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2910 2911 for (i = 0; i < 95; i++) { 2912 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2913 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2914 urtw_8225v2_rxgain[i]); 2915 } 2916 2917 urtw_8225_write(sc, 2918 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2919 urtw_8225_write(sc, 2920 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2921 urtw_8225_write(sc, 2922 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2923 urtw_8225_write(sc, 2924 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2925 urtw_pause_ms(sc, 100); 2926 urtw_8225_write(sc, 2927 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2928 urtw_pause_ms(sc, 100); 2929 2930 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2931 if (error != 0) 2932 goto fail; 2933 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2934 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2935 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2936 urtw_8225_write(sc, 2937 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2938 urtw_pause_ms(sc, 100); 2939 urtw_8225_write(sc, 2940 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2941 urtw_pause_ms(sc, 50); 2942 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2943 if (error != 0) 2944 goto fail; 2945 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2946 device_printf(sc->sc_dev, "RF calibration failed\n"); 2947 } 2948 urtw_pause_ms(sc, 100); 2949 2950 urtw_8225_write(sc, 2951 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2952 for (i = 0; i < 128; i++) { 2953 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2954 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2955 } 2956 2957 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2958 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2959 urtw_8225v2_rf_part2[i].val); 2960 } 2961 2962 error = urtw_8225v2_setgain(sc, 4); 2963 if (error) 2964 goto fail; 2965 2966 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2967 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2968 urtw_8225v2_rf_part3[i].val); 2969 } 2970 2971 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2972 2973 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2974 if (error) 2975 goto fail; 2976 2977 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2978 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2979 2980 /* TX ant A, 0x0 for B */ 2981 error = urtw_8185_tx_antenna(sc, 0x3); 2982 if (error) 2983 goto fail; 2984 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2985 2986 error = urtw_8225_rf_set_chan(sc, 1); 2987 fail: 2988 return (error); 2989 } 2990 2991 static usb_error_t 2992 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2993 { 2994 usb_error_t error; 2995 2996 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2997 if (error) 2998 goto fail; 2999 3000 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3001 urtw_pause_ms(sc, 10); 3002 fail: 3003 return (error); 3004 } 3005 3006 static usb_error_t 3007 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 3008 { 3009 int i; 3010 int16_t bit; 3011 uint8_t rlen = 12, wlen = 6; 3012 uint16_t o1, o2, o3, tmp; 3013 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 3014 uint32_t mask = 0x80000000, value = 0; 3015 usb_error_t error; 3016 3017 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 3018 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 3019 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 3020 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 3021 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 3022 o1 &= ~URTW_RF_PINS_MAGIC4; 3023 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 3024 DELAY(5); 3025 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 3026 DELAY(5); 3027 3028 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 3029 bit = ((d2w & mask) != 0) ? 1 : 0; 3030 3031 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3032 DELAY(2); 3033 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3034 URTW_BB_HOST_BANG_CLK); 3035 DELAY(2); 3036 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3037 URTW_BB_HOST_BANG_CLK); 3038 DELAY(2); 3039 mask = mask >> 1; 3040 if (i == 2) 3041 break; 3042 bit = ((d2w & mask) != 0) ? 1 : 0; 3043 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3044 URTW_BB_HOST_BANG_CLK); 3045 DELAY(2); 3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3047 URTW_BB_HOST_BANG_CLK); 3048 DELAY(2); 3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3050 DELAY(1); 3051 } 3052 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3053 URTW_BB_HOST_BANG_CLK); 3054 DELAY(2); 3055 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3056 DELAY(2); 3057 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3058 DELAY(2); 3059 3060 mask = 0x800; 3061 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3063 o1 | URTW_BB_HOST_BANG_RW); 3064 DELAY(2); 3065 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3066 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3067 DELAY(2); 3068 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3069 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3070 DELAY(2); 3071 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3072 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3073 DELAY(2); 3074 3075 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3076 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3077 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3078 o1 | URTW_BB_HOST_BANG_RW); 3079 DELAY(2); 3080 } 3081 3082 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3083 URTW_BB_HOST_BANG_RW); 3084 DELAY(2); 3085 3086 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3087 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3088 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3089 3090 if (data != NULL) 3091 *data = value; 3092 fail: 3093 return (error); 3094 } 3095 3096 static usb_error_t 3097 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3098 { 3099 int i; 3100 uint8_t *cck_pwrtable; 3101 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3102 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3103 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3104 usb_error_t error; 3105 3106 /* CCK power setting */ 3107 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3108 cck_pwrlvl += sc->sc_txpwr_cck_base; 3109 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3110 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3111 urtw_8225v2_txpwr_cck; 3112 3113 for (i = 0; i < 8; i++) 3114 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3115 3116 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3117 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3118 urtw_pause_ms(sc, 1); 3119 3120 /* OFDM power setting */ 3121 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3122 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3123 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3124 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3125 3126 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3127 if (error) 3128 goto fail; 3129 3130 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3131 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3132 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3133 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3134 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3135 3136 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3137 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3138 urtw_pause_ms(sc, 1); 3139 fail: 3140 return (error); 3141 } 3142 3143 static usb_error_t 3144 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3145 { 3146 uint8_t *gainp; 3147 usb_error_t error; 3148 3149 /* XXX for A? */ 3150 gainp = urtw_8225v2_gain_bg; 3151 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3152 urtw_pause_ms(sc, 1); 3153 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3154 urtw_pause_ms(sc, 1); 3155 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3156 urtw_pause_ms(sc, 1); 3157 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3158 urtw_pause_ms(sc, 1); 3159 fail: 3160 return (error); 3161 } 3162 3163 static usb_error_t 3164 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3165 { 3166 uint32_t data; 3167 usb_error_t error; 3168 3169 *ret = 1; 3170 3171 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3172 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3173 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3174 urtw_pause_ms(sc, 500); 3175 3176 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3177 URTW_8225_ADDR_0_DATA_MAGIC1); 3178 3179 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3180 if (error != 0) 3181 goto fail; 3182 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3183 *ret = 0; 3184 else { 3185 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3186 if (error != 0) 3187 goto fail; 3188 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3189 *ret = 0; 3190 } 3191 3192 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3193 URTW_8225_ADDR_0_DATA_MAGIC2); 3194 fail: 3195 return (error); 3196 } 3197 3198 static usb_error_t 3199 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3200 { 3201 struct ieee80211com *ic = &sc->sc_ic; 3202 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3203 const uint8_t *macaddr; 3204 unsigned i; 3205 uint8_t data8; 3206 usb_error_t error; 3207 3208 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3209 if (error) 3210 goto fail; 3211 3212 /* 3213 * initialize extra registers on 8187 3214 */ 3215 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3216 3217 /* retry limit */ 3218 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3219 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3220 urtw_write8_m(sc, URTW_CW_CONF, data8); 3221 3222 /* TX AGC */ 3223 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3224 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3225 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3226 3227 /* Auto Rate Fallback Control */ 3228 #define URTW_ARFR 0x1e0 3229 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3230 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3231 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3232 data8 | URTW_RATE_FALLBACK_ENABLE); 3233 3234 urtw_read8_m(sc, URTW_MSR, &data8); 3235 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3236 urtw_read8_m(sc, URTW_MSR, &data8); 3237 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3238 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3239 3240 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3241 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3242 #define URTW_FEMR_FOR_8187B 0x1d4 3243 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3244 3245 /* led type */ 3246 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3247 data8 = (data8 & 0x3f) | 0x80; 3248 urtw_write8_m(sc, URTW_CONFIG1, data8); 3249 3250 /* applying MAC address again. */ 3251 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 3252 error = urtw_set_macaddr(sc, macaddr); 3253 if (error) 3254 goto fail; 3255 3256 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3257 if (error) 3258 goto fail; 3259 3260 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3261 3262 /* 3263 * MAC configuration 3264 */ 3265 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3266 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3267 urtw_8225v2b_rf_part1[i].val); 3268 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3269 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3270 urtw_write32_m(sc, 0x1f0, 0); 3271 urtw_write32_m(sc, 0x1f4, 0); 3272 urtw_write8_m(sc, 0x1f8, 0); 3273 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3274 3275 #define URTW_RFSW_CTRL 0x272 3276 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3277 3278 /* 3279 * initialize PHY 3280 */ 3281 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3282 if (error) 3283 goto fail; 3284 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3285 urtw_write8_m(sc, URTW_CONFIG3, 3286 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3287 3288 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3289 if (error) 3290 goto fail; 3291 3292 /* setup RFE initial timing */ 3293 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3294 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3295 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3296 urtw_pause_ms(sc, 1100); 3297 3298 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3299 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3300 urtw_8225v2b_rf_part0[i].val); 3301 urtw_pause_ms(sc, 1); 3302 } 3303 urtw_8225_write(sc, 0x00, 0x01b7); 3304 3305 for (i = 0; i < 95; i++) { 3306 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3307 urtw_pause_ms(sc, 1); 3308 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3309 urtw_8225v2b_rxgain[i]); 3310 urtw_pause_ms(sc, 1); 3311 } 3312 3313 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3314 urtw_pause_ms(sc, 1); 3315 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3316 urtw_pause_ms(sc, 1); 3317 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3318 urtw_pause_ms(sc, 1); 3319 urtw_pause_ms(sc, 3000); 3320 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3321 urtw_pause_ms(sc, 2000); 3322 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3323 urtw_pause_ms(sc, 1); 3324 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3325 urtw_pause_ms(sc, 1); 3326 3327 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3328 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3329 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3330 3331 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3332 for (i = 0; i < 128; i++) { 3333 uint32_t addr, data; 3334 3335 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3336 addr = ((i + 0x80) << 8) | 0x0000008e; 3337 3338 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3339 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3340 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3341 } 3342 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3343 3344 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3345 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3346 3347 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3348 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3349 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3350 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3351 3352 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3353 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3354 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3355 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3356 3357 fail: 3358 return (error); 3359 } 3360 3361 static usb_error_t 3362 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3363 { 3364 usb_error_t error; 3365 3366 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3367 if (error) 3368 goto fail; 3369 3370 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3371 urtw_pause_ms(sc, 10); 3372 fail: 3373 return (error); 3374 } 3375 3376 static usb_error_t 3377 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3378 { 3379 int i; 3380 uint8_t *cck_pwrtable; 3381 uint8_t cck_pwrlvl_max = 15; 3382 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3383 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3384 usb_error_t error; 3385 3386 /* CCK power setting */ 3387 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3388 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3389 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3390 cck_pwrlvl += sc->sc_txpwr_cck_base; 3391 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3392 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3393 urtw_8225v2b_txpwr_cck; 3394 3395 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3396 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3397 ((cck_pwrlvl <= 11) ? 8 : 16); 3398 else 3399 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3400 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3401 3402 for (i = 0; i < 8; i++) 3403 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3404 3405 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3406 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3407 urtw_pause_ms(sc, 1); 3408 3409 /* OFDM power setting */ 3410 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3411 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3412 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3413 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3414 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3415 3416 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3417 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3418 3419 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3420 if (ofdm_pwrlvl <= 11) { 3421 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3422 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3423 } else { 3424 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3425 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3426 } 3427 } else { 3428 if (ofdm_pwrlvl <= 11) { 3429 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3430 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3431 } else if (ofdm_pwrlvl <= 17) { 3432 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3433 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3434 } else { 3435 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3436 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3437 } 3438 } 3439 urtw_pause_ms(sc, 1); 3440 fail: 3441 return (error); 3442 } 3443 3444 static usb_error_t 3445 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3446 { 3447 struct usb_device_request req; 3448 usb_error_t error; 3449 3450 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3451 req.bRequest = URTW_8187_GETREGS_REQ; 3452 USETW(req.wValue, val | 0xfe00); 3453 USETW(req.wIndex, 0); 3454 USETW(req.wLength, sizeof(uint8_t)); 3455 3456 error = urtw_do_request(sc, &req, data); 3457 return (error); 3458 } 3459 3460 static usb_error_t 3461 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3462 { 3463 struct usb_device_request req; 3464 3465 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3466 req.bRequest = URTW_8187_SETREGS_REQ; 3467 USETW(req.wValue, val | 0xfe00); 3468 USETW(req.wIndex, 0); 3469 USETW(req.wLength, sizeof(uint8_t)); 3470 3471 return (urtw_do_request(sc, &req, &data)); 3472 } 3473 3474 static usb_error_t 3475 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3476 { 3477 uint8_t data; 3478 usb_error_t error; 3479 3480 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3481 if (error) 3482 goto fail; 3483 3484 urtw_read8_m(sc, URTW_CONFIG3, &data); 3485 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3486 urtw_write32_m(sc, URTW_ANAPARAM, val); 3487 urtw_read8_m(sc, URTW_CONFIG3, &data); 3488 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3489 3490 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3491 if (error) 3492 goto fail; 3493 fail: 3494 return (error); 3495 } 3496 3497 static usb_error_t 3498 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3499 { 3500 uint8_t data; 3501 usb_error_t error; 3502 3503 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3504 if (error) 3505 goto fail; 3506 3507 urtw_read8_m(sc, URTW_CONFIG3, &data); 3508 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3509 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3510 urtw_read8_m(sc, URTW_CONFIG3, &data); 3511 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3512 3513 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3514 if (error) 3515 goto fail; 3516 fail: 3517 return (error); 3518 } 3519 3520 static usb_error_t 3521 urtw_intr_enable(struct urtw_softc *sc) 3522 { 3523 usb_error_t error; 3524 3525 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3526 fail: 3527 return (error); 3528 } 3529 3530 static usb_error_t 3531 urtw_intr_disable(struct urtw_softc *sc) 3532 { 3533 usb_error_t error; 3534 3535 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3536 fail: 3537 return (error); 3538 } 3539 3540 static usb_error_t 3541 urtw_reset(struct urtw_softc *sc) 3542 { 3543 uint8_t data; 3544 usb_error_t error; 3545 3546 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3547 if (error) 3548 goto fail; 3549 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3550 if (error) 3551 goto fail; 3552 3553 error = urtw_intr_disable(sc); 3554 if (error) 3555 goto fail; 3556 urtw_pause_ms(sc, 100); 3557 3558 error = urtw_write8e(sc, 0x18, 0x10); 3559 if (error != 0) 3560 goto fail; 3561 error = urtw_write8e(sc, 0x18, 0x11); 3562 if (error != 0) 3563 goto fail; 3564 error = urtw_write8e(sc, 0x18, 0x00); 3565 if (error != 0) 3566 goto fail; 3567 urtw_pause_ms(sc, 100); 3568 3569 urtw_read8_m(sc, URTW_CMD, &data); 3570 data = (data & 0x2) | URTW_CMD_RST; 3571 urtw_write8_m(sc, URTW_CMD, data); 3572 urtw_pause_ms(sc, 100); 3573 3574 urtw_read8_m(sc, URTW_CMD, &data); 3575 if (data & URTW_CMD_RST) { 3576 device_printf(sc->sc_dev, "reset timeout\n"); 3577 goto fail; 3578 } 3579 3580 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3581 if (error) 3582 goto fail; 3583 urtw_pause_ms(sc, 100); 3584 3585 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3586 if (error) 3587 goto fail; 3588 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3589 if (error) 3590 goto fail; 3591 fail: 3592 return (error); 3593 } 3594 3595 static usb_error_t 3596 urtw_led_ctl(struct urtw_softc *sc, int mode) 3597 { 3598 usb_error_t error = 0; 3599 3600 switch (sc->sc_strategy) { 3601 case URTW_SW_LED_MODE0: 3602 error = urtw_led_mode0(sc, mode); 3603 break; 3604 case URTW_SW_LED_MODE1: 3605 error = urtw_led_mode1(sc, mode); 3606 break; 3607 case URTW_SW_LED_MODE2: 3608 error = urtw_led_mode2(sc, mode); 3609 break; 3610 case URTW_SW_LED_MODE3: 3611 error = urtw_led_mode3(sc, mode); 3612 break; 3613 default: 3614 DPRINTF(sc, URTW_DEBUG_STATE, 3615 "unsupported LED mode %d\n", sc->sc_strategy); 3616 error = USB_ERR_INVAL; 3617 break; 3618 } 3619 3620 return (error); 3621 } 3622 3623 static usb_error_t 3624 urtw_led_mode0(struct urtw_softc *sc, int mode) 3625 { 3626 3627 switch (mode) { 3628 case URTW_LED_CTL_POWER_ON: 3629 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3630 break; 3631 case URTW_LED_CTL_TX: 3632 if (sc->sc_gpio_ledinprogress == 1) 3633 return (0); 3634 3635 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3636 sc->sc_gpio_blinktime = 2; 3637 break; 3638 case URTW_LED_CTL_LINK: 3639 sc->sc_gpio_ledstate = URTW_LED_ON; 3640 break; 3641 default: 3642 DPRINTF(sc, URTW_DEBUG_STATE, 3643 "unsupported LED mode 0x%x", mode); 3644 return (USB_ERR_INVAL); 3645 } 3646 3647 switch (sc->sc_gpio_ledstate) { 3648 case URTW_LED_ON: 3649 if (sc->sc_gpio_ledinprogress != 0) 3650 break; 3651 urtw_led_on(sc, URTW_LED_GPIO); 3652 break; 3653 case URTW_LED_BLINK_NORMAL: 3654 if (sc->sc_gpio_ledinprogress != 0) 3655 break; 3656 sc->sc_gpio_ledinprogress = 1; 3657 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3658 URTW_LED_OFF : URTW_LED_ON; 3659 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3660 break; 3661 case URTW_LED_POWER_ON_BLINK: 3662 urtw_led_on(sc, URTW_LED_GPIO); 3663 urtw_pause_ms(sc, 100); 3664 urtw_led_off(sc, URTW_LED_GPIO); 3665 break; 3666 default: 3667 DPRINTF(sc, URTW_DEBUG_STATE, 3668 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3669 return (USB_ERR_INVAL); 3670 } 3671 return (0); 3672 } 3673 3674 static usb_error_t 3675 urtw_led_mode1(struct urtw_softc *sc, int mode) 3676 { 3677 return (USB_ERR_INVAL); 3678 } 3679 3680 static usb_error_t 3681 urtw_led_mode2(struct urtw_softc *sc, int mode) 3682 { 3683 return (USB_ERR_INVAL); 3684 } 3685 3686 static usb_error_t 3687 urtw_led_mode3(struct urtw_softc *sc, int mode) 3688 { 3689 return (USB_ERR_INVAL); 3690 } 3691 3692 static usb_error_t 3693 urtw_led_on(struct urtw_softc *sc, int type) 3694 { 3695 usb_error_t error; 3696 3697 if (type == URTW_LED_GPIO) { 3698 switch (sc->sc_gpio_ledpin) { 3699 case URTW_LED_PIN_GPIO0: 3700 urtw_write8_m(sc, URTW_GPIO, 0x01); 3701 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3702 break; 3703 default: 3704 DPRINTF(sc, URTW_DEBUG_STATE, 3705 "unsupported LED PIN type 0x%x", 3706 sc->sc_gpio_ledpin); 3707 error = USB_ERR_INVAL; 3708 goto fail; 3709 } 3710 } else { 3711 DPRINTF(sc, URTW_DEBUG_STATE, 3712 "unsupported LED type 0x%x", type); 3713 error = USB_ERR_INVAL; 3714 goto fail; 3715 } 3716 3717 sc->sc_gpio_ledon = 1; 3718 fail: 3719 return (error); 3720 } 3721 3722 static usb_error_t 3723 urtw_led_off(struct urtw_softc *sc, int type) 3724 { 3725 usb_error_t error; 3726 3727 if (type == URTW_LED_GPIO) { 3728 switch (sc->sc_gpio_ledpin) { 3729 case URTW_LED_PIN_GPIO0: 3730 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3731 urtw_write8_m(sc, 3732 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3733 break; 3734 default: 3735 DPRINTF(sc, URTW_DEBUG_STATE, 3736 "unsupported LED PIN type 0x%x", 3737 sc->sc_gpio_ledpin); 3738 error = USB_ERR_INVAL; 3739 goto fail; 3740 } 3741 } else { 3742 DPRINTF(sc, URTW_DEBUG_STATE, 3743 "unsupported LED type 0x%x", type); 3744 error = USB_ERR_INVAL; 3745 goto fail; 3746 } 3747 3748 sc->sc_gpio_ledon = 0; 3749 3750 fail: 3751 return (error); 3752 } 3753 3754 static void 3755 urtw_led_ch(void *arg) 3756 { 3757 struct urtw_softc *sc = arg; 3758 struct ieee80211com *ic = &sc->sc_ic; 3759 3760 ieee80211_runtask(ic, &sc->sc_led_task); 3761 } 3762 3763 static void 3764 urtw_ledtask(void *arg, int pending) 3765 { 3766 struct urtw_softc *sc = arg; 3767 3768 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3769 DPRINTF(sc, URTW_DEBUG_STATE, 3770 "could not process a LED strategy 0x%x", 3771 sc->sc_strategy); 3772 return; 3773 } 3774 3775 URTW_LOCK(sc); 3776 urtw_led_blink(sc); 3777 URTW_UNLOCK(sc); 3778 } 3779 3780 static usb_error_t 3781 urtw_led_blink(struct urtw_softc *sc) 3782 { 3783 uint8_t ing = 0; 3784 3785 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3786 urtw_led_on(sc, URTW_LED_GPIO); 3787 else 3788 urtw_led_off(sc, URTW_LED_GPIO); 3789 sc->sc_gpio_blinktime--; 3790 if (sc->sc_gpio_blinktime == 0) 3791 ing = 1; 3792 else { 3793 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3794 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3795 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3796 ing = 1; 3797 } 3798 if (ing == 1) { 3799 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3800 sc->sc_gpio_ledon == 0) 3801 urtw_led_on(sc, URTW_LED_GPIO); 3802 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3803 sc->sc_gpio_ledon == 1) 3804 urtw_led_off(sc, URTW_LED_GPIO); 3805 3806 sc->sc_gpio_blinktime = 0; 3807 sc->sc_gpio_ledinprogress = 0; 3808 return (0); 3809 } 3810 3811 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3812 URTW_LED_ON : URTW_LED_OFF; 3813 3814 switch (sc->sc_gpio_ledstate) { 3815 case URTW_LED_BLINK_NORMAL: 3816 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3817 break; 3818 default: 3819 DPRINTF(sc, URTW_DEBUG_STATE, 3820 "unknown LED status 0x%x", 3821 sc->sc_gpio_ledstate); 3822 return (USB_ERR_INVAL); 3823 } 3824 return (0); 3825 } 3826 3827 static usb_error_t 3828 urtw_rx_enable(struct urtw_softc *sc) 3829 { 3830 uint8_t data; 3831 usb_error_t error; 3832 3833 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3834 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3835 3836 error = urtw_rx_setconf(sc); 3837 if (error != 0) 3838 goto fail; 3839 3840 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3841 urtw_read8_m(sc, URTW_CMD, &data); 3842 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3843 } 3844 fail: 3845 return (error); 3846 } 3847 3848 static usb_error_t 3849 urtw_tx_enable(struct urtw_softc *sc) 3850 { 3851 uint8_t data8; 3852 uint32_t data; 3853 usb_error_t error; 3854 3855 if (sc->sc_flags & URTW_RTL8187B) { 3856 urtw_read32_m(sc, URTW_TX_CONF, &data); 3857 data &= ~URTW_TX_LOOPBACK_MASK; 3858 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3859 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3860 data &= ~URTW_TX_SWPLCPLEN; 3861 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3862 (7 << 8) | /* short retry limit */ 3863 (7 << 0) | /* long retry limit */ 3864 (7 << 21); /* MAX TX DMA */ 3865 urtw_write32_m(sc, URTW_TX_CONF, data); 3866 3867 urtw_read8_m(sc, URTW_MSR, &data8); 3868 data8 |= URTW_MSR_LINK_ENEDCA; 3869 urtw_write8_m(sc, URTW_MSR, data8); 3870 return (error); 3871 } 3872 3873 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3874 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3875 urtw_write8_m(sc, URTW_CW_CONF, data8); 3876 3877 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3878 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3879 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3880 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3881 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3882 3883 urtw_read32_m(sc, URTW_TX_CONF, &data); 3884 data &= ~URTW_TX_LOOPBACK_MASK; 3885 data |= URTW_TX_LOOPBACK_NONE; 3886 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3887 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3888 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3889 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3890 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3891 data &= ~URTW_TX_SWPLCPLEN; 3892 data |= URTW_TX_NOICV; 3893 urtw_write32_m(sc, URTW_TX_CONF, data); 3894 3895 urtw_read8_m(sc, URTW_CMD, &data8); 3896 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3897 fail: 3898 return (error); 3899 } 3900 3901 static usb_error_t 3902 urtw_rx_setconf(struct urtw_softc *sc) 3903 { 3904 struct ieee80211com *ic = &sc->sc_ic; 3905 uint32_t data; 3906 usb_error_t error; 3907 3908 urtw_read32_m(sc, URTW_RX, &data); 3909 data = data &~ URTW_RX_FILTER_MASK; 3910 if (sc->sc_flags & URTW_RTL8187B) { 3911 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3912 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3913 URTW_RX_FIFO_THRESHOLD_NONE | 3914 URTW_MAX_RX_DMA_2048 | 3915 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3916 } else { 3917 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3918 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3919 3920 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3921 data = data | URTW_RX_FILTER_ICVERR; 3922 data = data | URTW_RX_FILTER_PWR; 3923 } 3924 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3925 data = data | URTW_RX_FILTER_CRCERR; 3926 3927 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3928 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3929 URTW_RX_AUTORESETPHY; 3930 data = data &~ URTW_MAX_RX_DMA_MASK; 3931 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3932 } 3933 3934 /* XXX allmulti should not be checked here... */ 3935 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3936 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3937 data = data | URTW_RX_FILTER_CTL; 3938 data = data | URTW_RX_FILTER_ALLMAC; 3939 } else { 3940 data = data | URTW_RX_FILTER_NICMAC; 3941 data = data | URTW_RX_CHECK_BSSID; 3942 } 3943 3944 urtw_write32_m(sc, URTW_RX, data); 3945 fail: 3946 return (error); 3947 } 3948 3949 static struct mbuf * 3950 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3951 int8_t *nf_p) 3952 { 3953 int actlen, flen, rssi; 3954 struct ieee80211_frame *wh; 3955 struct mbuf *m, *mnew; 3956 struct urtw_softc *sc = data->sc; 3957 struct ieee80211com *ic = &sc->sc_ic; 3958 uint8_t noise = 0, rate; 3959 uint64_t mactime; 3960 3961 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3962 3963 if (sc->sc_flags & URTW_RTL8187B) { 3964 struct urtw_8187b_rxhdr *rx; 3965 3966 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3967 goto fail; 3968 3969 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3970 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3971 flen = le32toh(rx->flag) & 0xfff; 3972 if (flen > actlen - sizeof(*rx)) 3973 goto fail; 3974 3975 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3976 /* XXX correct? */ 3977 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3978 noise = rx->noise; 3979 3980 if (ieee80211_radiotap_active(ic)) 3981 mactime = rx->mactime; 3982 } else { 3983 struct urtw_8187l_rxhdr *rx; 3984 3985 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3986 goto fail; 3987 3988 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3989 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3990 flen = le32toh(rx->flag) & 0xfff; 3991 if (flen > actlen - sizeof(*rx)) 3992 goto fail; 3993 3994 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3995 /* XXX correct? */ 3996 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3997 noise = rx->noise; 3998 3999 if (ieee80211_radiotap_active(ic)) 4000 mactime = rx->mactime; 4001 } 4002 4003 if (flen < IEEE80211_ACK_LEN) 4004 goto fail; 4005 4006 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 4007 if (mnew == NULL) 4008 goto fail; 4009 4010 m = data->m; 4011 data->m = mnew; 4012 data->buf = mtod(mnew, uint8_t *); 4013 4014 /* finalize mbuf */ 4015 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 4016 4017 if (ieee80211_radiotap_active(ic)) { 4018 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 4019 4020 tap->wr_tsf = mactime; 4021 tap->wr_flags = 0; 4022 tap->wr_dbm_antsignal = (int8_t)rssi; 4023 } 4024 4025 wh = mtod(m, struct ieee80211_frame *); 4026 if (IEEE80211_IS_DATA(wh)) 4027 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 4028 4029 *rssi_p = rssi; 4030 *nf_p = noise; /* XXX correct? */ 4031 4032 return (m); 4033 4034 fail: 4035 counter_u64_add(ic->ic_ierrors, 1); 4036 return (NULL); 4037 } 4038 4039 static void 4040 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 4041 { 4042 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4043 struct ieee80211com *ic = &sc->sc_ic; 4044 struct ieee80211_node *ni; 4045 struct epoch_tracker et; 4046 struct mbuf *m = NULL; 4047 struct urtw_data *data; 4048 int8_t nf = -95; 4049 int rssi = 1; 4050 4051 URTW_ASSERT_LOCKED(sc); 4052 4053 switch (USB_GET_STATE(xfer)) { 4054 case USB_ST_TRANSFERRED: 4055 data = STAILQ_FIRST(&sc->sc_rx_active); 4056 if (data == NULL) 4057 goto setup; 4058 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4059 m = urtw_rxeof(xfer, data, &rssi, &nf); 4060 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4061 /* FALLTHROUGH */ 4062 case USB_ST_SETUP: 4063 setup: 4064 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4065 if (data == NULL) { 4066 KASSERT(m == NULL, ("mbuf isn't NULL")); 4067 return; 4068 } 4069 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4070 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4071 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4072 usbd_xfer_max_len(xfer)); 4073 usbd_transfer_submit(xfer); 4074 4075 /* 4076 * To avoid LOR we should unlock our private mutex here to call 4077 * ieee80211_input() because here is at the end of a USB 4078 * callback and safe to unlock. 4079 */ 4080 URTW_UNLOCK(sc); 4081 if (m != NULL) { 4082 if (m->m_pkthdr.len >= 4083 sizeof(struct ieee80211_frame_min)) { 4084 ni = ieee80211_find_rxnode(ic, 4085 mtod(m, struct ieee80211_frame_min *)); 4086 } else 4087 ni = NULL; 4088 4089 NET_EPOCH_ENTER(et); 4090 if (ni != NULL) { 4091 (void) ieee80211_input(ni, m, rssi, nf); 4092 /* node is no longer needed */ 4093 ieee80211_free_node(ni); 4094 } else 4095 (void) ieee80211_input_all(ic, m, rssi, nf); 4096 NET_EPOCH_EXIT(et); 4097 m = NULL; 4098 } 4099 URTW_LOCK(sc); 4100 break; 4101 default: 4102 /* needs it to the inactive queue due to a error. */ 4103 data = STAILQ_FIRST(&sc->sc_rx_active); 4104 if (data != NULL) { 4105 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4106 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4107 } 4108 if (error != USB_ERR_CANCELLED) { 4109 usbd_xfer_set_stall(xfer); 4110 counter_u64_add(ic->ic_ierrors, 1); 4111 goto setup; 4112 } 4113 break; 4114 } 4115 } 4116 4117 #define URTW_STATUS_TYPE_TXCLOSE 1 4118 #define URTW_STATUS_TYPE_BEACON_INTR 0 4119 4120 static void 4121 urtw_txstatus_eof(struct usb_xfer *xfer) 4122 { 4123 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4124 struct ieee80211com *ic = &sc->sc_ic; 4125 int actlen, type, pktretry; 4126 uint64_t val; 4127 4128 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4129 4130 if (actlen != sizeof(uint64_t)) 4131 return; 4132 4133 val = le64toh(sc->sc_txstatus); 4134 type = (val >> 30) & 0x3; 4135 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4136 pktretry = val & 0xff; 4137 if (pktretry == URTW_TX_MAXRETRY) 4138 counter_u64_add(ic->ic_oerrors, 1); 4139 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4140 pktretry, (val >> 16) & 0xff); 4141 } 4142 } 4143 4144 static void 4145 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4146 { 4147 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4148 struct ieee80211com *ic = &sc->sc_ic; 4149 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4150 4151 URTW_ASSERT_LOCKED(sc); 4152 4153 switch (USB_GET_STATE(xfer)) { 4154 case USB_ST_TRANSFERRED: 4155 urtw_txstatus_eof(xfer); 4156 /* FALLTHROUGH */ 4157 case USB_ST_SETUP: 4158 setup: 4159 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4160 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4161 usbd_transfer_submit(xfer); 4162 break; 4163 default: 4164 if (error != USB_ERR_CANCELLED) { 4165 usbd_xfer_set_stall(xfer); 4166 counter_u64_add(ic->ic_ierrors, 1); 4167 goto setup; 4168 } 4169 break; 4170 } 4171 } 4172 4173 static void 4174 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4175 { 4176 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4177 4178 URTW_ASSERT_LOCKED(sc); 4179 4180 if (data->m) { 4181 /* XXX status? */ 4182 ieee80211_tx_complete(data->ni, data->m, 0); 4183 data->m = NULL; 4184 data->ni = NULL; 4185 } 4186 sc->sc_txtimer = 0; 4187 } 4188 4189 static void 4190 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4191 { 4192 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4193 struct urtw_data *data; 4194 4195 URTW_ASSERT_LOCKED(sc); 4196 4197 switch (USB_GET_STATE(xfer)) { 4198 case USB_ST_TRANSFERRED: 4199 data = STAILQ_FIRST(&sc->sc_tx_active); 4200 if (data == NULL) 4201 goto setup; 4202 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4203 urtw_txeof(xfer, data); 4204 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4205 /* FALLTHROUGH */ 4206 case USB_ST_SETUP: 4207 setup: 4208 data = STAILQ_FIRST(&sc->sc_tx_pending); 4209 if (data == NULL) { 4210 DPRINTF(sc, URTW_DEBUG_XMIT, 4211 "%s: empty pending queue\n", __func__); 4212 return; 4213 } 4214 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4215 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4216 4217 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4218 usbd_transfer_submit(xfer); 4219 4220 urtw_start(sc); 4221 break; 4222 default: 4223 data = STAILQ_FIRST(&sc->sc_tx_active); 4224 if (data == NULL) 4225 goto setup; 4226 if (data->ni != NULL) { 4227 if_inc_counter(data->ni->ni_vap->iv_ifp, 4228 IFCOUNTER_OERRORS, 1); 4229 ieee80211_free_node(data->ni); 4230 data->ni = NULL; 4231 } 4232 if (error != USB_ERR_CANCELLED) { 4233 usbd_xfer_set_stall(xfer); 4234 goto setup; 4235 } 4236 break; 4237 } 4238 } 4239 4240 static struct urtw_data * 4241 _urtw_getbuf(struct urtw_softc *sc) 4242 { 4243 struct urtw_data *bf; 4244 4245 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4246 if (bf != NULL) 4247 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4248 else 4249 bf = NULL; 4250 if (bf == NULL) 4251 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4252 "out of xmit buffers"); 4253 return (bf); 4254 } 4255 4256 static struct urtw_data * 4257 urtw_getbuf(struct urtw_softc *sc) 4258 { 4259 struct urtw_data *bf; 4260 4261 URTW_ASSERT_LOCKED(sc); 4262 4263 bf = _urtw_getbuf(sc); 4264 if (bf == NULL) 4265 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4266 return (bf); 4267 } 4268 4269 static int 4270 urtw_isbmode(uint16_t rate) 4271 { 4272 4273 return ((rate <= 22 && rate != 12 && rate != 18) || 4274 rate == 44) ? (1) : (0); 4275 } 4276 4277 static uint16_t 4278 urtw_rate2dbps(uint16_t rate) 4279 { 4280 4281 switch(rate) { 4282 case 12: 4283 case 18: 4284 case 24: 4285 case 36: 4286 case 48: 4287 case 72: 4288 case 96: 4289 case 108: 4290 return (rate * 2); 4291 default: 4292 break; 4293 } 4294 return (24); 4295 } 4296 4297 static int 4298 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4299 uint8_t ismgt, uint8_t isshort) 4300 { 4301 uint16_t ceiling, frametime, n_dbps; 4302 4303 if (urtw_isbmode(rate)) { 4304 if (ismgt || !isshort || rate == 2) 4305 frametime = (uint16_t)(144 + 48 + 4306 (framelen * 8 / (rate / 2))); 4307 else 4308 frametime = (uint16_t)(72 + 24 + 4309 (framelen * 8 / (rate / 2))); 4310 if ((framelen * 8 % (rate / 2)) != 0) 4311 frametime++; 4312 } else { 4313 n_dbps = urtw_rate2dbps(rate); 4314 ceiling = (16 + 8 * framelen + 6) / n_dbps 4315 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4316 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4317 } 4318 return (frametime); 4319 } 4320 4321 /* 4322 * Callback from the 802.11 layer to update the 4323 * slot time based on the current setting. 4324 */ 4325 static void 4326 urtw_updateslot(struct ieee80211com *ic) 4327 { 4328 struct urtw_softc *sc = ic->ic_softc; 4329 4330 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4331 } 4332 4333 static void 4334 urtw_updateslottask(void *arg, int pending) 4335 { 4336 struct urtw_softc *sc = arg; 4337 struct ieee80211com *ic = &sc->sc_ic; 4338 int error; 4339 4340 URTW_LOCK(sc); 4341 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4342 URTW_UNLOCK(sc); 4343 return; 4344 } 4345 if (sc->sc_flags & URTW_RTL8187B) { 4346 urtw_write8_m(sc, URTW_SIFS, 0x22); 4347 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4348 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4349 else 4350 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4351 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4352 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4353 } else { 4354 urtw_write8_m(sc, URTW_SIFS, 0x22); 4355 if (sc->sc_state == IEEE80211_S_ASSOC && 4356 ic->ic_flags & IEEE80211_F_SHSLOT) 4357 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4358 else 4359 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4360 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4361 urtw_write8_m(sc, URTW_DIFS, 0x14); 4362 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4363 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4364 } else { 4365 urtw_write8_m(sc, URTW_DIFS, 0x24); 4366 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4367 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4368 } 4369 } 4370 fail: 4371 URTW_UNLOCK(sc); 4372 } 4373 4374 static void 4375 urtw_sysctl_node(struct urtw_softc *sc) 4376 { 4377 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4378 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4379 struct sysctl_ctx_list *ctx; 4380 struct sysctl_oid_list *child, *parent; 4381 struct sysctl_oid *tree; 4382 struct urtw_stats *stats = &sc->sc_stats; 4383 4384 ctx = device_get_sysctl_ctx(sc->sc_dev); 4385 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4386 4387 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4388 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "URTW statistics"); 4389 parent = SYSCTL_CHILDREN(tree); 4390 4391 /* Tx statistics. */ 4392 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 4393 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 4394 child = SYSCTL_CHILDREN(tree); 4395 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4396 "1 Mbit/s"); 4397 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4398 "2 Mbit/s"); 4399 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4400 "5.5 Mbit/s"); 4401 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4402 "6 Mbit/s"); 4403 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4404 "9 Mbit/s"); 4405 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4406 "11 Mbit/s"); 4407 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4408 "12 Mbit/s"); 4409 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4410 "18 Mbit/s"); 4411 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4412 "24 Mbit/s"); 4413 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4414 "36 Mbit/s"); 4415 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4416 "48 Mbit/s"); 4417 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4418 "54 Mbit/s"); 4419 #undef URTW_SYSCTL_STAT_ADD32 4420 } 4421 4422 static device_method_t urtw_methods[] = { 4423 DEVMETHOD(device_probe, urtw_match), 4424 DEVMETHOD(device_attach, urtw_attach), 4425 DEVMETHOD(device_detach, urtw_detach), 4426 DEVMETHOD_END 4427 }; 4428 4429 static driver_t urtw_driver = { 4430 .name = "urtw", 4431 .methods = urtw_methods, 4432 .size = sizeof(struct urtw_softc) 4433 }; 4434 4435 DRIVER_MODULE(urtw, uhub, urtw_driver, NULL, NULL); 4436 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4437 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4438 MODULE_VERSION(urtw, 1); 4439 USB_PNP_HOST_INFO(urtw_devs);
Cache object: afbe83b6b7ca7e55821f128c75481a50
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