Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/usb/wlan/if_urtwreg.h
Version:
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1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define URTW_CONFIG_INDEX 0 20 #define URTW_IFACE_INDEX 0 21 22 /* for 8187 */ 23 #define URTW_MAC0 0x0000 /* 1 byte */ 24 #define URTW_MAC1 0x0001 /* 1 byte */ 25 #define URTW_MAC2 0x0002 /* 1 byte */ 26 #define URTW_MAC3 0x0003 /* 1 byte */ 27 #define URTW_MAC4 0x0004 /* 1 byte */ 28 #define URTW_MAC5 0x0005 /* 1 byte */ 29 #define URTW_MAR 0x0008 /* 6 byte */ 30 #define URTW_RXFIFO_CNT 0x0010 /* 1 byte */ 31 #define URTW_TXFIFO_CNT 0x0012 /* 1 byte */ 32 #define URTW_BQREQ 0x0013 /* 1 byte */ 33 #define URTW_TSFT 0x0018 /* 6 byte */ 34 #define URTW_TLPDA 0x0020 /* 4 byte */ 35 #define URTW_TNPDA 0x0024 /* 4 byte */ 36 #define URTW_THPDA 0x0028 /* 4 byte */ 37 #define URTW_BRSR 0x002c /* 2 byte */ 38 #define URTW_BRSR_MBR_8185 (0x0fff) 39 #define URTW_8187B_EIFS 0x002d /* 1 byte for 8187B */ 40 #define URTW_BSSID 0x002e /* 6 byte */ 41 #define URTW_BRSR_8187B 0x0034 /* 2 byte for 8187B */ 42 #define URTW_RESP_RATE 0x0034 /* 1 byte for 8187L */ 43 #define URTW_RESP_MAX_RATE_SHIFT (4) 44 #define URTW_RESP_MIN_RATE_SHIFT (0) 45 #define URTW_EIFS 0x0035 /* 1 byte */ 46 #define URTW_CMD 0x0037 /* 1 byte */ 47 #define URTW_CMD_TX_ENABLE (0x4) 48 #define URTW_CMD_RX_ENABLE (0x8) 49 #define URTW_CMD_RST (0x10) 50 #define URTW_INTR_MASK 0x003c /* 2 byte */ 51 #define URTW_INTR_STATUS 0x003e /* 2 byte */ 52 #define URTW_TX_CONF 0x0040 /* 4 byte */ 53 #define URTW_TX_LOOPBACK_SHIFT (17) 54 #define URTW_TX_LOOPBACK_NONE (0 << URTW_TX_LOOPBACK_SHIFT) 55 #define URTW_TX_LOOPBACK_MAC (1 << URTW_TX_LOOPBACK_SHIFT) 56 #define URTW_TX_LOOPBACK_BASEBAND (2 << URTW_TX_LOOPBACK_SHIFT) 57 #define URTW_TX_LOOPBACK_CONTINUE (3 << URTW_TX_LOOPBACK_SHIFT) 58 #define URTW_TX_LOOPBACK_MASK (0x60000) 59 #define URTW_TX_DPRETRY_MASK (0xff00) 60 #define URTW_TX_RTSRETRY_MASK (0xff) 61 #define URTW_TX_DPRETRY_SHIFT (0) 62 #define URTW_TX_RTSRETRY_SHIFT (8) 63 #define URTW_TX_NOCRC (0x10000) 64 #define URTW_TX_MXDMA_MASK (0xe00000) 65 #define URTW_TX_MXDMA_1024 (6 << URTW_TX_MXDMA_SHIFT) 66 #define URTW_TX_MXDMA_2048 (7 << URTW_TX_MXDMA_SHIFT) 67 #define URTW_TX_MXDMA_SHIFT (21) 68 #define URTW_TX_DISCW (1 << 20) 69 #define URTW_TX_SWPLCPLEN (1 << 24) 70 #define URTW_TX_R8187vD (5 << 25) 71 #define URTW_TX_R8187vD_B (6 << 25) 72 #define URTW_TX_HWMASK (7 << 25) 73 #define URTW_TX_DISREQQSIZE (1 << 28) 74 #define URTW_TX_HW_SEQNUM (1 << 30) 75 #define URTW_TX_CWMIN (1U << 31) 76 #define URTW_TX_NOICV (0x80000) 77 #define URTW_RX 0x0044 /* 4 byte */ 78 #define URTW_RX_9356SEL (1 << 6) 79 #define URTW_RX_FILTER_MASK \ 80 (URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \ 81 URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \ 82 URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG | \ 83 (1 << 21) | \ 84 URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID) 85 #define URTW_RX_FILTER_ALLMAC (0x00000001) 86 #define URTW_RX_FILTER_NICMAC (0x00000002) 87 #define URTW_RX_FILTER_MCAST (0x00000004) 88 #define URTW_RX_FILTER_BCAST (0x00000008) 89 #define URTW_RX_FILTER_CRCERR (0x00000020) 90 #define URTW_RX_FILTER_ICVERR (0x00001000) 91 #define URTW_RX_FILTER_DATA (0x00040000) 92 #define URTW_RX_FILTER_CTL (0x00080000) 93 #define URTW_RX_FILTER_MNG (0x00100000) 94 #define URTW_RX_FILTER_PWR (0x00400000) 95 #define URTW_RX_CHECK_BSSID (0x00800000) 96 #define URTW_RX_FIFO_THRESHOLD_MASK ((1 << 13) | (1 << 14) | (1 << 15)) 97 #define URTW_RX_FIFO_THRESHOLD_SHIFT (13) 98 #define URTW_RX_FIFO_THRESHOLD_128 (3) 99 #define URTW_RX_FIFO_THRESHOLD_256 (4) 100 #define URTW_RX_FIFO_THRESHOLD_512 (5) 101 #define URTW_RX_FIFO_THRESHOLD_1024 (6) 102 #define URTW_RX_FIFO_THRESHOLD_NONE (7 << URTW_RX_FIFO_THRESHOLD_SHIFT) 103 #define URTW_RX_AUTORESETPHY (1 << URTW_RX_AUTORESETPHY_SHIFT) 104 #define URTW_RX_AUTORESETPHY_SHIFT (28) 105 #define URTW_MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) 106 #define URTW_MAX_RX_DMA_2048 (7 << URTW_MAX_RX_DMA_SHIFT) 107 #define URTW_MAX_RX_DMA_1024 (6) 108 #define URTW_MAX_RX_DMA_SHIFT (10) 109 #define URTW_RCR_ONLYERLPKT (1U << 31) 110 #define URTW_INT_TIMEOUT 0x0048 /* 4 byte */ 111 #define URTW_INT_TBDA 0x004c /* 4 byte */ 112 #define URTW_EPROM_CMD 0x0050 /* 1 byte */ 113 #define URTW_EPROM_CMD_NORMAL (0x0) 114 #define URTW_EPROM_CMD_NORMAL_MODE \ 115 (URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT) 116 #define URTW_EPROM_CMD_LOAD (0x1) 117 #define URTW_EPROM_CMD_PROGRAM (0x2) 118 #define URTW_EPROM_CMD_PROGRAM_MODE \ 119 (URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT) 120 #define URTW_EPROM_CMD_CONFIG (0x3) 121 #define URTW_EPROM_CMD_SHIFT (6) 122 #define URTW_EPROM_CMD_MASK ((1 << 7) | (1 << 6)) 123 #define URTW_EPROM_READBIT (0x1) 124 #define URTW_EPROM_WRITEBIT (0x2) 125 #define URTW_EPROM_CK (0x4) 126 #define URTW_EPROM_CS (0x8) 127 #define URTW_CONFIG0 0x0051 /* 1 byte */ 128 #define URTW_CONFIG1 0x0052 /* 1 byte */ 129 #define URTW_CONFIG2 0x0053 /* 1 byte */ 130 #define URTW_ANAPARAM 0x0054 /* 4 byte */ 131 #define URTW_8225_ANAPARAM_ON (0xa0000a59) 132 #define URTW_8225_ANAPARAM_OFF (0xa00beb59) 133 #define URTW_8187B_8225_ANAPARAM_ON (0x45090658) 134 #define URTW_8187B_8225_ANAPARAM_OFF (0x55480658) 135 #define URTW_MSR 0x0058 /* 1 byte */ 136 #define URTW_MSR_LINK_MASK ((1 << 2) | (1 << 3)) 137 #define URTW_MSR_LINK_SHIFT (2) 138 #define URTW_MSR_LINK_NONE (0 << URTW_MSR_LINK_SHIFT) 139 #define URTW_MSR_LINK_ADHOC (1 << URTW_MSR_LINK_SHIFT) 140 #define URTW_MSR_LINK_STA (2 << URTW_MSR_LINK_SHIFT) 141 #define URTW_MSR_LINK_HOSTAP (3 << URTW_MSR_LINK_SHIFT) 142 #define URTW_MSR_LINK_ENEDCA (1 << 4) 143 #define URTW_CONFIG3 0x0059 /* 1 byte */ 144 #define URTW_CONFIG3_ANAPARAM_WRITE (0x40) 145 #define URTW_CONFIG3_GNT_SELECT (0x80) 146 #define URTW_CONFIG3_ANAPARAM_W_SHIFT (6) 147 #define URTW_CONFIG4 0x005a /* 1 byte */ 148 #define URTW_CONFIG4_VCOOFF (1 << 7) 149 #define URTW_TESTR 0x005b /* 1 byte */ 150 #define URTW_PSR 0x005e /* 1 byte */ 151 #define URTW_SECURITY 0x005f /* 1 byte */ 152 #define URTW_ANAPARAM2 0x0060 /* 4 byte */ 153 #define URTW_8225_ANAPARAM2_ON (0x860c7312) 154 #define URTW_8225_ANAPARAM2_OFF (0x840dec11) 155 #define URTW_8187B_8225_ANAPARAM2_ON (0x727f3f52) 156 #define URTW_8187B_8225_ANAPARAM2_OFF (0x72003f50) 157 #define URTW_BEACON_INTERVAL 0x0070 /* 2 byte */ 158 #define URTW_ATIM_WND 0x0072 /* 2 byte */ 159 #define URTW_BEACON_INTERVAL_TIME 0x0074 /* 2 byte */ 160 #define URTW_ATIM_TR_ITV 0x0076 /* 2 byte */ 161 #define URTW_PHY_DELAY 0x0078 /* 1 byte */ 162 #define URTW_CARRIER_SCOUNT 0x0079 /* 1 byte */ 163 #define URTW_PHY_MAGIC1 0x007c /* 1 byte */ 164 #define URTW_PHY_MAGIC2 0x007d /* 1 byte */ 165 #define URTW_PHY_MAGIC3 0x007e /* 1 byte */ 166 #define URTW_PHY_MAGIC4 0x007f /* 1 byte */ 167 #define URTW_RF_PINS_OUTPUT 0x0080 /* 2 byte */ 168 #define URTW_RF_PINS_OUTPUT_MAGIC1 (0x3a0) 169 #define URTW_BB_HOST_BANG_CLK (1 << 1) 170 #define URTW_BB_HOST_BANG_EN (1 << 2) 171 #define URTW_BB_HOST_BANG_RW (1 << 3) 172 #define URTW_RF_PINS_ENABLE 0x0082 /* 2 byte */ 173 #define URTW_RF_PINS_SELECT 0x0084 /* 2 byte */ 174 #define URTW_ADDR_MAGIC1 0x0085 /* broken? */ 175 #define URTW_RF_PINS_INPUT 0x0086 /* 2 byte */ 176 #define URTW_RF_PINS_MAGIC1 (0xfff3) 177 #define URTW_RF_PINS_MAGIC2 (0xfff0) 178 #define URTW_RF_PINS_MAGIC3 (0x0007) 179 #define URTW_RF_PINS_MAGIC4 (0xf) 180 #define URTW_RF_PINS_MAGIC5 (0x0080) 181 #define URTW_RF_PARA 0x0088 /* 4 byte */ 182 #define URTW_RF_TIMING 0x008c /* 4 byte */ 183 #define URTW_GP_ENABLE 0x0090 /* 1 byte */ 184 #define URTW_GP_ENABLE_DATA_MAGIC1 (0x1) 185 #define URTW_GPIO 0x0091 /* 1 byte */ 186 #define URTW_GPIO_DATA_MAGIC1 (0x1) 187 #define URTW_HSSI_PARA 0x0094 /* 4 byte */ 188 #define URTW_TX_AGC_CTL 0x009c /* 1 byte */ 189 #define URTW_TX_AGC_CTL_PERPACKET_GAIN (0x1) 190 #define URTW_TX_AGC_CTL_PERPACKET_ANTSEL (0x2) 191 #define URTW_TX_AGC_CTL_FEEDBACK_ANT (0x4) 192 #define URTW_TX_GAIN_CCK 0x009d /* 1 byte */ 193 #define URTW_TX_GAIN_OFDM 0x009e /* 1 byte */ 194 #define URTW_TX_ANTENNA 0x009f /* 1 byte */ 195 #define URTW_WPA_CONFIG 0x00b0 /* 1 byte */ 196 #define URTW_SIFS 0x00b4 /* 1 byte */ 197 #define URTW_DIFS 0x00b5 /* 1 byte */ 198 #define URTW_SLOT 0x00b6 /* 1 byte */ 199 #define URTW_CW_CONF 0x00bc /* 1 byte */ 200 #define URTW_CW_CONF_PERPACKET_RETRY (0x2) 201 #define URTW_CW_CONF_PERPACKET_CW (0x1) 202 #define URTW_CW_VAL 0x00bd /* 1 byte */ 203 #define URTW_RATE_FALLBACK 0x00be /* 1 byte */ 204 #define URTW_RATE_FALLBACK_ENABLE (0x80) 205 #define URTW_ACM_CONTROL 0x00bf /* 1 byte */ 206 #define URTW_CONFIG5 0x00d8 /* 1 byte */ 207 #define URTW_TXDMA_POLLING 0x00d9 /* 1 byte */ 208 #define URTW_CWR 0x00dc /* 2 byte */ 209 #define URTW_RETRY_CTR 0x00de /* 1 byte */ 210 #define URTW_INT_MIG 0x00e2 /* 2 byte */ 211 #define URTW_RDSAR 0x00e4 /* 4 byte */ 212 #define URTW_TID_AC_MAP 0x00e8 /* 2 byte */ 213 #define URTW_ANAPARAM3 0x00ee /* 1 byte */ 214 #define URTW_8187B_8225_ANAPARAM3_ON (0x0) 215 #define URTW_8187B_8225_ANAPARAM3_OFF (0x0) 216 #define URTW_8187B_AC_VO 0x00f0 /* 4 byte for 8187B */ 217 #define URTW_FEMR 0x00f4 /* 2 byte */ 218 #define URTW_8187B_AC_VI 0x00f4 /* 4 byte for 8187B */ 219 #define URTW_8187B_AC_BE 0x00f8 /* 4 byte for 8187B */ 220 #define URTW_TALLY_CNT 0x00fa /* 2 byte */ 221 #define URTW_TALLY_SEL 0x00fc /* 1 byte */ 222 #define URTW_8187B_AC_BK 0x00fc /* 4 byte for 8187B */ 223 #define URTW_ADDR_MAGIC2 0x00fe /* 2 byte */ 224 #define URTW_ADDR_MAGIC3 0x00ff /* 1 byte */ 225 226 /* for 8225 */ 227 #define URTW_8225_ADDR_0_MAGIC 0x0 228 #define URTW_8225_ADDR_0_DATA_MAGIC1 (0x1b7) 229 #define URTW_8225_ADDR_0_DATA_MAGIC2 (0x0b7) 230 #define URTW_8225_ADDR_0_DATA_MAGIC3 (0x127) 231 #define URTW_8225_ADDR_0_DATA_MAGIC4 (0x027) 232 #define URTW_8225_ADDR_0_DATA_MAGIC5 (0x22f) 233 #define URTW_8225_ADDR_0_DATA_MAGIC6 (0x2bf) 234 #define URTW_8225_ADDR_1_MAGIC 0x1 235 #define URTW_8225_ADDR_2_MAGIC 0x2 236 #define URTW_8225_ADDR_2_DATA_MAGIC1 (0xc4d) 237 #define URTW_8225_ADDR_2_DATA_MAGIC2 (0x44d) 238 #define URTW_8225_ADDR_3_MAGIC 0x3 239 #define URTW_8225_ADDR_3_DATA_MAGIC1 (0x2) 240 #define URTW_8225_ADDR_5_MAGIC 0x5 241 #define URTW_8225_ADDR_5_DATA_MAGIC1 (0x4) 242 #define URTW_8225_ADDR_6_MAGIC 0x6 243 #define URTW_8225_ADDR_6_DATA_MAGIC1 (0xe6) 244 #define URTW_8225_ADDR_6_DATA_MAGIC2 (0x80) 245 #define URTW_8225_ADDR_7_MAGIC 0x7 246 #define URTW_8225_ADDR_8_MAGIC 0x8 247 #define URTW_8225_ADDR_8_DATA_MAGIC1 (0x588) 248 #define URTW_8225_ADDR_9_MAGIC 0x9 249 #define URTW_8225_ADDR_9_DATA_MAGIC1 (0x700) 250 #define URTW_8225_ADDR_C_MAGIC 0xc 251 #define URTW_8225_ADDR_C_DATA_MAGIC1 (0x850) 252 #define URTW_8225_ADDR_C_DATA_MAGIC2 (0x050) 253 254 /* for EEPROM */ 255 #define URTW_EPROM_CHANPLAN 0x03 256 #define URTW_EPROM_CHANPLAN_BY_HW (0x80) 257 #define URTW_EPROM_TXPW_BASE 0x05 258 #define URTW_EPROM_RFCHIPID 0x06 259 #define URTW_EPROM_RFCHIPID_RTL8225U (5) 260 #define URTW_EPROM_RFCHIPID_RTL8225Z2 (6) 261 #define URTW_EPROM_MACADDR 0x07 262 #define URTW_EPROM_TXPW0 0x16 263 #define URTW_EPROM_TXPW2 0x1b 264 #define URTW_EPROM_TXPW1 0x3d 265 #define URTW_EPROM_SWREV 0x3f 266 #define URTW_EPROM_CID_MASK (0xff) 267 #define URTW_EPROM_CID_RSVD0 (0x00) 268 #define URTW_EPROM_CID_RSVD1 (0xff) 269 #define URTW_EPROM_CID_ALPHA0 (0x01) 270 #define URTW_EPROM_CID_SERCOMM_PS (0x02) 271 #define URTW_EPROM_CID_HW_LED (0x03) 272 273 /* LED */ 274 #define URTW_CID_DEFAULT 0 275 #define URTW_CID_8187_ALPHA0 1 276 #define URTW_CID_8187_SERCOMM_PS 2 277 #define URTW_CID_8187_HW_LED 3 278 #define URTW_SW_LED_MODE0 0 279 #define URTW_SW_LED_MODE1 1 280 #define URTW_SW_LED_MODE2 2 281 #define URTW_SW_LED_MODE3 3 282 #define URTW_HW_LED 4 283 #define URTW_LED_CTL_POWER_ON 0 284 #define URTW_LED_CTL_LINK 2 285 #define URTW_LED_CTL_TX 4 286 #define URTW_LED_PIN_GPIO0 0 287 #define URTW_LED_PIN_LED0 1 288 #define URTW_LED_PIN_LED1 2 289 #define URTW_LED_UNKNOWN 0 290 #define URTW_LED_ON 1 291 #define URTW_LED_OFF 2 292 #define URTW_LED_BLINK_NORMAL 3 293 #define URTW_LED_BLINK_SLOWLY 4 294 #define URTW_LED_POWER_ON_BLINK 5 295 #define URTW_LED_SCAN_BLINK 6 296 #define URTW_LED_NO_LINK_BLINK 7 297 #define URTW_LED_BLINK_CM3 8 298 299 /* for extra area */ 300 #define URTW_EPROM_DISABLE 0 301 #define URTW_EPROM_ENABLE 1 302 #define URTW_EPROM_DELAY 10 303 #define URTW_8187_GETREGS_REQ 5 304 #define URTW_8187_SETREGS_REQ 5 305 #define URTW_8225_RF_MAX_SENS 6 306 #define URTW_8225_RF_DEF_SENS 4 307 #define URTW_DEFAULT_RTS_RETRY 7 308 #define URTW_DEFAULT_TX_RETRY 7 309 #define URTW_DEFAULT_RTS_THRESHOLD 2342U 310 311 #define URTW_ASIFS_TIME 10 312 #define URTW_ACKCTS_LEN 14 /* len for ACK and CTS */ 313 314 struct urtw_8187b_rxhdr { 315 uint32_t flag; 316 #define URTW_RX_FLAG_LEN /* 0 ~ 11 bits */ 317 #define URTW_RX_FLAG_ICV_ERR (1 << 12) 318 #define URTW_RX_FLAG_CRC32_ERR (1 << 13) 319 #define URTW_RX_FLAG_PM (1 << 14) 320 #define URTW_RX_FLAG_RX_ERR (1 << 15) 321 #define URTW_RX_FLAG_BCAST (1 << 16) 322 #define URTW_RX_FLAG_PAM (1 << 17) 323 #define URTW_RX_FLAG_MCAST (1 << 18) 324 #define URTW_RX_FLAG_QOS (1 << 19) /* only for RTL8187B */ 325 #define URTW_RX_FLAG_RXRATE /* 20 ~ 23 bits */ 326 #define URTW_RX_FLAG_RXRATE_SHIFT 20 327 #define URTW_RX_FLAG_TRSW (1 << 24) /* only for RTL8187B */ 328 #define URTW_RX_FLAG_SPLCP (1 << 25) 329 #define URTW_RX_FLAG_FOF (1 << 26) 330 #define URTW_RX_FLAG_DMA_FAIL (1 << 27) 331 #define URTW_RX_FLAG_LAST (1 << 28) 332 #define URTW_RX_FLAG_FIRST (1 << 29) 333 #define URTW_RX_FLAG_EOR (1 << 30) 334 #define URTW_RX_FLAG_OWN (1U << 31) 335 uint64_t mactime; 336 uint8_t noise; 337 uint8_t rssi; 338 #define URTW_RX_RSSI /* 0 ~ 6 bits */ 339 #define URTW_RX_RSSI_MASK 0x3f 340 #define URTW_RX_ANTENNA (1 << 7) 341 uint8_t agc; 342 uint8_t flag2; 343 #define URTW_RX_FLAG2_DECRYPTED (1 << 0) 344 #define URTW_RX_FLAG2_WAKUP (1 << 1) 345 #define URTW_RX_FLAG2_SHIFT (1 << 2) 346 #define URTW_RX_FLAG2_RSVD0 /* 3 ~ 7 bits */ 347 uint16_t flag3; 348 #define URTW_RX_FLAG3_NUMMCSI /* 0 ~ 3 bits */ 349 #define URTW_RX_FLAG3_SNR_L2E /* 4 ~ 9 bits */ 350 #define URTW_RX_FLAG3_CFO_BIAS /* 10 ~ 15 bits */ 351 int8_t pwdb; 352 uint8_t fot; 353 } __packed; 354 355 struct urtw_8187b_txhdr { 356 uint32_t flag; 357 #define URTW_TX_FLAG_PKTLEN /* 0 ~ 11 bits */ 358 #define URTW_TX_FLAG_RSVD0 /* 12 ~ 14 bits */ 359 #define URTW_TX_FLAG_NO_ENC (1 << 15) 360 #define URTW_TX_FLAG_SPLCP (1 << 16) 361 #define URTW_TX_FLAG_MOREFRAG (1 << 17) 362 #define URTW_TX_FLAG_CTS (1 << 18) 363 #define URTW_TX_FLAG_RTSRATE /* 19 ~ 22 bits */ 364 #define URTW_TX_FLAG_RTSRATE_SHIFT 19 365 #define URTW_TX_FLAG_RTS (1 << 23) 366 #define URTW_TX_FLAG_TXRATE /* 24 ~ 27 bits */ 367 #define URTW_TX_FLAG_TXRATE_SHIFT 24 368 #define URTW_TX_FLAG_LAST (1 << 28) 369 #define URTW_TX_FLAG_FIRST (1 << 29) 370 #define URTW_TX_FLAG_DMA (1 << 30) 371 #define URTW_TX_FLAG_OWN (1U << 31) 372 uint16_t rtsdur; 373 uint16_t len; 374 #define URTW_TX_LEN /* 0 ~ 14 bits */ 375 #define URTW_TX_LEN_EXT (1 << 15) 376 uint32_t bufaddr; 377 uint16_t flag1; 378 #define URTW_TX_FLAG1_RXLEN /* 0 ~ 11 bits */ 379 #define URTW_TX_FLAG1_RSVD0 /* 12 ~ 14 bits */ 380 #define URTW_TX_FLAG1_MICCAL (1 << 15) 381 uint16_t txdur; 382 uint32_t nextdescaddr; 383 uint8_t rtsagc; 384 uint8_t retry; 385 uint16_t flag2; 386 #define URTW_TX_FLAG2_RTDB (1 << 0) 387 #define URTW_TX_FLAG2_NOACM (1 << 1) 388 #define URTW_TX_FLAG2_PIFS (1 << 2) 389 #define URTW_TX_FLAG2_RSVD0 /* 3 ~ 6 bits */ 390 #define URTW_TX_FLAG2_RTSRATEFALLBACK /* 7 ~ 10 bits */ 391 #define URTW_TX_FLAG2_RATEFALLBACK /* 11 ~ 15 bits */ 392 uint16_t delaybound; 393 uint16_t flag3; 394 #define URTW_TX_FLAG3_RSVD0 /* 0 ~ 3 bits */ 395 #define URTW_TX_FLAG3_AGC /* 4 ~ 11 bits */ 396 #define URTW_TX_FLAG3_ANTENNA (1 << 12) 397 #define URTW_TX_FLAG3_SPC /* 13 ~ 14 bits */ 398 #define URTW_TX_FLAG3_RSVD1 (1 << 15) 399 uint32_t flag4; 400 #define URTW_TX_FLAG4_LENADJUST /* 0 ~ 1 bits */ 401 #define URTW_TX_FLAG4_RSVD0 (1 << 2) 402 #define URTW_TX_FLAG4_TPCDESEN (1 << 3) 403 #define URTW_TX_FLAG4_TPCPOLARITY /* 4 ~ 5 bits */ 404 #define URTW_TX_FLAG4_TPCEN (1 << 6) 405 #define URTW_TX_FLAG4_PTEN (1 << 7) 406 #define URTW_TX_FLAG4_BCKEY /* 8 ~ 13 bits */ 407 #define URTW_TX_FLAG4_ENBCKEY (1 << 14) 408 #define URTW_TX_FLAG4_ENPMPD (1 << 15) 409 #define URTW_TX_FLAG4_FRAGQSZ /* 16 ~ 31 bits */ 410 } __packed; 411 412 struct urtw_8187l_rxhdr { 413 uint32_t flag; 414 uint8_t noise; 415 uint8_t rssi; 416 #define URTW_RX_8187L_RSSI /* 0 ~ 6 bits */ 417 #define URTW_RX_8187L_RSSI_MASK 0x3f 418 #define URTW_RX_8187L_ANTENNA (1 << 7) 419 uint8_t agc; 420 uint8_t flag2; 421 #define URTW_RX_8187L_DECRYPTED (1 << 0) 422 #define URTW_RX_8187L_WAKEUP (1 << 1) 423 #define URTW_RX_8187L_SHIFT (1 << 2) 424 #define URTW_RX_8187L_RSVD0 /* 3 ~ 7 bits */ 425 uint64_t mactime; 426 } __packed; 427 428 struct urtw_8187l_txhdr { 429 uint32_t flag; 430 uint16_t rtsdur; 431 uint16_t len; 432 uint32_t retry; 433 } __packed;
Cache object: 6be36f297f237a8222d70ec6c046ddc2
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