Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/utopia/suni.h
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1 /*- 2 * Copyright (c) 2003 3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Author: Hartmut Brandt <harti@freebsd.org> 28 * 29 * $FreeBSD: releng/6.4/sys/dev/utopia/suni.h 139749 2005-01-06 01:43:34Z imp $ 30 * 31 * Register definitions for the following chips: 32 * PMC-Sierra PMC-5346 (S/UNI-LITE) 33 * PMC-Sierra PMC-5350 (S/UNI-ULTRA) 34 * PMC-Sierra PMC-5355 (S/UNI-622) 35 * 36 * All definitions ending with _ULTRA are for the ULTRA chip only, all 37 * definitions ending with _LITE are for the LITE chip only. Some registers 38 * are only in the ULTRA and the definitions are not suffixed. All other 39 * definitions are for all chips. 40 */ 41 #ifndef _DEV_UTOPIA_SUNI_H 42 #define _DEV_UTOPIA_SUNI_H 43 44 /* lite, ultra, 622 */ 45 #define SUNI_REGN_MRESET "Master Reset and Identity/Load Meters" 46 #define SUNI_REGO_MRESET 0x00 47 #define SUNI_REGM_MRESET_RESET 0x80 48 #define SUNI_REGM_MRESET_TYPE 0x70 49 #define SUNI_REGM_MRESET_TYPE_622 0x10 50 #define SUNI_REGM_MRESET_TYPE_LITE 0x30 51 #define SUNI_REGM_MRESET_TYPE_ULTRA 0x70 52 #define SUNI_REGM_MRESET_TIP_ULTRA 0x08 53 #define SUNI_REGM_MRESET_ID_ULTRA 0x07 54 #define SUNI_REGM_MRESET_ID_LITE 0x0f 55 #define SUNI_REGM_MRESET_ID_622 0x0f 56 #define SUNI_REGX_MRESET_ULTRA "\020\10RESET\12\x70\12TYPE\4TIP\12\7\12ID" 57 #define SUNI_REGX_MRESET_LITE "\020\10RESET\12\x70\12TYPE\12\xf\12ID" 58 #define SUNI_REGX_MRESET_622 "\020\10RESET\12\x70\12TYPE\12\xf\12ID" 59 60 /* lite, ultra */ 61 #define SUNI_REGN_MCONFIG "Master Configuration" 62 #define SUNI_REGO_MCONFIG 0x01 63 #define SUNI_REGM_MCONFIG_AUTOFEBE 0x40 64 #define SUNI_REGM_MCONFIG_AUTOLRDI 0x20 65 #define SUNI_REGM_MCONFIG_AUTOPRDI 0x10 66 #define SUNI_REGM_MCONFIG_TCAINV 0x08 67 #define SUNI_REGM_MCONFIG_RCAINV 0x04 68 #define SUNI_REGM_MCONFIG_RXDINV_LITE 0x02 69 #define SUNI_REGM_MCONFIG_TFP_IN_ULTRA 0x01 70 #define SUNI_REGM_MCONFIG_RESERVED 0x00 71 #define SUNI_REGX_MCONFIG_LITE "\020\7AUTOFEBE\6AUTOLRDI\5AUTOPRDI\4TCAINV\3RCAINV\2RXDINV" 72 #define SUNI_REGX_MCONFIG_ULTRA "\020\7AUTOFEBE\6AUTOLRDI\5AUTOPRDI\4TCAINV\3RCAINV\1TFPI_IN" 73 74 /* 622 */ 75 #define SUNI_REGM_MCONFIG_TPTBEN_622 0x80 76 #define SUNI_REGM_MCONFIG_TSTBEN_622 0x40 77 #define SUNI_REGM_MCONFIG_SDH_C1_622 0x20 78 #define SUNI_REGM_MCONFIG_FIXPTR_622 0x10 79 #define SUNI_REGM_MCONFIG_TMODE_622 0x0C 80 #define SUNI_REGM_MCONFIG_TMODE_STS1_BYTE 0x00 81 #define SUNI_REGM_MCONFIG_TMODE_STS3c 0x04 82 #define SUNI_REGM_MCONFIG_TMODE_STS1_BIT 0x08 83 #define SUNI_REGM_MCONFIG_TMODE_STS12c 0x0C 84 #define SUNI_REGM_MCONFIG_RMODE_622 0x03 85 #define SUNI_REGM_MCONFIG_RMODE_STS1_BYTE 0x00 86 #define SUNI_REGM_MCONFIG_RMODE_STS3c 0x01 87 #define SUNI_REGM_MCONFIG_RMODE_STS1_BIT 0x02 88 #define SUNI_REGM_MCONFIG_RMODE_STS12c 0x03 89 #define SUNI_REGX_MCONFIG_622 "\020\10TPTBEN\7TSTBEN\6SDH_C1\5FIXPTR\11\x0C\0x00XSTS1BYTE\11\0x0C\0x04XSTS3c\11\0x0C\0x08XSTS1BIT\11\0x0C\0x0CXSTS12c\11\0x03\0x00RSTS1BYTE\11\0x03\0x01RSTS3c\11\0x03\0x02RSTS1BIT\11\0x03\0x03RSTS12c" 90 91 /* lite, ultra, 622 */ 92 #define SUNI_REGN_MISTATUS "Master Interrupt Status" 93 #define SUNI_REGO_MISTATUS 0x02 94 #define SUNI_REGM_MISTATUS_CSUI_ULTRA 0x80 95 #define SUNI_REGM_MISTATUS_TROOLI_LITE 0x80 96 #define SUNI_REGM_MISTATUS_SUNII_622 0x80 97 #define SUNI_REGM_MISTATUS_LCDI 0x40 98 #define SUNI_REGM_MISTATUS_STBI_622 0x40 99 #define SUNI_REGM_MISTATUS_CRUI_ULTRA 0x20 100 #define SUNI_REGM_MISTATUS_RDOOLI_LITE 0x20 101 #define SUNI_REGM_MISTATUS_RESERVED_622 0x20 102 #define SUNI_REGM_MISTATUS_TACPI 0x10 103 #define SUNI_REGM_MISTATUS_RACPI 0x08 104 #define SUNI_REGM_MISTATUS_RPOPI 0x04 105 #define SUNI_REGM_MISTATUS_RLOPI 0x02 106 #define SUNI_REGM_MISTATUS_RSOPI 0x01 107 #define SUNI_REGX_MISTATUS_LITE "\020\10TROOLI\7LCDI\6RDOOLI\5TACPI\4RACPI\3RPOPI\2RLOPI\1RSOPI" 108 #define SUNI_REGX_MISTATUS_ULTRA "\020\10CSUI\7LCDI\6CRUI\5TACPI\4RACPI\3RPOPI\2RLOPI\1RSOPI" 109 #define SUNI_REGX_MISTATUS_622 "\020\10S/UNII\7STBI\5TACPI\4RACPI\3RPOPI\2RLOPI\1RSOPI" 110 111 /* ultra */ 112 #define SUNI_REGN_MMCTRL "Master Mode Control" 113 #define SUNI_REGO_MMCTRL 0x03 114 #define SUNI_REGM_MMCTRL_51 0x02 115 #define SUNI_REGM_MMCTRL_155 0x03 116 #define SUNI_REGX_MMCTRL "\020\11\3\00251MBIT\11\3\003155MBIT" 117 118 /* 622 */ 119 #define SUNI_REGN_PISO "PISO Interrupt" 120 #define SUNI_REGO_PISO 0x03 121 #define SUNI_REGM_PISO_PAEE 0x02 122 #define SUNI_REGM_PISO_PAEI 0x01 123 #define SUNI_REGX_PISO "\020\2PAEE\1PAEI" 124 125 /* ultra/lite */ 126 #define SUNI_REGN_MCLKM "Master Clock Monitor" 127 #define SUNI_REGO_MCLKM 0x04 128 #define SUNI_REGM_MCLKM_RFCLKA 0x10 /* ultra */ 129 #define SUNI_REGM_MCLKM_TFCLKA 0x08 /* ultra */ 130 #define SUNI_REGM_MCLKM_RRCLKA 0x08 /* lite */ 131 #define SUNI_REGM_MCLKM_REFCLKA 0x04 /* ultra */ 132 #define SUNI_REGM_MCLKM_TRCLKA 0x04 /* lite */ 133 #define SUNI_REGM_MCLKM_RCLKA 0x02 134 #define SUNI_REGM_MCLKM_TCLKA 0x01 135 #define SUNI_REGX_MCLKM_LITE "\020\4RRCLKA\3TRCLKA\2RCLKA\1TCLKA" 136 #define SUNI_REGX_MCLKM_ULTRA "\020\5RFCLKA\4TFCLKA\3REFCLKA\2RCLKA\1TCLKA" 137 138 /* 622 */ 139 #define SUNI_REGN_MCTRLM "Master Control/Monitor" 140 #define SUNI_REGO_MCTRLM 0x04 141 #define SUNI_REGM_MCTRLM_TCAINV 0x80 142 #define SUNI_REGM_MCTRLM_RCAINV 0x40 143 #define SUNI_REGM_MCTRLM_LLE 0x20 144 #define SUNI_REGM_MCTRLM_DLE 0x10 145 #define SUNI_REGM_MCTRLM_LOOPT 0x08 146 #define SUNI_REGM_MCTRLM_DPLE 0x04 147 #define SUNI_REGM_MCTRLM_PICLKA 0x02 148 #define SUNI_REGM_MCTRLM_TCLKA 0x01 149 #define SUNI_REGX_MCTRLM "\020\10TCAINV\7RCAINV\6LLE\5DLE\4LOOPT\3DPLE\2PICLKA\1TCLKA" 150 151 /* ultra/lite */ 152 #define SUNI_REGN_MCTRL "Master Control" 153 #define SUNI_REGO_MCTRL 0x05 154 #define SUNI_REGM_MCTRL_LCDE 0x80 155 #define SUNI_REGM_MCTRL_LCDV 0x40 156 #define SUNI_REGM_MCTRL_FIXPTR 0x20 157 #define SUNI_REGM_MCTRL_TPLE 0x10 /* ultra */ 158 #define SUNI_REGM_MCTRL_PDLE 0x08 /* ultra */ 159 #define SUNI_REGM_MCTRL_LLE 0x04 160 #define SUNI_REGM_MCTRL_SDLE 0x02 /* ultra */ 161 #define SUNI_REGM_MCTRL_DLE 0x02 /* lite */ 162 #define SUNI_REGM_MCTRL_LOOPT 0x01 163 #define SUNI_REGX_MCTRL_ULTRA "\020\10LCDE\7LCDV\6FIXPTR\5TPLE\4PDLE\3LLE\2SDLE\1LOOPT" 164 #define SUNI_REGX_MCTRL_LITE "\020\10LCDE\7LCDV\6FIXPTR\3LLE\2DLE\1LOOPT" 165 166 /* 622 */ 167 #define SUNI_REGN_MALARM "Master Auto Alarm" 168 #define SUNI_REGO_MALARM 0x05 169 #define SUNI_REGM_MALARM_AUTOFEBE 0x04 170 #define SUNI_REGM_MALARM_AUTOLRDI 0x02 171 #define SUNI_REGM_MALARM_AUTOPRDI 0x01 172 #define SUNI_REGX_MALARM "\020\4AUTOFEBE\2AUTOLRDI\1AUTOPRDI" 173 174 /* ultra/lite */ 175 #define SUNI_REGN_CLKSYN "Clock Synthesis Control and Status" 176 #define SUNI_REGO_CLKSYN 0x06 177 #define SUNI_REGM_CLKSYN_TROOLI 0x20 /* ultra */ 178 #define SUNI_REGM_CLKSYN_TROOLV 0x08 179 #define SUNI_REGM_CLKSYN_TROOLE 0x02 180 #define SUNI_REGM_CLKSYN_TREFSEL 0x01 /* lite */ 181 #define SUNI_REGM_CLKSYN_RESERVED 0x00 182 #define SUNI_REGX_CLKSYN_ULTRA "\020\6TROOLI\4TROOLV\2TROOLE" 183 #define SUNI_REGX_CLKSYN_LITE "\020\4TROOLV\2TROOLE\1TREFSEL" 184 185 /* 622 */ 186 #define SUNI_REGN_POUT "Parallel Output Port" 187 #define SUNI_REGO_POUT 0x06 188 #define SUNI_REGM_POUT_POP 0x3f 189 #define SUNI_REGX_POUT "\020\12\x3f\12POP" 190 191 /* ultra/lite */ 192 #define SUNI_REGN_CLKREC "Clock Recovery Control and Status" 193 #define SUNI_REGO_CLKREC_LITE 0x07 194 #define SUNI_REGO_CLKREC_ULTRA 0x08 195 #define SUNI_REGM_CLKREC_RROOLI 0x40 /* ultra */ 196 #define SUNI_REGM_CLKREC_RDOOLI 0x20 /* ultra */ 197 #define SUNI_REGM_CLKREC_RROOLV 0x10 198 #define SUNI_REGM_CLKREC_RDOOLV 0x08 199 #define SUNI_REGM_CLKREC_RROOLE 0x04 /* ultra */ 200 #define SUNI_REGM_CLKREC_RDOOLE 0x02 201 #define SUNI_REGM_CLKREC_RREFSEL 0x01 /* lite */ 202 #define SUNI_REGM_CLKREC_RESERVED 0x00 203 #define SUNI_REGX_CLKREC_ULTRA "\020\7RROOLI\6RDOOLI\5RROOLV\4RDOOLV\3RROOLE\2RDOOLE" 204 #define SUNI_REGX_CLKREC_LITE "\020\5RROOLV\4RDOOLV\2RDOOLE\1RREFSEL" 205 206 /* 622 */ 207 #define SUNI_REGN_PIN "Parallel Input Port" 208 #define SUNI_REGO_PIN 0x07 209 210 /* 622 */ 211 #define SUNI_REGN_PINV "Parallel Input Port Value" 212 #define SUNI_REGO_PINV 0x08 213 #define SUNI_REGM_PINV_PIPV 0x0f 214 #define SUNI_REGX_PINV "\020\12\0x0f\12PIPIV" 215 216 /* ultra */ 217 #define SUNI_REGN_CLKRECCFG "Clock Recovery Configuration" 218 #define SUNI_REGO_CLKRECCFG 0x09 219 #define SUNI_REGM_CLKRECCFG_RESERVED 0x07 220 #define SUNI_REGX_CLKRECCFG "\020" 221 222 /* 622 */ 223 #define SUNI_REGN_PINE "Parallel Input Port Enable" 224 #define SUNI_REGO_PINE 0x09 225 226 /* ultra */ 227 #define SUNI_REGN_LTXCFG1 "Line Transmitter Configuration 1" 228 #define SUNI_REGO_LTXCFG1 0x0A 229 #define SUNI_REGM_LTXCFG1_VREFSEL 0x80 230 #define SUNI_REGM_LTXCFG1_OEN 0x20 231 #define SUNI_REGM_LTXCFG1_OTQ 0x10 232 #define SUNI_REGM_LTXCFG1_RESERVED 0x0C 233 #define SUNI_REGX_LTXCFG1 "\020\10VREFSEL\6OEN\5OTQ" 234 235 /* 622 */ 236 #define SUNI_REGN_XC1 "Transmit C1" 237 #define SUNI_REGO_XC1 0x0A 238 239 /* ultra */ 240 #define SUNI_REGN_LTXCFG2 "Line Transmitter Configuration 2" 241 #define SUNI_REGO_LTXCFG2 0x0B 242 #define SUNI_REGM_LTXCFG2_RESERVED 0xFF 243 #define SUNI_REGX_LTXCFG2 "\020" 244 245 /* 622 */ 246 #define SUNI_REGN_APSCS "APS Control/Status" 247 #define SUNI_REGO_APSCS 0x0B 248 #define SUNI_REGM_APSCS_PSBFE 0x80 249 #define SUNI_REGM_APSCS_COAPSE 0x40 250 #define SUNI_REGM_APSCS_Z1E 0x20 251 #define SUNI_REGM_APSCS_Zi1 0x10 252 #define SUNI_REGM_APSCS_PSBFI 0x08 253 #define SUNI_REGM_APSCS_COAPSI 0x04 254 #define SUNI_REGM_APSCS_RESERVED 0x02 255 #define SUNI_REGM_APSCS_PSBFV 0x01 256 #define SUNI_REGX_APSCS "\020\10PSBFE\7COAPSE\6Z1E\5Z1I\4PSBFI\3COAPSI\1PSBFV" 257 258 /* ultra */ 259 #define SUNI_REGN_LRXCFG "Line Receiver Configuration" 260 #define SUNI_REGO_LRXCFG 0x0C 261 #define SUNI_REGM_LRXCFG_RESERVED 0x01 262 #define SUNI_REGX_LRXCFG "\020" 263 264 /* 622 */ 265 #define SUNI_REGN_RK1 "Receive K1" 266 #define SUNI_REGO_RK1 0x0C 267 268 /* 622 */ 269 #define SUNI_REGN_RK2 "Receive K2" 270 #define SUNI_REGO_RK2 0x0D 271 272 /* 622 */ 273 #define SUNI_REGN_RZ1 "Receive Z1" 274 #define SUNI_REGO_RZ1 0x0E 275 276 /* 622 */ 277 #define SUNI_REGN_XZ1 "Transmit Z1" 278 #define SUNI_REGO_XZ1 0x0F 279 280 /* lite, ultra, 622 */ 281 #define SUNI_REGN_RSOPCIE "RSOP Control/Interrupt Enable" 282 #define SUNI_REGO_RSOPCIE 0x10 283 #define SUNI_REGO_RSOPCIE_BIPWORD_622 0x80 284 #define SUNI_REGM_RSOPCIE_DDS 0x40 285 #define SUNI_REGM_RSOPCIE_FOOF 0x20 286 #define SUNI_REGM_RSOPCIE_RESV 0x10 287 #define SUNI_REGM_RSOPCIE_ALGO2_622 0x10 288 #define SUNI_REGM_RSOPCIE_BIPEE 0x08 289 #define SUNI_REGM_RSOPCIE_LOSE 0x04 290 #define SUNI_REGM_RSOPCIE_LOFE 0x02 291 #define SUNI_REGM_RSOPCIE_OOFE 0x01 292 #define SUNI_REGX_RSOPCIE "\020\7DDS\6FOOF\4BIPEE\3LOSE\2LOFE\1OOFE" 293 #define SUNI_REGX_RSOPCIE_622 "\020\10BIPWORD\7DDS\6FOOF\5ALGO2\4BIPEE\3LOSE\2LOFE\1OOFE" 294 295 /* lite, ultra, 622 */ 296 #define SUNI_REGN_RSOPSIS "RSOP Status/Interrupt Status" 297 #define SUNI_REGO_RSOPSIS 0x11 298 #define SUNI_REGM_RSOPSIS_BIPEI 0x40 299 #define SUNI_REGM_RSOPSIS_LOSI 0x20 300 #define SUNI_REGM_RSOPSIS_LOFI 0x10 301 #define SUNI_REGM_RSOPSIS_OOFI 0x08 302 #define SUNI_REGM_RSOPSIS_LOSV 0x04 303 #define SUNI_REGM_RSOPSIS_LOFV 0x02 304 #define SUNI_REGM_RSOPSIS_OOFV 0x01 305 #define SUNI_REGX_RSOPSIS "\020\7BIPEI\6LOSI\5LOFI\4OOFI\3LOSV\2LOFV\1OOFV" 306 307 /* lite, ultra, 622 */ 308 #define SUNI_REGN_RSOP_BIP8 "RSOP Section BIP-8" 309 #define SUNI_REGO_RSOP_BIP8 0x12 /* +0x13 */ 310 311 /* lite, ultra, 622 */ 312 #define SUNI_REGN_TSOPCTRL "TSOP Control" 313 #define SUNI_REGO_TSOPCTRL 0x14 314 #define SUNI_REGM_TSOPCTRL_DS 0x40 315 #define SUNI_REGM_TSOPCTRL_LAIS 0x01 316 #define SUNI_REGM_TSOPCTRL_RESERVED 0x00 317 #define SUNI_REGX_TSOPCTRL "\020\7DS\1LAIS" 318 319 /* lite, ultra, 622 */ 320 #define SUNI_REGN_TSOPDIAG "TSOP Diagnostics" 321 #define SUNI_REGO_TSOPDIAG 0x15 322 #define SUNI_REGM_TSOPDIAG_DLOS 0x04 323 #define SUNI_REGM_TSOPDIAG_DBIP8 0x02 324 #define SUNI_REGM_TSOPDIAG_DFP 0x01 325 #define SUNI_REGX_TSOPDIAG "\020\3DLOS\2DBIP8\1DFP" 326 327 /* lite, ultra, 622 */ 328 #define SUNI_REGN_RLOPCTRL "RLOP Control/Status" 329 #define SUNI_REGO_RLOPCTRL 0x18 330 #define SUNI_REGO_RLOPCTRL_BIPWORD 0x80 331 #define SUNI_REGO_RLOPCTRL_ALLONES_622 0x40 332 #define SUNI_REGO_RLOPCTRL_AISDET_622 0x20 333 #define SUNI_REGO_RLOPCTRL_LRDIDET_622 0x10 334 #define SUNI_REGO_RLOPCTRL_BIPWORDO_622 0x08 335 #define SUNI_REGO_RLOPCTRL_LAISV 0x02 336 #define SUNI_REGO_RLOPCTRL_RDIV 0x01 337 #define SUNI_REGO_RLOPCTRL_RESERVED 0x00 338 #define SUNI_REGX_RLOPCTRL "\020\10BIPWORD\2LAISV\1RDIV" 339 #define SUNI_REGX_RLOPCTRL_622 "\020\10BIPWORD\7ALLONES\6AISDET\5LRDIDET\4BIPWORDO\2LAISV\1RDIV" 340 341 /* lite, ultra, 622 */ 342 #define SUNI_REGN_RLOPINTR "RLOP Interrupt Enable/Interrupt Status" 343 #define SUNI_REGO_RLOPINTR 0x19 344 #define SUNI_REGO_RLOPINTR_FEBEE 0x80 345 #define SUNI_REGO_RLOPINTR_BIPEE 0x40 346 #define SUNI_REGO_RLOPINTR_LAISE 0x20 347 #define SUNI_REGO_RLOPINTR_RDIE 0x10 348 #define SUNI_REGO_RLOPINTR_FEBEI 0x08 349 #define SUNI_REGO_RLOPINTR_BIPEI 0x04 350 #define SUNI_REGO_RLOPINTR_LAISI 0x02 351 #define SUNI_REGO_RLOPINTR_RDII 0x01 352 #define SUNI_REGX_RLOPINTR "\020\10FEBEE\7BIPEE\6LAISE\5DRIE\4FEBEI\3BIPEI\2LAISI\1RDII" 353 354 /* lite, ultra */ 355 #define SUNI_REGN_RLOPBIP8_24 "RLOP Line BIP-8/24" 356 #define SUNI_REGO_RLOPBIP8_24 0x1A /* +1B,1C */ 357 #define SUNI_REGM_RLOPBIP8_24 0x0F 358 359 /* 622 */ 360 #define SUNI_REGN_RLOPBIP8_24_96 "RLOP Line BIP-8/24/96" 361 #define SUNI_REGO_RLOPBIP8_24_96 0x1A /* +1B,1C */ 362 #define SUNI_REGM_RLOPBIP8_24_96 0x0F 363 364 /* lite, ultra, 622 */ 365 #define SUNI_REGN_RLOPFEBE "RLOP Line FEBE" 366 #define SUNI_REGO_RLOPFEBE 0x1D /* +1E,1F */ 367 #define SUNI_REGM_RLOPFEBE 0x0F 368 369 /* lite, ultra, 622 */ 370 #define SUNI_REGN_TLOPCTRL "TLOP Control" 371 #define SUNI_REGO_TLOPCTRL 0x20 372 #define SUNI_REGM_TLOPCTRL_APSREG_622 0x20 373 #define SUNI_REGM_TLOPCTRL_RDI 0x01 374 #define SUNI_REGM_TLOPCTRL_RESERVED 0x00 375 #define SUNI_REGX_TLOPCTRL "\020\1RDI" 376 #define SUNI_REGX_TLOPCTRL_622 "\020\6APSREG\1LRDI" 377 378 /* lite, ultra, 622 */ 379 #define SUNI_REGN_TLOPDIAG "TLOP Diagnostics" 380 #define SUNI_REGO_TLOPDIAG 0x21 381 #define SUNI_REGM_TLOPDIAG_DBIP 0x01 382 #define SUNI_REGX_TLOPDIAG "\020\1DBIP" 383 384 /* 622 */ 385 #define SUNI_REGN_TLOP_XK1 "TLOP Transmit K1" 386 #define SUNI_REGO_TLOP_XK1 0x22 387 388 /* 622 */ 389 #define SUNI_REGN_TLOP_XK2 "TLOP Transmit K2" 390 #define SUNI_REGO_TLOP_XK2 0x23 391 392 /* 622 */ 393 #define SUNI_REGN_SSTBCTRL "SSTB Control" 394 #define SUNI_REGO_SSTBCTRL 0x28 395 #define SUNI_REGM_SSTBCTRL_RRAMACC 0x40 396 #define SUNI_REGM_SSTBCTRL_RTIUIE 0x20 397 #define SUNI_REGM_SSTBCTRL_RTIMIE 0x10 398 #define SUNI_REGM_SSTBCTRL_PER5 0x08 399 #define SUNI_REGM_SSTBCTRL_TNULL 0x04 400 #define SUNI_REGM_SSTBCTRL_NOSYNC 0x02 401 #define SUNI_REGM_SSTBCTRL_LEN16 0x01 402 #define SUNI_REGX_SSTBCTRL "\020\7RRAMACC\6RTIUIE\5RTIMIE\4PER5\3TNULL\2NOSYNC\1LEN16" 403 404 /* 622 */ 405 #define SUNI_REGN_SSTBSTIS "SSTB Section Trace Identifier Status" 406 #define SUNI_REGO_SSTBSTIS 0x29 407 #define SUNI_REGM_SSTBSTIS_BUSY 0x80 408 #define SUNI_REGM_SSTBSTIS_RTIUI 0x08 409 #define SUNI_REGM_SSTBSTIS_RTIUV 0x04 410 #define SUNI_REGM_SSTBSTIS_RTIMI 0x02 411 #define SUNI_REGM_SSTBSTIS_RTIMV 0x01 412 #define SUNI_REGX_SSTBSTIS "\020\10BUSY\4RTIUI\3RTIUV\2RTIMI\1RTIMV" 413 414 /* 622 */ 415 #define SUNI_REGN_SSTBIAR "SSTB Indirect Address Register" 416 #define SUNI_REGO_SSTBIAR 0x2A 417 #define SUNI_REGM_SSTBIAR_RWB 0x80 418 #define SUNI_REGM_SSTBIAR_A 0x7F 419 #define SUNI_REGX_SSTBIAR "\020\10RWB\12\x7f\2" 420 421 /* 622 */ 422 #define SUNI_REGN_SSTBIDR "SSTB Indirect Data Register" 423 #define SUNI_REGO_SSTBIDR 0x2B 424 425 #if 0 /* see chip errata */ 426 /* 622 */ 427 #define SUNI_REGN_SSTBECSM "SSTB Expected Clock Synchronization Message" 428 #define SUNI_REGO_SSTBECSM 0x2C 429 #endif 430 431 /* 622 */ 432 #define SUNI_REGN_SSTBCSMS "SSTB Clock Synchronisation Message Status" 433 #define SUNI_REGO_SSTBCSMS 0x2D 434 #define SUNI_REGM_SSTBCSMS_RCSMUIE 0x80 435 #define SUNI_REGM_SSTBCSMS_RCSMMIE 0x40 436 #define SUNI_REGM_SSTBCSMS_RCSMUI 0x08 437 #define SUNI_REGM_SSTBCSMS_RCSMUV 0x04 438 #define SUNI_REGM_SSTBCSMS_RCSMMI 0x02 439 #define SUNI_REGM_SSTBCSMS_RCSMMV 0x01 440 #define SUNI_REGX_SSTBCSMS "\020\10RCSMUIE\7RCSMMIE\4RCSMUI\3RCSMUV\2RCSMMI\1RCSMMV" 441 442 /* lite, ultra, 622 */ 443 #define SUNI_REGN_RPOPCTRL "RPOP Status/Control" 444 #define SUNI_REGO_RPOPCTRL 0x30 445 #define SUNI_REGM_RPOPCTRL_LOP 0x20 446 #define SUNI_REGM_RPOPCTRL_PAIS 0x08 447 #define SUNI_REGM_RPOPCTRL_PRDI 0x04 448 #define SUNI_REGM_RPOPCTRL_NEWPTRI_622 0x02 449 #define SUNI_REGM_RPOPCTRL_NEWPTRE_622 0x01 450 #define SUNI_REGM_RPOPCTRL_RESERVED 0x00 451 #define SUNI_REGX_RPOPCTRL "\020\6LOP\4PAIS\3PRDI" 452 #define SUNI_REGX_RPOPCTRL_622 "\020\6LOP\4PAIS\3PRDI\2NEWPTRI\1NEWPTRE" 453 454 /* lite, ultra, 622 */ 455 #define SUNI_REGN_RPOPISTAT "RPOP Interrupt Status" 456 #define SUNI_REGO_RPOPISTAT 0x31 457 #define SUNI_REGM_RPOPISTAT_PSLI 0x80 458 #define SUNI_REGM_RPOPISTAT_LOPI 0x20 459 #define SUNI_REGM_RPOPISTAT_PAISI 0x08 460 #define SUNI_REGM_RPOPISTAT_PRDII 0x04 461 #define SUNI_REGM_RPOPISTAT_BIPEI 0x02 462 #define SUNI_REGM_RPOPISTAT_FEBEI 0x01 463 #define SUNI_REGX_RPOPISTAT "\02010PSLI\6LOPI\4PAISI\3PRDII\2BIPEI\1FEBEI" 464 465 /* 622 */ 466 #define SUNI_REGN_RPOPPIS "RPOP Pointer Interrupt Status" 467 #define SUNI_REGO_RPOPPIS 0x32 468 #define SUNI_REGM_RPOPPIS_ILLJREQI 0x80 469 #define SUNI_REGM_RPOPPIS_DISCOPAI 0x20 470 #define SUNI_REGM_RPOPPIS_INVNDFI 0x10 471 #define SUNI_REGM_RPOPPIS_ILLPTRI 0x08 472 #define SUNI_REGM_RPOPPIS_NSEI 0x04 473 #define SUNI_REGM_RPOPPIS_PSEI 0x02 474 #define SUNI_REGM_RPOPPIS_NDFI 0x01 475 #define SUNI_REGX_RPOPPIS "\020\10ILLJREQI\6DISCOPAI\5INVNDFI\4ILLPTRI\3NSEI\2PSEI\1NDFI" 476 477 /* lite, ultra, 622 */ 478 #define SUNI_REGN_RPOPIEN "RPOP Interrupt Enable" 479 #define SUNI_REGO_RPOPIEN 0x33 480 #define SUNI_REGM_RPOPIEN_PSLE 0x80 481 #define SUNI_REGM_RPOPIEN_LOPE 0x20 482 #define SUNI_REGM_RPOPIEN_PAISE 0x08 483 #define SUNI_REGM_RPOPIEN_PRDIE 0x04 484 #define SUNI_REGM_RPOPIEN_BIPEE 0x02 485 #define SUNI_REGM_RPOPIEN_FEBEE 0x01 486 #define SUNI_REGM_RPOPIEN_RESERVED 0x00 487 #define SUNI_REGX_RPOPIEN "\02010PSLE\6LOPE\4PAISE\3PRDIE\2BIPEE\1FEBEE" 488 489 /* 622 */ 490 #define SUNI_REGN_RPOPPIE "RPOP Pointer Interrupt Enable" 491 #define SUNI_REGO_RPOPPIE 0x34 492 #define SUNI_REGM_RPOPPIE_ILLJREQE 0x80 493 #define SUNI_REGM_RPOPPIE_DISCOPAE 0x20 494 #define SUNI_REGM_RPOPPIE_INVNDFE 0x10 495 #define SUNI_REGM_RPOPPIE_ILLPTRE 0x08 496 #define SUNI_REGM_RPOPPIE_NSEE 0x04 497 #define SUNI_REGM_RPOPPIE_PSEE 0x02 498 #define SUNI_REGM_RPOPPIE_NDFE 0x01 499 #define SUNI_REGX_RPOPPIE "\020\10ILLJREQE\6DISCOPAE\5INVNDFE\4ILLPTRE\3NSEE\2PSEE\1NDFE" 500 501 /* 622 */ 502 #define SUNI_REGN_RPOPPTR "RPOP Pointer" 503 #define SUNI_REGO_RPOPPTR 0x35 /* +36 */ 504 #define SUNI_REGM_RPOPPTR_RDI10 0x20 505 #define SUNI_REGM_RPOPPTR_S 0x0c 506 #define SUNI_REGS_RPOPPTR_S 2 507 #define SUNI_REGM_RPOPPTR 0x03 508 #define SUNI_REGS_RPOPPTR 0 509 #define SUNI_REGX_RPOPPTR "\020\6RDI10\12\xc\20S" 510 511 /* lite, ultra, 622 */ 512 #define SUNI_REGN_RPOPPSL "RPOP Path Signal Label" 513 #define SUNI_REGO_RPOPPSL 0x37 514 515 /* lite, ultra, 622 */ 516 #define SUNI_REGN_RPOPBIP8 "RPOP Path BIP-8" 517 #define SUNI_REGO_RPOPBIP8 0x38 /* +39 */ 518 519 /* lite, ultra, 622 */ 520 #define SUNI_REGN_RPOPFEBE "RPOP Path FEBE" 521 #define SUNI_REGO_RPOPFEBE 0x3A /* +3B */ 522 523 /* 622 */ 524 #define SUNI_REGN_RPOPRDI "RPOP RDI" 525 #define SUNI_REGO_RPOPRDI 0x3C 526 #define SUNI_REGM_RPOPRDI_BLKFEBE 0x10 527 #define SUNI_REGM_RPOPRDI_ARDIE 0x02 528 #define SUNI_REGM_RPOPRDI_ARDIV 0x01 529 #define SUNI_REGM_RPOPRDI_RESERVED 0x00 530 #define SUNI_REGX_RPOPRDI "\020\5BLKFEBE\2ARDIE\1ARDIV" 531 532 /* lite, ultra */ 533 #define SUNI_REGN_RPOPBIP8CFG "RPOP Path BIP-8 Configuration" 534 #define SUNI_REGO_RPOPBIP8CFG 0x3D 535 #define SUNI_REGM_RPOPBIP8CFG_BLKBIP 0x20 536 #define SUNI_REGM_RPOPBIP8CFG_RESERVED 0x00 537 #define SUNI_REGX_RPOPBIP8CFG "\020\6BLKBIP" 538 539 /* 622 */ 540 #define SUNI_REGN_RPOPRING "RPOP Ring Control" 541 #define SUNI_REGO_RPOPRING 0x3D 542 #define SUNI_REGM_RPOPRING_SOS 0x80 543 #define SUNI_REGM_RPOPRING_ENSS 0x40 544 #define SUNI_REGM_RPOPRING_BLKBIP 0x20 545 #define SUNI_REGM_RPOPRING_DISFS 0x10 546 #define SUNI_REGM_RPOPRING_BLKBIPO 0x08 547 #define SUNI_REGM_RPOPRING_RESERVED 0x00 548 #define SUNI_REGX_RPOPRING "\020\10SOS\7ENSS\6BLKBIP\5DISFS\4BLKBIPO" 549 550 /* lite, ultra, 622 */ 551 #define SUNI_REGN_TPOPCTRL "TPOP Control/Diagnostic" 552 #define SUNI_REGO_TPOPCTRL 0x40 553 #define SUNI_REGM_TPOPCTRL_EXCFS 0x80 /* 622 */ 554 #define SUNI_REGM_TPOPCTRL_DB3 0x02 555 #define SUNI_REGM_TPOPCTRL_PAIS 0x01 556 #define SUNI_REGM_TPOPCTRL_RESERVED 0x00 557 #define SUNI_REGX_TPOPCTRL "\020\2DB3\1PAIS" 558 #define SUNI_REGX_TPOPCTRL_622 "\020\4EXCFS\2DB3\1PAIS" 559 560 /* lite, ultra, 622 */ 561 #define SUNI_REGN_TPOPPTRC "TPOP Pointer Control" 562 #define SUNI_REGO_TPOPPTRC 0x41 563 #define SUNI_REGM_TPOPPTRC_FTPTR 0x40 564 #define SUNI_REGM_TPOPPTRC_SOS 0x20 565 #define SUNI_REGM_TPOPPTRC_PLD 0x10 566 #define SUNI_REGM_TPOPPTRC_NDF 0x08 567 #define SUNI_REGM_TPOPPTRC_NSE 0x04 568 #define SUNI_REGM_TPOPPTRC_PSE 0x02 569 #define SUNI_REGM_TPOPPTRC_RESERVED 0x00 570 #define SUNI_REGX_TPOPPTRC "\020\7FTPTR\6SOS\5PLD\4NDF\3NSE\2PSE" 571 572 /* 622 */ 573 #define SUNI_REGN_TPOPCP "TPOP Current Pointer" 574 #define SUNI_REGO_TPOPCP 0x43 /* +44 */ 575 #define SUNI_REGM_TPOPCP 0x03 576 #define SUNI_REGS_TPOPCP 0 577 #define SUNI_REGX_TPOPCP "\020" 578 579 /* lite, ultra, 622 */ 580 #define SUNI_REGN_TPOPAPTR "TPOP Arbitrary Pointer" 581 #define SUNI_REGO_TPOPAPTR 0x45 /* +46 */ 582 #define SUNI_REGM_TPOPAPTR_NDF 0xF0 583 #define SUNI_REGS_TPOPAPTR_NDF 4 584 #define SUNI_REGM_TPOPAPTR_S 0x0C 585 #define SUNI_REGS_TPOPAPTR_S 2 586 #define SUNI_REGM_TPOPAPTR 0x03 587 #define SUNI_REGS_TPOPAPTR 0 588 #define SUNI_REGX_TPOPAPTR "\020\12\x0C\12S\12\xF0\12NDF" 589 590 #define SUNI_REGM_SONET 0 591 #define SUNI_REGM_SDH 2 592 593 /* 622 */ 594 #define SUNI_REGN_TPOPPT "TPOP Path Trace" 595 #define SUNI_REGO_TPOPPT 0x47 596 597 /* lite, ultra, 622 */ 598 #define SUNI_REGN_TPOPPSL "TPOP Path Signal Label" 599 #define SUNI_REGO_TPOPPSL 0x48 600 601 /* lite, ultra, 622 */ 602 #define SUNI_REGN_TPOPSTATUS "TPOP Path Status" 603 #define SUNI_REGO_TPOPSTATUS 0x49 604 #define SUNI_REGM_TPOPSTATUS_FEBE 0xF0 605 #define SUNI_REGS_TPOPSTATUS_FEBE 4 606 #define SUNI_REGM_TPOPSTATUS_PRDI 0x08 607 #define SUNI_REGM_TPOPSTATUS_G1 0x07 608 #define SUNI_REGS_TPOPSTATUS_G1 0 609 #define SUNI_REGX_TPOPSTATUS "\020\12\xF0\12FEBE\4PRDI\12\x7\12G" 610 611 /* 622 */ 612 #define SUNI_REGN_TPOPPUC "TPOP Path User Channel" 613 #define SUNI_REGO_TPOPPUC 0x4A 614 615 /* 622 */ 616 #define SUNI_REGN_TPOPPG1 "TPOP Path Grow #1" 617 #define SUNI_REGO_TPOPPG1 0x4B 618 619 /* 622 */ 620 #define SUNI_REGN_TPOPPG2 "TPOP Path Grow #2" 621 #define SUNI_REGO_TPOPPG2 0x4C 622 623 /* 622 */ 624 #define SUNI_REGN_TPOPPG3 "TPOP Path Grow #3" 625 #define SUNI_REGO_TPOPPG3 0x4D 626 627 /* lite, ultra, 622 */ 628 #define SUNI_REGN_RACPCTRL "RACP Control/Status" 629 #define SUNI_REGO_RACPCTRL 0x50 630 #define SUNI_REGM_RACPCTRL_OOCDV 0x80 631 #define SUNI_REGM_RACPCTRL_FSEN 0x80 632 #define SUNI_REGM_RACPCTRL_RXPTYP 0x40 633 #define SUNI_REGM_RACPCTRL_PASS 0x20 634 #define SUNI_REGM_RACPCTRL_DISCOR 0x10 635 #define SUNI_REGM_RACPCTRL_HCSPASS 0x08 636 #define SUNI_REGM_RACPCTRL_HCSADD 0x04 637 #define SUNI_REGM_RACPCTRL_DDSCR 0x02 638 #define SUNI_REGM_RACPCTRL_FIFORST 0x01 639 #define SUNI_REGX_RACPCTRL "\020\10OOCDV\7RXPTYP\6PASS\5DISCO\4HCSPASS\3HCSADD\2DDSCR\1FIFORST" 640 #define SUNI_REGX_RACPCTRL_622 "\020\10FSEN\7RXPTYP\6PASS\5DISCO\4HCSPASS\3HCSADD\2DDSCR\1FIFORST" 641 642 /* lite, ultra */ 643 #define SUNI_REGN_RACPINTR "RACP Interrupt Enable/Status" 644 #define SUNI_REGO_RACPINTR 0x51 645 #define SUNI_REGM_RACPINTR_OOCDE 0x80 646 #define SUNI_REGM_RACPINTR_HCSE 0x40 647 #define SUNI_REGM_RACPINTR_FIFOE 0x20 648 #define SUNI_REGM_RACPINTR_OOCDI 0x10 649 #define SUNI_REGM_RACPINTR_CHCSI 0x08 650 #define SUNI_REGM_RACPINTR_UHCSI 0x04 651 #define SUNI_REGM_RACPINTR_FOVRI 0x02 652 #define SUNI_REGX_RACPINTR "\020\10OOCDE\7HCSE\6FIFOE\5OOCDI\4CHCSI\3UHCSI\2FOVRI" 653 654 /* 622 */ 655 #define SUNI_REGN_RACPIS "RACP Interrupt Status" 656 #define SUNI_REGO_RACPIS 0x51 657 #define SUNI_REGM_RACPIS_OCDV 0x80 658 #define SUNI_REGM_RACPIS_LCDV 0x40 659 #define SUNI_REGM_RACPIS_OCDI 0x20 660 #define SUNI_REGM_RACPIS_LCDI 0x10 661 #define SUNI_REGM_RACPIS_CHCSI 0x08 662 #define SUNI_REGM_RACPIS_UHCSI 0x04 663 #define SUNI_REGM_RACPIS_FOVRI 0x02 664 #define SUNI_REGM_RACPIS_FUDRI 0x01 665 #define SUNI_REGX_RACPIS "\020\10OCDV\7LCDV\6OCDI\5LCDI\4CHCSI\3UHCSI\2FOVRI\1FUDRI" 666 667 /* lite, ultra */ 668 #define SUNI_REGN_RACPPATTERN "RACP Match Header Pattern" 669 #define SUNI_REGO_RACPPATTERN 0x52 670 #define SUNI_REGM_RACPPATTERN_GFC 0xF0 671 #define SUNI_REGS_RACPPATTERN_GFC 4 672 #define SUNI_REGM_RACPPATTERN_PTI 0x0E 673 #define SUNI_REGS_RACPPATTERN_PTI 1 674 #define SUNI_REGM_RACPPATTERN_CLP 0x01 675 #define SUNI_REGS_RACPPATTERN_CLP 0 676 #define SUNI_REGX_RACPPATTERN "\020\12\xF0\12GFC\12\x0E\12PTI\1CLP" 677 678 /* 622 */ 679 #define SUNI_REGN_RACPIEC "RACP Interrupt Enable/Control" 680 #define SUNI_REGO_RACPIEC 0x52 681 #define SUNI_REGM_RACPIEC_OCDE 0x80 682 #define SUNI_REGM_RACPIEC_LCDE 0x40 683 #define SUNI_REGM_RACPIEC_HCSE 0x20 684 #define SUNI_REGM_RACPIEC_FIFOE 0x10 685 #define SUNI_REGM_RACPIEC_LCDDROP 0x08 686 #define SUNI_REGM_RACPIEC_RCALEVEL0 0x04 687 #define SUNI_REGM_RACPIEC_HCSFTR 0x03 688 #define SUNI_REGX_RACPIEC "\020\10OCDE\7LCDE\6HCSE\5FIFOE\4LCDDROP\3RCALEVEL0\12\0x3\12HCSFTR" 689 690 /* lite, ultra */ 691 #define SUNI_REGN_RACPMASK "RACP Match Header Mask" 692 #define SUNI_REGO_RACPMASK 0x53 693 #define SUNI_REGM_RACPMASK_MGFC 0xF0 694 #define SUNI_REGS_RACPMASK_MGFC 4 695 #define SUNI_REGM_RACPMASK_MPTI 0x0E 696 #define SUNI_REGS_RACPMASK_MPTI 1 697 #define SUNI_REGM_RACPMASK_MCLP 0x01 698 #define SUNI_REGS_RACPMASK_MCLP 0 699 #define SUNI_REGX_RACPMASK "\020\12\xF0\12MGFC\12\x0E\12MPTI\1MCLP" 700 701 /* 622 */ 702 #define SUNI_REGO_RACPPATTERN_622 0x53 703 704 /* lite, ultra */ 705 #define SUNI_REGN_RACPCHCS "RACP Correctable HCS Error Count" 706 #define SUNI_REGO_RACPCHCS 0x54 707 708 /* 622 */ 709 #define SUNI_REGO_RACPMASK_622 0x54 710 711 /* lite, ultra */ 712 #define SUNI_REGN_RACPUHCS "RACP Uncorrectable HCS Error Count" 713 #define SUNI_REGO_RACPUHCS 0x55 714 715 /* 622 */ 716 #define SUNI_REGO_RACPCHCS_622 0x55 /* +56 */ 717 #define SUNI_REGM_RACPCHCS_622 0x0f 718 719 /* lite, ultra */ 720 #define SUNI_REGN_RACPCNT "RACP Receive Cell Counter" 721 #define SUNI_REGO_RACPCNT 0x56 /* +57,58 */ 722 #define SUNI_REGM_RACPCNT 0x07 723 724 /* 622 */ 725 #define SUNI_REGO_RACPUHCS_622 0x57 /* +58 */ 726 #define SUNI_REGM_RACPUHCS_622 0x0f 727 728 /* 622 */ 729 #define SUNI_REGO_RACPCNT_622 0x59 /* +5A,5B */ 730 #define SUNI_REGM_RACPCNT_622 0x1F 731 732 /* lite, ultra */ 733 #define SUNI_REGN_RACPCFG "RACP Configuration" 734 #define SUNI_REGO_RACPCFG 0x59 735 #define SUNI_REGM_RACPCFG_RGFCE 0xF0 736 #define SUNI_REGS_RACPCFG_RGFCE 4 737 #define SUNI_REGM_RACPCFG_FSEN 0x08 738 #define SUNI_REGM_RACPCFG_LEVEL0 0x04 739 #define SUNI_REGM_RACPCFG_HCSFTR 0x03 740 #define SUNI_REGS_RACPCFG_HCSFTR 0 741 #define SUNI_REGX_RACPCFG "\020\12\xF0\20RGFCE\4FSEN\3RCALEVEL0\12\x03\12HCSFTR" 742 743 /* 622 */ 744 #define SUNI_REGN_RACPGFC "RACP GFC Control/Misc. Control" 745 #define SUNI_REGO_RACPGFC 0x5C 746 #define SUNI_REGM_RACPGFC_CDDIS 0x80 747 #define SUNI_REGM_RACPGFC_RXBYTEPRTY 0x40 748 #define SUNI_REGM_RACPGFC_RGFCE 0x0f 749 #define SUNI_REGX_RACPGFC "\020\10CDDIS\7RXBYTEPRTY\12\xf\2" 750 751 /* lite, ultra, 622 */ 752 #define SUNI_REGN_TACPCTRL "TACP Control/Status" 753 #define SUNI_REGO_TACPCTRL 0x60 754 #define SUNI_REGM_TACPCTRL_FIFOE 0x80 755 #define SUNI_REGM_TACPCTRL_TSOCI 0x40 756 #define SUNI_REGM_TACPCTRL_FOVRI 0x20 757 #define SUNI_REGM_TACPCTRL_DHCS 0x10 758 #define SUNI_REGM_TACPCTRL_HCSB 0x08 /* ultra, 622 */ 759 #define SUNI_REGM_TACPCTRL_HCSADD 0x04 760 #define SUNI_REGM_TACPCTRL_DSCR 0x02 761 #define SUNI_REGM_TACPCTRL_FIFORST 0x01 762 #define SUNI_REGX_TACPCTRL_LITE "\020\10FIFOE\7TSOCI\6FOVRI\5DHCS\3HCSADD\2DSCR\1FIFORST" 763 #define SUNI_REGX_TACPCTRL_ULTRA "\020\10FIFOE\7TSOCI\6FOVRI\5DHCS\4HCSB\3HCSADD\2DSCR\1FIFORST" 764 #define SUNI_REGX_TACPCTRL_622 "\020\10FIFOE\7TSOCI\6FOVRI\5DHCS\4HCSB\3HCSADD\2DSCR\1FIFORST" 765 766 /* lite, ultra, 622 */ 767 #define SUNI_REGN_TACPIDLEH "TACP Idle/Unassigned Cell Header Pattern" 768 #define SUNI_REGO_TACPIDLEH 0x61 769 #define SUNI_REGM_TACPIDLEH_GFC 0xF0 770 #define SUNI_REGS_TACPIDLEH_GFC 4 771 #define SUNI_REGM_TACPIDLEH_PTI 0x0E 772 #define SUNI_REGS_TACPIDLEH_PTI 1 773 #define SUNI_REGM_TACPIDLEH_CLP 0x01 774 #define SUNI_REGS_TACPIDLEH_CLP 0 775 #define SUNI_REGX_TACPIDLEH "\020\12\xF0\20GFC\12\x0E\20PTI\12\x01\20CLP" 776 777 /* lite, ultra, 622 */ 778 #define SUNI_REGN_TACPIDLEP "TACP Idle/Unassigned Cell Payload Octet Pattern" 779 #define SUNI_REGO_TACPIDLEP 0x62 780 781 /* lite, ultra, 622 */ 782 #define SUNI_REGN_TACPFIFOC "TACP FIFO Control" 783 #define SUNI_REGO_TACPFIFOC 0x63 784 #define SUNI_REGM_TACPFIFOC_TXPTYP 0x80 785 #define SUNI_REGM_TACPFIFOC_TXPRTYE 0x40 786 #define SUNI_REGM_TACPFIFOC_TXPRTYI 0x10 787 #define SUNI_REGM_TACPFIFOC_TXPRTYI_622 0x30 788 #define SUNI_REGS_TACPFIFOC_TXPRTYI_622 4 789 #define SUNI_REGM_TACPFIFOC_FIFODP 0x0C 790 #define SUNI_REGS_TACPFIFOC_FIFODP 2 791 #define SUNI_REGM_TACPFIFOC_TCALEVEL0 0x02 792 #define SUNI_REGM_TACPFIFOC_HCSCTLEB 0x01 793 #define SUNI_REGM_TACPFIFOC_RESERVED 0x00 794 #define SUNI_REGX_TACPFIFOC "\020\10TXPTYP\7TXPRTYE\5TXPRTYI\12\x0C\20FIFODP\2TCALEVEL0" 795 #define SUNI_REGX_TACPFIFOC_622 "\020\10TXPTYP\7TXPRTYE\12\x30\12TXPRTYI\12\x0C\20FIFODP\2TCALEVEL0\1HCSCTLEB" 796 797 /* lite, ultra, 622 */ 798 #define SUNI_REGN_TACPCNT "TACP Transmit Cell Counter" 799 #define SUNI_REGO_TACPCNT 0x64 /* +65,66 */ 800 #define SUNI_REGM_TACPCNT 0x07 801 #define SUNI_REGM_TACPCNT_622 0x1F 802 803 /* lite, ultra */ 804 #define SUNI_REGN_TACPCFG "TACP Configuration" 805 #define SUNI_REGO_TACPCFG 0x67 806 #define SUNI_REGM_TACPCFG_TGFCE 0xF0 807 #define SUNI_REGS_TACPCFG_TGFCE 4 808 #define SUNI_REGM_TACPCFG_FSEN 0x08 809 #define SUNI_REGM_TACPCFG_H4INSB 0x04 810 #define SUNI_REGM_TACPCFG_FIXBYTE 0x03 811 #define SUNI_REGS_TACPCFG_FIXBYTE 0 812 #define SUNI_REGX_TACPCFG "\020\12\xF0\20TGFCE\4FSEN\3H4INSB\12\x03\20FIXBYTE" 813 814 /* 622 */ 815 #define SUNI_REGN_TACPGFC "TACP Fixed Stuff/GFC" 816 #define SUNI_REGO_TACPGFC 0x67 817 #define SUNI_REGO_TACPGFC_TGFCE 0xf0 818 #define SUNI_REGS_TACPGFC_TGFCE 4 819 #define SUNI_REGO_TACPGFC_FSEN 0x08 820 #define SUNI_REGO_TACPGFC_TXBYTEPRTY 0x04 821 #define SUNI_REGO_TACPGFC_FIXBYTE 0x03 822 #define SUNI_REGS_TACPGFC_FIXBYTE 0 823 #define SUNI_REGX_TACPGFC "\020\12\xf0\20TGFCE\4FSEN\3TXBYTEPRTY\12\x3\20FIXBYTE" 824 825 /* 622 */ 826 #define SUNI_REGN_SPTBCTRL "SPTB Control" 827 #define SUNI_REGO_SPTBCTRL 0x68 828 #define SUNI_REGO_SPTBCTRL_RRAMACC 0x40 829 #define SUNI_REGO_SPTBCTRL_RTIUIE 0x20 830 #define SUNI_REGO_SPTBCTRL_RTIMIE 0x10 831 #define SUNI_REGO_SPTBCTRL_PER5 0x08 832 #define SUNI_REGO_SPTBCTRL_TNULL 0x04 833 #define SUNI_REGO_SPTBCTRL_NOSYNC 0x02 834 #define SUNI_REGO_SPTBCTRL_LEN16 0x01 835 #define SUNI_REGX_SPTBCTRL "\020\7RRAMACC\6RTIUIE\5RTIMIE\4PER5\3TNULL\2NOSYNC\1LEN16" 836 837 /* 622 */ 838 #define SUNI_REGN_SPTBPTIS "SPTB Path Trace Identifier Status" 839 #define SUNI_REGO_SPTBPTIS 0x69 840 #define SUNI_REGM_SPTBPTIS_BUSY 0x80 841 #define SUNI_REGM_SPTBPTIS_RTIUI 0x08 842 #define SUNI_REGM_SPTBPTIS_RTIUV 0x04 843 #define SUNI_REGM_SPTBPTIS_RTIMI 0x02 844 #define SUNI_REGM_SPTBPTIS_RTIMV 0x01 845 #define SUNI_REGX_SPTBPTIS "\020\10BUSY\4RTIUI\3RTIUV\2RTIMI\1RTIMV" 846 847 /* 622 */ 848 #define SUNI_REGN_SPTBIAR "SPTB Indirect Address Register" 849 #define SUNI_REGO_SPTBIAR 0x6A 850 #define SUNI_REGM_SPTBIAR_RWB 0x80 851 #define SUNI_REGM_SPTBIAR_A 0x7f 852 #define SUNI_REGX_SPTBIAR "\020\10RWB\12\x7f\20A" 853 854 /* 622 */ 855 #define SUNI_REGN_SPTBIDR "SPTB Indirect Data Register" 856 #define SUNI_REGO_SPTBIDR 0x6B 857 858 /* 622 */ 859 #define SUNI_REGN_SPTBEPSL "SPTB Expected Path Signal Label" 860 #define SUNI_REGO_SPTBEPSL 0x6C 861 862 /* 622 */ 863 #define SUNI_REGN_SPTBPSLS "SPTB Path Signal Label Status" 864 #define SUNI_REGO_SPTBPSLS 0x6D 865 #define SUNI_REGM_SPTBPSLS_RPSLUIE 0x80 866 #define SUNI_REGM_SPTBPSLS_RPSLMIE 0x40 867 #define SUNI_REGM_SPTBPSLS_RPSLUI 0x08 868 #define SUNI_REGM_SPTBPSLS_RPSLUV 0x04 869 #define SUNI_REGM_SPTBPSLS_RPSLMI 0x02 870 #define SUNI_REGM_SPTBPSLS_RPSLMV 0x01 871 #define SUNI_REGX_SPTBPSLS "\020\10RPSLUIE\7RPSLMIE\4RPSLUI\3RPSLUV\2RPSLMI\1RPSLMV" 872 873 /* ultra */ 874 #define SUNI_REGN_POPCCTRL "POPC Control" 875 #define SUNI_REGO_POPCCTRL 0x68 876 #define SUNI_REGM_POPCCTRL_PDAT 0xC0 877 #define SUNI_REGS_POPCCTRL_PDAT 6 878 #define SUNI_REGM_POPCCTRL_TOGGLE 0x30 879 #define SUNI_REGS_POPCCTRL_TOGGLE 4 880 #define SUNI_REGM_POPCCTRL_TRAFFIC 0x02 881 #define SUNI_REGM_POPCCTRL_ALARM 0x01 882 #define SUNI_REGX_POPCCTRL "\020\12\xC0\20PDAT\12\x30\20TOGGLE\2TRAFFIC\1ALARM" 883 884 /* ultra */ 885 #define SUNI_REGN_POPCSTROBE0 "POPC Strobe Rate 0" 886 #define SUNI_REGO_POPCSTROBE0 0x69 887 888 /* ultra */ 889 #define SUNI_REGN_POPCSTROBE1 "POPC Strobe Rate 1" 890 #define SUNI_REGO_POPCSTROBE1 0x6A 891 892 /* 622 */ 893 #define SUNI_REGN_BERMCTRL "BERM Control" 894 #define SUNI_REGO_BERMCTRL 0x70 895 #define SUNI_REGM_BERMCTRL_BERTEN 0x80 896 #define SUNI_REGM_BERMCTRL_BERIE 0x01 897 #define SUNI_REGX_BERMCTRL "\020\10BERTEN\1BERIE" 898 899 /* 622 */ 900 #define SUNI_REGN_BERMINT "BERM Interrupt" 901 #define SUNI_REGO_BERMINT 0x71 902 #define SUNI_REGM_BERMINT_TST 0xf0 903 #define SUNI_REGS_BERMINT_TST 4 904 #define SUNI_REGM_BERMINT_BERI 0x01 905 #define SUNI_REGX_BERMINT "\020\12\xf0\20BERM_TST\1BERI" 906 907 /* 622 */ 908 #define SUNI_REGN_BERMLAP "BERM Line BIP Accumulation Period" 909 #define SUNI_REGO_BERMLAP 0x72 /* +73 */ 910 911 /* 622 */ 912 #define SUNI_REGN_BERMLT "BERM Line BIP Threshold" 913 #define SUNI_REGO_BERMLT 0x74 /* +75 */ 914 915 /* lite, ultra, 622 */ 916 #define SUNI_REGN_MTEST "Master Test" 917 #define SUNI_REGO_MTEST 0x80 918 #define SUNI_REGM_MTEST_DS27_53_622 0x80 919 #define SUNI_REGM_MTEST_BYPASS_ULTRA 0x40 920 #define SUNI_REGM_MTEST_PMCATST_ULTRA 0x20 921 #define SUNI_REGM_MTEST_PMCTST 0x10 922 #define SUNI_REGM_MTEST_DBCTRL 0x08 923 #define SUNI_REGM_MTEST_IOTST 0x04 924 #define SUNI_REGM_MTEST_HIZDATA 0x02 925 #define SUNI_REGM_MTEST_HIZIO 0x01 926 #define SUNI_REGX_MTEST_LITE "\020\5PMCTST\4DBCTRL\3IOTST\2HIZDATA\1HIZIO" 927 #define SUNI_REGX_MTEST_ULTRA "\020\7BYPASS\6PMCATST\5PMCTST\4DBCTRL\3IOTST\2HIZDATA\1HIZIO" 928 #define SUNI_REGX_MTEST_622 "\020\10DS27_53\5PMCTST\4DBCTRL\3IOTST\2HIZDATA\1HIZIO" 929 930 /* 931 * Printing support 932 */ 933 #define SUNI_PRINT_LITE \ 934 { /* 00 */ \ 935 UTP_REGT_BITS, SUNI_REGO_MRESET, \ 936 SUNI_REGN_MRESET, SUNI_REGX_MRESET_LITE }, \ 937 { /* 01 */ \ 938 UTP_REGT_BITS, SUNI_REGO_MCONFIG, \ 939 SUNI_REGN_MCONFIG, SUNI_REGX_MCONFIG_LITE }, \ 940 { /* 02 */ \ 941 UTP_REGT_BITS, SUNI_REGO_MISTATUS, \ 942 SUNI_REGN_MISTATUS, SUNI_REGX_MISTATUS_LITE }, \ 943 /* 03 unused */ \ 944 { /* 04 */ \ 945 UTP_REGT_BITS, SUNI_REGO_MCLKM, \ 946 SUNI_REGN_MCLKM, SUNI_REGX_MCLKM_LITE }, \ 947 { /* 05 */ \ 948 UTP_REGT_BITS, SUNI_REGO_MCTRL, \ 949 SUNI_REGN_MCTRL, SUNI_REGX_MCTRL_LITE }, \ 950 { /* 06 */ \ 951 UTP_REGT_BITS, SUNI_REGO_CLKSYN, \ 952 SUNI_REGN_CLKSYN, SUNI_REGX_CLKSYN_LITE }, \ 953 { /* 07 */ \ 954 UTP_REGT_BITS, SUNI_REGO_CLKREC_LITE, \ 955 SUNI_REGN_CLKREC, SUNI_REGX_CLKREC_LITE }, \ 956 /* 08-0F unused */ \ 957 { /* 10 */ \ 958 UTP_REGT_BITS, SUNI_REGO_RSOPCIE, \ 959 SUNI_REGN_RSOPCIE, SUNI_REGX_RSOPCIE }, \ 960 { /* 11 */ \ 961 UTP_REGT_BITS, SUNI_REGO_RSOPSIS, \ 962 SUNI_REGN_RSOPSIS, SUNI_REGX_RSOPSIS }, \ 963 { /* 12, 13 */ \ 964 UTP_REGT_INT16, SUNI_REGO_RSOP_BIP8, \ 965 SUNI_REGN_RSOP_BIP8, NULL }, \ 966 { /* 14 */ \ 967 UTP_REGT_BITS, SUNI_REGO_TSOPCTRL, \ 968 SUNI_REGN_TSOPCTRL, SUNI_REGX_TSOPCTRL }, \ 969 { /* 15 */ \ 970 UTP_REGT_BITS, SUNI_REGO_TSOPDIAG, \ 971 SUNI_REGN_TSOPDIAG, SUNI_REGX_TSOPDIAG }, \ 972 /* 16-17 unused */ \ 973 { /* 18 */ \ 974 UTP_REGT_BITS, SUNI_REGO_RLOPCTRL, \ 975 SUNI_REGN_RLOPCTRL, SUNI_REGX_RLOPCTRL }, \ 976 { /* 19 */ \ 977 UTP_REGT_BITS, SUNI_REGO_RLOPINTR, \ 978 SUNI_REGN_RLOPINTR, SUNI_REGX_RLOPINTR }, \ 979 { /* 1A, 1B, 1C */ \ 980 UTP_REGT_INT20, SUNI_REGO_RLOPBIP8_24, \ 981 SUNI_REGN_RLOPBIP8_24, NULL }, \ 982 { /* 1D, 1E, 1F */ \ 983 UTP_REGT_INT20, SUNI_REGO_RLOPFEBE, \ 984 SUNI_REGN_RLOPFEBE, NULL }, \ 985 { /* 20 */ \ 986 UTP_REGT_BITS, SUNI_REGO_TLOPCTRL, \ 987 SUNI_REGN_TLOPCTRL, SUNI_REGX_TLOPCTRL }, \ 988 { /* 21 */ \ 989 UTP_REGT_BITS, SUNI_REGO_TLOPDIAG, \ 990 SUNI_REGN_TLOPDIAG, SUNI_REGX_TLOPDIAG }, \ 991 /* 22-2F unused */ \ 992 { /* 30 */ \ 993 UTP_REGT_BITS, SUNI_REGO_RPOPCTRL, \ 994 SUNI_REGN_RPOPCTRL, SUNI_REGX_RPOPCTRL }, \ 995 { /* 31 */ \ 996 UTP_REGT_BITS, SUNI_REGO_RPOPISTAT, \ 997 SUNI_REGN_RPOPISTAT, SUNI_REGX_RPOPISTAT }, \ 998 /* 32 unused */ \ 999 { /* 33 */ \ 1000 UTP_REGT_BITS, SUNI_REGO_RPOPIEN, \ 1001 SUNI_REGN_RPOPIEN, SUNI_REGX_RPOPIEN }, \ 1002 /* 34-36 unused */ \ 1003 { /* 37 */ \ 1004 UTP_REGT_INT8, SUNI_REGO_RPOPPSL, \ 1005 SUNI_REGN_RPOPPSL, NULL }, \ 1006 { /* 38, 39 */ \ 1007 UTP_REGT_INT16, SUNI_REGO_RPOPBIP8, \ 1008 SUNI_REGN_RPOPBIP8, NULL }, \ 1009 { /* 3A, 3B */ \ 1010 UTP_REGT_INT16, SUNI_REGO_RPOPFEBE, \ 1011 SUNI_REGN_RPOPFEBE, NULL }, \ 1012 /* 3C unused */ \ 1013 { /* 3D */ \ 1014 UTP_REGT_BITS, SUNI_REGO_RPOPBIP8CFG, \ 1015 SUNI_REGN_RPOPBIP8CFG, SUNI_REGX_RPOPBIP8CFG }, \ 1016 /* 3E-3F unused */ \ 1017 { /* 40 */ \ 1018 UTP_REGT_BITS, SUNI_REGO_TPOPCTRL, \ 1019 SUNI_REGN_TPOPCTRL, SUNI_REGX_TPOPCTRL }, \ 1020 { /* 41 */ \ 1021 UTP_REGT_BITS, SUNI_REGO_TPOPPTRC, \ 1022 SUNI_REGN_TPOPPTRC, SUNI_REGX_TPOPPTRC }, \ 1023 /* 42-44 unused */ \ 1024 { /* 45, 46 */ \ 1025 UTP_REGT_INT10BITS, SUNI_REGO_TPOPAPTR, \ 1026 SUNI_REGN_TPOPAPTR, SUNI_REGX_TPOPAPTR }, \ 1027 /* 47 unused */ \ 1028 { /* 48 */ \ 1029 UTP_REGT_INT8, SUNI_REGO_TPOPPSL, \ 1030 SUNI_REGN_TPOPPSL, NULL }, \ 1031 { /* 49 */ \ 1032 UTP_REGT_BITS, SUNI_REGO_TPOPSTATUS, \ 1033 SUNI_REGN_TPOPSTATUS, SUNI_REGX_TPOPSTATUS }, \ 1034 /* 4A-4F unused */ \ 1035 { /* 50 */ \ 1036 UTP_REGT_BITS, SUNI_REGO_RACPCTRL, \ 1037 SUNI_REGN_RACPCTRL, SUNI_REGX_RACPCTRL }, \ 1038 { /* 51 */ \ 1039 UTP_REGT_BITS, SUNI_REGO_RACPINTR, \ 1040 SUNI_REGN_RACPINTR, SUNI_REGX_RACPINTR }, \ 1041 { /* 52 */ \ 1042 UTP_REGT_BITS, SUNI_REGO_RACPPATTERN, \ 1043 SUNI_REGN_RACPPATTERN, SUNI_REGX_RACPPATTERN }, \ 1044 { /* 53 */ \ 1045 UTP_REGT_BITS, SUNI_REGO_RACPMASK, \ 1046 SUNI_REGN_RACPMASK, SUNI_REGX_RACPMASK }, \ 1047 { /* 54 */ \ 1048 UTP_REGT_INT8, SUNI_REGO_RACPCHCS, \ 1049 SUNI_REGN_RACPCHCS, NULL }, \ 1050 { /* 55 */ \ 1051 UTP_REGT_INT8, SUNI_REGO_RACPUHCS, \ 1052 SUNI_REGN_RACPUHCS, NULL }, \ 1053 { /* 56, 57, 58 */ \ 1054 UTP_REGT_INT19, SUNI_REGO_RACPCNT, \ 1055 SUNI_REGN_RACPCNT, NULL }, \ 1056 { /* 59 */ \ 1057 UTP_REGT_BITS, SUNI_REGO_RACPCFG, \ 1058 SUNI_REGN_RACPCFG, SUNI_REGX_RACPCFG }, \ 1059 /* 5A-5F unused */ \ 1060 { /* 60 */ \ 1061 UTP_REGT_BITS, SUNI_REGO_TACPCTRL, \ 1062 SUNI_REGN_TACPCTRL, SUNI_REGX_TACPCTRL_LITE }, \ 1063 { /* 61 */ \ 1064 UTP_REGT_BITS, SUNI_REGO_TACPIDLEH, \ 1065 SUNI_REGN_TACPIDLEH, SUNI_REGX_TACPIDLEH }, \ 1066 { /* 62 */ \ 1067 UTP_REGT_INT8, SUNI_REGO_TACPIDLEP, \ 1068 SUNI_REGN_TACPIDLEP, NULL }, \ 1069 { /* 63 */ \ 1070 UTP_REGT_BITS, SUNI_REGO_TACPFIFOC, \ 1071 SUNI_REGN_TACPFIFOC, SUNI_REGX_TACPFIFOC }, \ 1072 { /* 64, 65, 66 */ \ 1073 UTP_REGT_INT19, SUNI_REGO_TACPCNT, \ 1074 SUNI_REGN_TACPCNT, NULL }, \ 1075 { /* 67 */ \ 1076 UTP_REGT_BITS, SUNI_REGO_TACPGFC, \ 1077 SUNI_REGN_TACPGFC, SUNI_REGX_TACPGFC }, \ 1078 /* 68-7f unused */ \ 1079 { /* 80 */ \ 1080 UTP_REGT_BITS, SUNI_REGO_MTEST, \ 1081 SUNI_REGN_MTEST, SUNI_REGX_MTEST_LITE } 1082 1083 #define SUNI_PRINT_ULTRA \ 1084 { /* 00 */ \ 1085 UTP_REGT_BITS, SUNI_REGO_MRESET, \ 1086 SUNI_REGN_MRESET, SUNI_REGX_MRESET_ULTRA }, \ 1087 { /* 01 */ \ 1088 UTP_REGT_BITS, SUNI_REGO_MCONFIG, \ 1089 SUNI_REGN_MCONFIG, SUNI_REGX_MCONFIG_ULTRA }, \ 1090 { /* 02 */ \ 1091 UTP_REGT_BITS, SUNI_REGO_MISTATUS, \ 1092 SUNI_REGN_MISTATUS, SUNI_REGX_MISTATUS_ULTRA }, \ 1093 { /* 03 */ \ 1094 UTP_REGT_BITS, SUNI_REGO_MMCTRL, \ 1095 SUNI_REGN_MMCTRL, SUNI_REGX_MMCTRL }, \ 1096 { /* 04 */ \ 1097 UTP_REGT_BITS, SUNI_REGO_MCLKM, \ 1098 SUNI_REGN_MCLKM, SUNI_REGX_MCLKM_ULTRA }, \ 1099 { /* 05 */ \ 1100 UTP_REGT_BITS, SUNI_REGO_MCTRL, \ 1101 SUNI_REGN_MCTRL, SUNI_REGX_MCTRL_ULTRA }, \ 1102 { /* 06 */ \ 1103 UTP_REGT_BITS, SUNI_REGO_CLKSYN, \ 1104 SUNI_REGN_CLKSYN, SUNI_REGX_CLKSYN_ULTRA }, \ 1105 /* 07 unused */ \ 1106 { /* 08 */ \ 1107 UTP_REGT_BITS, SUNI_REGO_CLKREC_ULTRA, \ 1108 SUNI_REGN_CLKREC, SUNI_REGX_CLKREC_ULTRA }, \ 1109 { /* 09 */ \ 1110 UTP_REGT_BITS, SUNI_REGO_CLKRECCFG, \ 1111 SUNI_REGN_CLKRECCFG, SUNI_REGX_CLKRECCFG }, \ 1112 { /* 0A */ \ 1113 UTP_REGT_BITS, SUNI_REGO_LTXCFG1, \ 1114 SUNI_REGN_LTXCFG1, SUNI_REGX_LTXCFG1 }, \ 1115 { /* 0B */ \ 1116 UTP_REGT_BITS, SUNI_REGO_LTXCFG2, \ 1117 SUNI_REGN_LTXCFG2, SUNI_REGX_LTXCFG2 }, \ 1118 { /* 0C */ \ 1119 UTP_REGT_BITS, SUNI_REGO_LRXCFG, \ 1120 SUNI_REGN_LRXCFG, SUNI_REGX_LRXCFG }, \ 1121 /* 0D-0F unused */ \ 1122 { /* 10 */ \ 1123 UTP_REGT_BITS, SUNI_REGO_RSOPCIE, \ 1124 SUNI_REGN_RSOPCIE, SUNI_REGX_RSOPCIE }, \ 1125 { /* 11 */ \ 1126 UTP_REGT_BITS, SUNI_REGO_RSOPSIS, \ 1127 SUNI_REGN_RSOPSIS, SUNI_REGX_RSOPSIS }, \ 1128 { /* 12, 13 */ \ 1129 UTP_REGT_INT16, SUNI_REGO_RSOP_BIP8, \ 1130 SUNI_REGN_RSOP_BIP8, NULL }, \ 1131 { /* 14 */ \ 1132 UTP_REGT_BITS, SUNI_REGO_TSOPCTRL, \ 1133 SUNI_REGN_TSOPCTRL, SUNI_REGX_TSOPCTRL }, \ 1134 { /* 15 */ \ 1135 UTP_REGT_BITS, SUNI_REGO_TSOPDIAG, \ 1136 SUNI_REGN_TSOPDIAG, SUNI_REGX_TSOPDIAG }, \ 1137 /* 16-17 unused */ \ 1138 { /* 18 */ \ 1139 UTP_REGT_BITS, SUNI_REGO_RLOPCTRL, \ 1140 SUNI_REGN_RLOPCTRL, SUNI_REGX_RLOPCTRL }, \ 1141 { /* 19 */ \ 1142 UTP_REGT_BITS, SUNI_REGO_RLOPINTR, \ 1143 SUNI_REGN_RLOPINTR, SUNI_REGX_RLOPINTR }, \ 1144 { /* 1A, 1B, 1C */ \ 1145 UTP_REGT_INT20, SUNI_REGO_RLOPBIP8_24, \ 1146 SUNI_REGN_RLOPBIP8_24, NULL }, \ 1147 { /* 1D, 1E, 1F */ \ 1148 UTP_REGT_INT20, SUNI_REGO_RLOPFEBE, \ 1149 SUNI_REGN_RLOPFEBE, NULL }, \ 1150 { /* 20 */ \ 1151 UTP_REGT_BITS, SUNI_REGO_TLOPCTRL, \ 1152 SUNI_REGN_TLOPCTRL, SUNI_REGX_TLOPCTRL }, \ 1153 { /* 21 */ \ 1154 UTP_REGT_BITS, SUNI_REGO_TLOPDIAG, \ 1155 SUNI_REGN_TLOPDIAG, SUNI_REGX_TLOPDIAG }, \ 1156 /* 22-2F unused */ \ 1157 { /* 30 */ \ 1158 UTP_REGT_BITS, SUNI_REGO_RPOPCTRL, \ 1159 SUNI_REGN_RPOPCTRL, SUNI_REGX_RPOPCTRL }, \ 1160 { /* 31 */ \ 1161 UTP_REGT_BITS, SUNI_REGO_RPOPISTAT, \ 1162 SUNI_REGN_RPOPISTAT, SUNI_REGX_RPOPISTAT }, \ 1163 /* 32 unused */ \ 1164 { /* 33 */ \ 1165 UTP_REGT_BITS, SUNI_REGO_RPOPIEN, \ 1166 SUNI_REGN_RPOPIEN, SUNI_REGX_RPOPIEN }, \ 1167 /* 34-36 unused */ \ 1168 { /* 37 */ \ 1169 UTP_REGT_INT8, SUNI_REGO_RPOPPSL, \ 1170 SUNI_REGN_RPOPPSL, NULL }, \ 1171 { /* 38, 39 */ \ 1172 UTP_REGT_INT16, SUNI_REGO_RPOPBIP8, \ 1173 SUNI_REGN_RPOPBIP8, NULL }, \ 1174 { /* 3A, 3B */ \ 1175 UTP_REGT_INT16, SUNI_REGO_RPOPFEBE, \ 1176 SUNI_REGN_RPOPFEBE, NULL }, \ 1177 /* 3C unused */ \ 1178 { /* 3D */ \ 1179 UTP_REGT_BITS, SUNI_REGO_RPOPBIP8CFG, \ 1180 SUNI_REGN_RPOPBIP8CFG, SUNI_REGX_RPOPBIP8CFG }, \ 1181 /* 3E-3F unused */ \ 1182 { /* 40 */ \ 1183 UTP_REGT_BITS, SUNI_REGO_TPOPCTRL, \ 1184 SUNI_REGN_TPOPCTRL, SUNI_REGX_TPOPCTRL }, \ 1185 { /* 41 */ \ 1186 UTP_REGT_BITS, SUNI_REGO_TPOPPTRC, \ 1187 SUNI_REGN_TPOPPTRC, SUNI_REGX_TPOPPTRC }, \ 1188 /* 42-44 unused */ \ 1189 { /* 45, 46 */ \ 1190 UTP_REGT_INT10BITS, SUNI_REGO_TPOPAPTR, \ 1191 SUNI_REGN_TPOPAPTR, SUNI_REGX_TPOPAPTR }, \ 1192 /* 47 unused */ \ 1193 { /* 48 */ \ 1194 UTP_REGT_INT8, SUNI_REGO_TPOPPSL, \ 1195 SUNI_REGN_TPOPPSL, NULL }, \ 1196 { /* 49 */ \ 1197 UTP_REGT_BITS, SUNI_REGO_TPOPSTATUS, \ 1198 SUNI_REGN_TPOPSTATUS, SUNI_REGX_TPOPSTATUS }, \ 1199 /* 4A-4F unused */ \ 1200 { /* 50 */ \ 1201 UTP_REGT_BITS, SUNI_REGO_RACPCTRL, \ 1202 SUNI_REGN_RACPCTRL, SUNI_REGX_RACPCTRL }, \ 1203 { /* 51 */ \ 1204 UTP_REGT_BITS, SUNI_REGO_RACPINTR, \ 1205 SUNI_REGN_RACPINTR, SUNI_REGX_RACPINTR }, \ 1206 { /* 52 */ \ 1207 UTP_REGT_BITS, SUNI_REGO_RACPPATTERN, \ 1208 SUNI_REGN_RACPPATTERN, SUNI_REGX_RACPPATTERN }, \ 1209 { /* 53 */ \ 1210 UTP_REGT_BITS, SUNI_REGO_RACPMASK, \ 1211 SUNI_REGN_RACPMASK, SUNI_REGX_RACPMASK }, \ 1212 { /* 54 */ \ 1213 UTP_REGT_INT8, SUNI_REGO_RACPCHCS, \ 1214 SUNI_REGN_RACPCHCS, NULL }, \ 1215 { /* 55 */ \ 1216 UTP_REGT_INT8, SUNI_REGO_RACPUHCS, \ 1217 SUNI_REGN_RACPUHCS, NULL }, \ 1218 { /* 56, 57, 58 */ \ 1219 UTP_REGT_INT19, SUNI_REGO_RACPCNT, \ 1220 SUNI_REGN_RACPCNT, NULL }, \ 1221 { /* 59 */ \ 1222 UTP_REGT_BITS, SUNI_REGO_RACPCFG, \ 1223 SUNI_REGN_RACPCFG, SUNI_REGX_RACPCFG }, \ 1224 /* 5A-5F unused */ \ 1225 { /* 60 */ \ 1226 UTP_REGT_BITS, SUNI_REGO_TACPCTRL, \ 1227 SUNI_REGN_TACPCTRL, SUNI_REGX_TACPCTRL_ULTRA }, \ 1228 { /* 61 */ \ 1229 UTP_REGT_BITS, SUNI_REGO_TACPIDLEH, \ 1230 SUNI_REGN_TACPIDLEH, SUNI_REGX_TACPIDLEH }, \ 1231 { /* 62 */ \ 1232 UTP_REGT_INT8, SUNI_REGO_TACPIDLEP, \ 1233 SUNI_REGN_TACPIDLEP, NULL }, \ 1234 { /* 63 */ \ 1235 UTP_REGT_BITS, SUNI_REGO_TACPFIFOC, \ 1236 SUNI_REGN_TACPFIFOC, SUNI_REGX_TACPFIFOC }, \ 1237 { /* 64, 65, 66 */ \ 1238 UTP_REGT_INT19, SUNI_REGO_TACPCNT, \ 1239 SUNI_REGN_TACPCNT, NULL }, \ 1240 { /* 67 */ \ 1241 UTP_REGT_BITS, SUNI_REGO_TACPGFC, \ 1242 SUNI_REGN_TACPGFC, SUNI_REGX_TACPGFC }, \ 1243 { /* 68 */ \ 1244 UTP_REGT_BITS, SUNI_REGO_POPCCTRL, \ 1245 SUNI_REGN_POPCCTRL, SUNI_REGX_POPCCTRL }, \ 1246 { /* 69 */ \ 1247 UTP_REGT_INT8, SUNI_REGO_POPCSTROBE0, \ 1248 SUNI_REGN_POPCSTROBE0, NULL }, \ 1249 { /* 6A */ \ 1250 UTP_REGT_INT8, SUNI_REGO_POPCSTROBE1, \ 1251 SUNI_REGN_POPCSTROBE1, NULL }, \ 1252 /* 6B-7f unused */ \ 1253 { /* 80 */ \ 1254 UTP_REGT_BITS, SUNI_REGO_MTEST, \ 1255 SUNI_REGN_MTEST, SUNI_REGX_MTEST_ULTRA } 1256 1257 #define SUNI_PRINT_622 \ 1258 { /* 00 */ \ 1259 UTP_REGT_BITS, SUNI_REGO_MRESET, \ 1260 SUNI_REGN_MRESET, SUNI_REGX_MRESET_622 }, \ 1261 { /* 01 */ \ 1262 UTP_REGT_BITS, SUNI_REGO_MCONFIG, \ 1263 SUNI_REGN_MCONFIG, SUNI_REGX_MCONFIG_622 }, \ 1264 { /* 02 */ \ 1265 UTP_REGT_BITS, SUNI_REGO_MISTATUS, \ 1266 SUNI_REGN_MISTATUS, SUNI_REGX_MISTATUS_622 }, \ 1267 { /* 03 */ \ 1268 UTP_REGT_BITS, SUNI_REGO_PISO, \ 1269 SUNI_REGN_PISO, SUNI_REGX_PISO }, \ 1270 { /* 04 */ \ 1271 UTP_REGT_BITS, SUNI_REGO_MCTRLM, \ 1272 SUNI_REGN_MCTRLM, SUNI_REGX_MCTRLM }, \ 1273 { /* 05 */ \ 1274 UTP_REGT_BITS, SUNI_REGO_MALARM, \ 1275 SUNI_REGN_MALARM, SUNI_REGX_MALARM }, \ 1276 { /* 06 */ \ 1277 UTP_REGT_BITS, SUNI_REGO_POUT, \ 1278 SUNI_REGN_POUT, SUNI_REGX_POUT }, \ 1279 { /* 07 */ \ 1280 UTP_REGT_INT8, SUNI_REGO_PIN, \ 1281 SUNI_REGN_PIN, NULL }, \ 1282 { /* 08 */ \ 1283 UTP_REGT_BITS, SUNI_REGO_PINV, \ 1284 SUNI_REGN_PINV, SUNI_REGX_PINV }, \ 1285 { /* 09 */ \ 1286 UTP_REGT_INT8, SUNI_REGO_PINE, \ 1287 SUNI_REGN_PINE, NULL }, \ 1288 { /* 0A */ \ 1289 UTP_REGT_INT8, SUNI_REGO_XC1, \ 1290 SUNI_REGN_XC1, NULL }, \ 1291 { /* 0B */ \ 1292 UTP_REGT_BITS, SUNI_REGO_APSCS, \ 1293 SUNI_REGN_APSCS, SUNI_REGX_APSCS }, \ 1294 { /* 0C */ \ 1295 UTP_REGT_INT8, SUNI_REGO_RK1, \ 1296 SUNI_REGN_RK1, NULL }, \ 1297 { /* 0D */ \ 1298 UTP_REGT_INT8, SUNI_REGO_RK2, \ 1299 SUNI_REGN_RK2, NULL }, \ 1300 { /* 0E */ \ 1301 UTP_REGT_INT8, SUNI_REGO_RZ1, \ 1302 SUNI_REGN_RZ1, NULL }, \ 1303 { /* 0F */ \ 1304 UTP_REGT_INT8, SUNI_REGO_XZ1, \ 1305 SUNI_REGN_XZ1, NULL }, \ 1306 { /* 10 */ \ 1307 UTP_REGT_BITS, SUNI_REGO_RSOPCIE, \ 1308 SUNI_REGN_RSOPCIE, SUNI_REGX_RSOPCIE_622 }, \ 1309 { /* 11 */ \ 1310 UTP_REGT_BITS, SUNI_REGO_RSOPSIS, \ 1311 SUNI_REGN_RSOPSIS, SUNI_REGX_RSOPSIS }, \ 1312 { /* 12, 13 */ \ 1313 UTP_REGT_INT16, SUNI_REGO_RSOP_BIP8, \ 1314 SUNI_REGN_RSOP_BIP8, NULL }, \ 1315 { /* 14 */ \ 1316 UTP_REGT_BITS, SUNI_REGO_TSOPCTRL, \ 1317 SUNI_REGN_TSOPCTRL, SUNI_REGX_TSOPCTRL }, \ 1318 { /* 15 */ \ 1319 UTP_REGT_BITS, SUNI_REGO_TSOPDIAG, \ 1320 SUNI_REGN_TSOPDIAG, SUNI_REGX_TSOPDIAG }, \ 1321 /* 16-17 unused */ \ 1322 { /* 18 */ \ 1323 UTP_REGT_BITS, SUNI_REGO_RLOPCTRL, \ 1324 SUNI_REGN_RLOPCTRL, SUNI_REGX_RLOPCTRL_622 }, \ 1325 { /* 19 */ \ 1326 UTP_REGT_BITS, SUNI_REGO_RLOPINTR, \ 1327 SUNI_REGN_RLOPINTR, SUNI_REGX_RLOPINTR }, \ 1328 { /* 1A, 1B, 1C */ \ 1329 UTP_REGT_INT20, SUNI_REGO_RLOPBIP8_24_96, \ 1330 SUNI_REGN_RLOPBIP8_24_96, NULL }, \ 1331 { /* 1D, 1E, 1F */ \ 1332 UTP_REGT_INT20, SUNI_REGO_RLOPFEBE, \ 1333 SUNI_REGN_RLOPFEBE, NULL }, \ 1334 { /* 20 */ \ 1335 UTP_REGT_BITS, SUNI_REGO_TLOPCTRL, \ 1336 SUNI_REGN_TLOPCTRL, SUNI_REGX_TLOPCTRL_622 }, \ 1337 { /* 21 */ \ 1338 UTP_REGT_BITS, SUNI_REGO_TLOPDIAG, \ 1339 SUNI_REGN_TLOPDIAG, SUNI_REGX_TLOPDIAG }, \ 1340 { /* 22 */ \ 1341 UTP_REGT_INT8, SUNI_REGO_TLOP_XK1, \ 1342 SUNI_REGN_TLOP_XK1, NULL }, \ 1343 { /* 23 */ \ 1344 UTP_REGT_INT8, SUNI_REGO_TLOP_XK2, \ 1345 SUNI_REGN_TLOP_XK2, NULL }, \ 1346 /* 24-27 unused */ \ 1347 { /* 28 */ \ 1348 UTP_REGT_BITS, SUNI_REGO_SSTBCTRL, \ 1349 SUNI_REGN_SSTBCTRL, SUNI_REGX_SSTBCTRL }, \ 1350 { /* 29 */ \ 1351 UTP_REGT_BITS, SUNI_REGO_SSTBSTIS, \ 1352 SUNI_REGN_SSTBSTIS, SUNI_REGX_SSTBSTIS }, \ 1353 { /* 2A */ \ 1354 UTP_REGT_BITS, SUNI_REGO_SSTBIAR, \ 1355 SUNI_REGN_SSTBIAR, SUNI_REGX_SSTBIAR }, \ 1356 { /* 2B */ \ 1357 UTP_REGT_INT8, SUNI_REGO_SSTBIDR, \ 1358 SUNI_REGN_SSTBIDR, NULL }, \ 1359 /* 2C unused (see chip errata) */ \ 1360 { /* 2D */ \ 1361 UTP_REGT_BITS, SUNI_REGO_SSTBCSMS, \ 1362 SUNI_REGN_SSTBCSMS, SUNI_REGX_SSTBCSMS }, \ 1363 /* 2E-2F unused */ \ 1364 { /* 30 */ \ 1365 UTP_REGT_BITS, SUNI_REGO_RPOPCTRL, \ 1366 SUNI_REGN_RPOPCTRL, SUNI_REGX_RPOPCTRL_622 }, \ 1367 { /* 31 */ \ 1368 UTP_REGT_BITS, SUNI_REGO_RPOPISTAT, \ 1369 SUNI_REGN_RPOPISTAT, SUNI_REGX_RPOPISTAT }, \ 1370 { /* 32 */ \ 1371 UTP_REGT_BITS, SUNI_REGO_RPOPPIS, \ 1372 SUNI_REGN_RPOPPIS, SUNI_REGX_RPOPPIS }, \ 1373 { /* 33 */ \ 1374 UTP_REGT_BITS, SUNI_REGO_RPOPIEN, \ 1375 SUNI_REGN_RPOPIEN, SUNI_REGX_RPOPIEN }, \ 1376 { /* 34 */ \ 1377 UTP_REGT_BITS, SUNI_REGO_RPOPPIE, \ 1378 SUNI_REGN_RPOPPIE, SUNI_REGX_RPOPPIE }, \ 1379 { /* 35, 36 */ \ 1380 UTP_REGT_INT10BITS, SUNI_REGO_RPOPPTR, \ 1381 SUNI_REGN_RPOPPTR, SUNI_REGX_RPOPPTR }, \ 1382 { /* 37 */ \ 1383 UTP_REGT_INT8, SUNI_REGO_RPOPPSL, \ 1384 SUNI_REGN_RPOPPSL, NULL }, \ 1385 { /* 38, 39 */ \ 1386 UTP_REGT_INT16, SUNI_REGO_RPOPBIP8, \ 1387 SUNI_REGN_RPOPBIP8, NULL }, \ 1388 { /* 3A, 3B */ \ 1389 UTP_REGT_INT16, SUNI_REGO_RPOPFEBE, \ 1390 SUNI_REGN_RPOPFEBE, NULL }, \ 1391 { /* 3C */ \ 1392 UTP_REGT_BITS, SUNI_REGO_RPOPRDI, \ 1393 SUNI_REGN_RPOPRDI, SUNI_REGX_RPOPRDI }, \ 1394 { /* 3D */ \ 1395 UTP_REGT_BITS, SUNI_REGO_RPOPRING, \ 1396 SUNI_REGN_RPOPRING, SUNI_REGX_RPOPRING }, \ 1397 /* 3E-3F unused */ \ 1398 { /* 40 */ \ 1399 UTP_REGT_BITS, SUNI_REGO_TPOPCTRL, \ 1400 SUNI_REGN_TPOPCTRL, SUNI_REGX_TPOPCTRL_622 }, \ 1401 { /* 41 */ \ 1402 UTP_REGT_BITS, SUNI_REGO_TPOPPTRC, \ 1403 SUNI_REGN_TPOPPTRC, SUNI_REGX_TPOPPTRC }, \ 1404 /* 42 unused */ \ 1405 { /* 43, 44 */ \ 1406 UTP_REGT_INT10BITS, SUNI_REGO_TPOPCP, \ 1407 SUNI_REGN_TPOPCP, SUNI_REGX_TPOPCP }, \ 1408 { /* 45, 46 */ \ 1409 UTP_REGT_INT10BITS, SUNI_REGO_TPOPAPTR, \ 1410 SUNI_REGN_TPOPAPTR, SUNI_REGX_TPOPAPTR }, \ 1411 { /* 47 */ \ 1412 UTP_REGT_INT8, SUNI_REGO_TPOPPT, \ 1413 SUNI_REGN_TPOPPT, NULL }, \ 1414 { /* 48 */ \ 1415 UTP_REGT_INT8, SUNI_REGO_TPOPPSL, \ 1416 SUNI_REGN_TPOPPSL, NULL }, \ 1417 { /* 49 */ \ 1418 UTP_REGT_BITS, SUNI_REGO_TPOPSTATUS, \ 1419 SUNI_REGN_TPOPSTATUS, SUNI_REGX_TPOPSTATUS }, \ 1420 { /* 4A */ \ 1421 UTP_REGT_INT8, SUNI_REGO_TPOPPUC, \ 1422 SUNI_REGN_TPOPPUC, NULL }, \ 1423 { /* 4B */ \ 1424 UTP_REGT_INT8, SUNI_REGO_TPOPPG1, \ 1425 SUNI_REGN_TPOPPG1, NULL }, \ 1426 { /* 4C */ \ 1427 UTP_REGT_INT8, SUNI_REGO_TPOPPG2, \ 1428 SUNI_REGN_TPOPPG2, NULL }, \ 1429 { /* 4D */ \ 1430 UTP_REGT_INT8, SUNI_REGO_TPOPPG3, \ 1431 SUNI_REGN_TPOPPG3, NULL }, \ 1432 /* 4E-4F unused */ \ 1433 { /* 50 */ \ 1434 UTP_REGT_BITS, SUNI_REGO_RACPCTRL, \ 1435 SUNI_REGN_RACPCTRL, SUNI_REGX_RACPCTRL_622 }, \ 1436 { /* 51 */ \ 1437 UTP_REGT_BITS, SUNI_REGO_RACPIS, \ 1438 SUNI_REGN_RACPIS, SUNI_REGX_RACPIS }, \ 1439 { /* 52 */ \ 1440 UTP_REGT_BITS, SUNI_REGO_RACPIEC, \ 1441 SUNI_REGN_RACPIEC, SUNI_REGX_RACPIEC }, \ 1442 { /* 53 */ \ 1443 UTP_REGT_BITS, SUNI_REGO_RACPPATTERN_622, \ 1444 SUNI_REGN_RACPPATTERN, SUNI_REGX_RACPPATTERN }, \ 1445 { /* 54 */ \ 1446 UTP_REGT_BITS, SUNI_REGO_RACPMASK_622, \ 1447 SUNI_REGN_RACPMASK, SUNI_REGX_RACPMASK }, \ 1448 { /* 55, 56 */ \ 1449 UTP_REGT_INT12, SUNI_REGO_RACPCHCS_622, \ 1450 SUNI_REGN_RACPCHCS, NULL }, \ 1451 { /* 57, 58 */ \ 1452 UTP_REGT_INT12, SUNI_REGO_RACPUHCS_622, \ 1453 SUNI_REGN_RACPUHCS, NULL }, \ 1454 { /* 59, 5A, 5B */ \ 1455 UTP_REGT_INT21, SUNI_REGO_RACPCNT_622, \ 1456 SUNI_REGN_RACPCNT, NULL }, \ 1457 { /* 5C */ \ 1458 UTP_REGT_BITS, SUNI_REGO_RACPGFC, \ 1459 SUNI_REGN_RACPGFC, SUNI_REGX_RACPGFC }, \ 1460 /* 5D-5F unused */ \ 1461 { /* 60 */ \ 1462 UTP_REGT_BITS, SUNI_REGO_TACPCTRL, \ 1463 SUNI_REGN_TACPCTRL, SUNI_REGX_TACPCTRL_622 }, \ 1464 { /* 61 */ \ 1465 UTP_REGT_BITS, SUNI_REGO_TACPIDLEH, \ 1466 SUNI_REGN_TACPIDLEH, SUNI_REGX_TACPIDLEH }, \ 1467 { /* 62 */ \ 1468 UTP_REGT_INT8, SUNI_REGO_TACPIDLEP, \ 1469 SUNI_REGN_TACPIDLEP, NULL }, \ 1470 { /* 63 */ \ 1471 UTP_REGT_BITS, SUNI_REGO_TACPFIFOC, \ 1472 SUNI_REGN_TACPFIFOC, SUNI_REGX_TACPFIFOC_622 }, \ 1473 { /* 64, 65, 66 */ \ 1474 UTP_REGT_INT21, SUNI_REGO_TACPCNT, \ 1475 SUNI_REGN_TACPCNT, NULL }, \ 1476 { /* 67 */ \ 1477 UTP_REGT_BITS, SUNI_REGO_TACPGFC, \ 1478 SUNI_REGN_TACPGFC, SUNI_REGX_TACPGFC }, \ 1479 { /* 68 */ \ 1480 UTP_REGT_BITS, SUNI_REGO_SPTBCTRL, \ 1481 SUNI_REGN_SPTBCTRL, SUNI_REGX_SPTBCTRL }, \ 1482 { /* 69 */ \ 1483 UTP_REGT_BITS, SUNI_REGO_SPTBPTIS, \ 1484 SUNI_REGN_SPTBPTIS, SUNI_REGX_SPTBPTIS }, \ 1485 { /* 6A */ \ 1486 UTP_REGT_BITS, SUNI_REGO_SPTBIAR, \ 1487 SUNI_REGN_SPTBIAR, SUNI_REGX_SPTBIAR }, \ 1488 { /* 6B */ \ 1489 UTP_REGT_INT8, SUNI_REGO_SPTBIDR, \ 1490 SUNI_REGN_SPTBIDR, NULL }, \ 1491 { /* 6C */ \ 1492 UTP_REGT_INT8, SUNI_REGO_SPTBEPSL, \ 1493 SUNI_REGN_SPTBEPSL, NULL }, \ 1494 { /* 6D */ \ 1495 UTP_REGT_BITS, SUNI_REGO_SPTBPSLS, \ 1496 SUNI_REGN_SPTBPSLS, SUNI_REGX_SPTBPSLS }, \ 1497 /* 6E-6F unused */ \ 1498 { /* 70 */ \ 1499 UTP_REGT_BITS, SUNI_REGO_BERMCTRL, \ 1500 SUNI_REGN_BERMCTRL, SUNI_REGX_BERMCTRL }, \ 1501 { /* 71 */ \ 1502 UTP_REGT_BITS, SUNI_REGO_BERMINT, \ 1503 SUNI_REGN_BERMINT, SUNI_REGX_BERMINT }, \ 1504 { /* 72, 73 */ \ 1505 UTP_REGT_INT16, SUNI_REGO_BERMLAP, \ 1506 SUNI_REGN_BERMLAP, NULL }, \ 1507 { /* 74, 75 */ \ 1508 UTP_REGT_INT16, SUNI_REGO_BERMLT, \ 1509 SUNI_REGN_BERMLT, NULL }, \ 1510 /* 76-7f unused */ \ 1511 { /* 80 */ \ 1512 UTP_REGT_BITS, SUNI_REGO_MTEST, \ 1513 SUNI_REGN_MTEST, SUNI_REGX_MTEST_622 } 1514 1515 #endif /* _DEV_UTOPIA_SUNI_H */
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