The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/vme/sireg.h

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    1 /*      $NetBSD: sireg.h,v 1.2 2003/05/03 18:11:42 wiz Exp $    */
    2 
    3 /*-
    4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Paul Kranenburg.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *        This product includes software developed by the NetBSD
   21  *        Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 /*
   40  * Register map for the VME SCSI-3 adpater (si)
   41  * The first part of this register map is an NCR5380
   42  * SCSI Bus Interface Controller (SBIC).  The rest is a
   43  * DMA controller and custom logic.
   44  */
   45 
   46 
   47 #if __for_reference_only__
   48 /*
   49  * Am5380 Register map (no padding). See dev/ic/ncr5380reg.h
   50  */
   51 struct ncr5380regs {
   52         u_char r[8];
   53 };
   54 
   55 struct si_regs {
   56         struct ncr5380regs sci;
   57 
   58         /* DMA controller registers */
   59         u_short dma_addrh;      /* DMA address (VME only) */
   60         u_short dma_addrl;      /* (high word, low word)  */
   61         u_short dma_counth;     /* DMA count   (VME only) */
   62         u_short dma_countl;     /* (high word, low word)  */
   63 
   64         u_int   pad0;           /* no-existent register */
   65 
   66         u_short fifo_data;      /* fifo data register */
   67         u_short fifo_count;     /* fifo count register */
   68         u_short si_csr;         /* si control/status */
   69         u_short bprh;           /* VME byte pack high */
   70         u_short bprl;           /* VME byte pack low */
   71         u_short iv_am;          /* bits 0-7: intr vector */
   72                                 /* bits 8-13: addr modifier (VME only) */
   73                                 /* bits 14-15: unused */
   74         u_short fifo_cnt_hi;    /* high part of fifo_count (VME only) */
   75 
   76         /* Whole thing repeats after 32 bytes. */
   77         u_short _space[3];
   78 };
   79 #endif
   80 
   81 /*
   82  * Size of NCR5380 registers located at the bottom of the register bank
   83  */
   84 #define NCR5380REGS_SZ  8
   85 
   86 /*
   87  * Register definition for the `si' VME controller
   88  */
   89 #define SIREG_DMA_ADDRH (NCR5380REGS_SZ + 0)    /* DMA address, high word */
   90 #define SIREG_DMA_ADDRL (NCR5380REGS_SZ + 2)    /* DMA address, low word */
   91 #define SIREG_DMA_CNTH  (NCR5380REGS_SZ + 4)    /* DMA count, high word */
   92 #define SIREG_DMA_CNTL  (NCR5380REGS_SZ + 6)    /* DMA count, low word */
   93 #define SIREG_FIFO_DATA (NCR5380REGS_SZ + 12)   /* FIFO data */
   94 #define SIREG_FIFO_CNT  (NCR5380REGS_SZ + 14)   /* FIFO count, low word */
   95 #define SIREG_CSR       (NCR5380REGS_SZ + 16)   /* Control/status register */
   96 #define SIREG_BPRH      (NCR5380REGS_SZ + 18)   /* VME byte pack, high word */
   97 #define SIREG_BPRL      (NCR5380REGS_SZ + 20)   /* VME byte pack, low word */
   98 #define SIREG_IV_AM     (NCR5380REGS_SZ + 22)   /* bits 0-7: intr vector;
   99                                                    bits 8-13: addr modifier */
  100 #define SIREG_FIFO_CNTH (NCR5380REGS_SZ + 24)   /* FIFO count, high word */
  101 #define SIREG_BANK_SZ   (NCR5380REGS_SZ + 26)
  102 
  103 /*
  104  * Status Register.
  105  * Note:
  106  *      (r)     indicates bit is read only.
  107  *      (rw)    indicates bit is read or write.
  108  *      (v)     vme host adaptor interface only.
  109  *      (o)     sun3/50 onboard host adaptor interface only.
  110  *      (b)     both vme and sun3/50 host adaptor interfaces.
  111  *
  112  * Note 2: because of the historical connections of this VME driver
  113  * with the on-board SCSI interfaces found in sun3/50, sun3/60 and sun4/100
  114  * systems, the (v), (o) and (b) qualifications are left in for
  115  * cross-reference.
  116  */
  117 #define SI_CSR_DMA_ACTIVE       0x8000  /* (r,o) DMA transfer active */
  118 #define SI_CSR_DMA_CONFLICT     0x4000  /* (r,b) reg accessed while DMA'ing */
  119 #define SI_CSR_DMA_BUS_ERR      0x2000  /* (r,b) bus error during DMA */
  120 #define SI_CSR_ID               0x1000  /* (r,b) 0 for 3/50, 1 for SCSI-3, */
  121                                         /* 0 if SCSI-3 unmodified */
  122 #define SI_CSR_FIFO_FULL        0x0800  /* (r,b) fifo full */
  123 #define SI_CSR_FIFO_EMPTY       0x0400  /* (r,b) fifo empty */
  124 #define SI_CSR_SBC_IP           0x0200  /* (r,b) sbc interrupt pending */
  125 #define SI_CSR_DMA_IP           0x0100  /* (r,b) DMA interrupt pending */
  126 #define SI_CSR_LOB              0x00c0  /* (r,v) number of leftover bytes */
  127 #define   SI_CSR_LOB_THREE      0x00c0  /* (r,v) three leftover bytes */
  128 #define   SI_CSR_LOB_TWO        0x0080  /* (r,v) two leftover bytes */
  129 #define   SI_CSR_LOB_ONE        0x0040  /* (r,v) one leftover byte */
  130 #define SI_CSR_BPCON            0x0020  /* (rw,v) byte packing control */
  131                                         /* DMA is in 0=longwords, 1=words */
  132 #define SI_CSR_DMA_EN           0x0010  /* (rw,v) DMA/interrupt enable */
  133 #define SI_CSR_SEND             0x0008  /* (rw,b) DMA dir, 1=to device */
  134 #define SI_CSR_INTR_EN          0x0004  /* (rw,b) interrupts enable */
  135 #define SI_CSR_FIFO_RES         0x0002  /* (rw,b) inits fifo, 0=reset */
  136 #define SI_CSR_SCSI_RES         0x0001  /* (rw,b) reset sbc and udc, 0=reset */

Cache object: 40d12bbf21cfb1d0cd3262a4b2b71b31


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