FreeBSD/Linux Kernel Cross Reference
sys/dev/vnic/nic.h
1 /*
2 * Copyright (C) 2015 Cavium Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 *
28 */
29
30 #ifndef NIC_H
31 #define NIC_H
32
33 /* PCI vendor ID */
34 #define PCI_VENDOR_ID_CAVIUM 0x177D
35 /* PCI device IDs */
36 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
37 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
38 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
39 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
40
41 /* PCI BAR nos */
42 #define PCI_CFG_REG_BAR_NUM 0
43 #define PCI_MSIX_REG_BAR_NUM 4
44
45 /* PCI revision IDs */
46 #define PCI_REVID_PASS2 8
47
48 /* NIC SRIOV VF count */
49 #define MAX_NUM_VFS_SUPPORTED 128
50 #define DEFAULT_NUM_VF_ENABLED 8
51
52 #define NIC_TNS_BYPASS_MODE 0
53 #define NIC_TNS_MODE 1
54
55 /* NIC priv flags */
56 #define NIC_SRIOV_ENABLED (1 << 0)
57 #define NIC_TNS_ENABLED (1 << 1)
58
59 /* ARM64TODO */
60 #if 0
61 /* VNIC HW optimiation features */
62 #define VNIC_RSS_SUPPORT
63 #define VNIC_MULTI_QSET_SUPPORT
64 #endif
65
66 /* Min/Max packet size */
67 #define NIC_HW_MIN_FRS 64
68 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */
69
70 /* Max pkinds */
71 #define NIC_MAX_PKIND 16
72
73 /*
74 * Rx Channels */
75 /* Receive channel configuration in TNS bypass mode
76 * Below is configuration in TNS bypass mode
77 * BGX0-LMAC0-CHAN0 - VNIC CHAN0
78 * BGX0-LMAC1-CHAN0 - VNIC CHAN16
79 * ...
80 * BGX1-LMAC0-CHAN0 - VNIC CHAN128
81 * ...
82 * BGX1-LMAC3-CHAN0 - VNIC CHAN174
83 */
84 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */
85 #define NIC_CHANS_PER_INF 128
86 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
87 #define NIC_CPI_COUNT 2048 /* No of channel parse indices */
88
89 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
90 #define NIC_MAX_BGX MAX_BGX_PER_CN88XX
91 #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX)
92 #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */
93 #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX)
94
95 /* Tx scheduling */
96 #define NIC_MAX_TL4 1024
97 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */
98 #define NIC_MAX_TL3 256
99 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */
100 #define NIC_MAX_TL2 64
101 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */
102 #define NIC_MAX_TL1 2
103
104 /* TNS bypass mode */
105 #define NIC_TL2_PER_BGX 32
106 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX)
107 #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF)
108
109 /* NIC VF Interrupts */
110 #define NICVF_INTR_CQ 0
111 #define NICVF_INTR_SQ 1
112 #define NICVF_INTR_RBDR 2
113 #define NICVF_INTR_PKT_DROP 3
114 #define NICVF_INTR_TCP_TIMER 4
115 #define NICVF_INTR_MBOX 5
116 #define NICVF_INTR_QS_ERR 6
117
118 #define NICVF_INTR_CQ_SHIFT 0
119 #define NICVF_INTR_SQ_SHIFT 8
120 #define NICVF_INTR_RBDR_SHIFT 16
121 #define NICVF_INTR_PKT_DROP_SHIFT 20
122 #define NICVF_INTR_TCP_TIMER_SHIFT 21
123 #define NICVF_INTR_MBOX_SHIFT 22
124 #define NICVF_INTR_QS_ERR_SHIFT 23
125
126 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
127 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
128 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
129 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT)
130 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT)
131 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT)
132 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT)
133
134 /* MSI-X interrupts */
135 #define NIC_PF_MSIX_VECTORS 10
136 #define NIC_VF_MSIX_VECTORS 20
137
138 #define NIC_PF_INTR_ID_ECC0_SBE 0
139 #define NIC_PF_INTR_ID_ECC0_DBE 1
140 #define NIC_PF_INTR_ID_ECC1_SBE 2
141 #define NIC_PF_INTR_ID_ECC1_DBE 3
142 #define NIC_PF_INTR_ID_ECC2_SBE 4
143 #define NIC_PF_INTR_ID_ECC2_DBE 5
144 #define NIC_PF_INTR_ID_ECC3_SBE 6
145 #define NIC_PF_INTR_ID_ECC3_DBE 7
146 #define NIC_PF_INTR_ID_MBOX0 8
147 #define NIC_PF_INTR_ID_MBOX1 9
148
149 struct msix_entry {
150 struct resource * irq_res;
151 void * handle;
152 };
153
154 /*
155 * Global timer for CQ timer thresh interrupts
156 * Calculated for SCLK of 700Mhz
157 * value written should be a 1/16th of what is expected
158 *
159 * 1 tick per 0.05usec = value of 2.2
160 * This 10% would be covered in CQ timer thresh value
161 */
162 #define NICPF_CLK_PER_INT_TICK 2
163
164 /*
165 * Time to wait before we decide that a SQ is stuck.
166 *
167 * Since both pkt rx and tx notifications are done with same CQ,
168 * when packets are being received at very high rate (eg: L2 forwarding)
169 * then freeing transmitted skbs will be delayed and watchdog
170 * will kick in, resetting interface. Hence keeping this value high.
171 */
172 #define NICVF_TX_TIMEOUT (50 * HZ)
173
174 #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */
175 #define NIC_MAX_RSS_HASH_BITS 8
176 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
177 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
178
179 struct nicvf_rss_info {
180 boolean_t enable;
181 #define RSS_L2_EXTENDED_HASH_ENA (1UL << 0)
182 #define RSS_IP_HASH_ENA (1UL << 1)
183 #define RSS_TCP_HASH_ENA (1UL << 2)
184 #define RSS_TCP_SYN_DIS (1UL << 3)
185 #define RSS_UDP_HASH_ENA (1UL << 4)
186 #define RSS_L4_EXTENDED_HASH_ENA (1UL << 5)
187 #define RSS_ROCE_ENA (1UL << 6)
188 #define RSS_L3_BI_DIRECTION_ENA (1UL << 7)
189 #define RSS_L4_BI_DIRECTION_ENA (1UL << 8)
190 uint64_t cfg;
191 uint8_t hash_bits;
192 uint16_t rss_size;
193 uint8_t ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
194 uint64_t key[RSS_HASH_KEY_SIZE];
195 };
196
197 enum rx_stats_reg_offset {
198 RX_OCTS = 0x0,
199 RX_UCAST = 0x1,
200 RX_BCAST = 0x2,
201 RX_MCAST = 0x3,
202 RX_RED = 0x4,
203 RX_RED_OCTS = 0x5,
204 RX_ORUN = 0x6,
205 RX_ORUN_OCTS = 0x7,
206 RX_FCS = 0x8,
207 RX_L2ERR = 0x9,
208 RX_DRP_BCAST = 0xa,
209 RX_DRP_MCAST = 0xb,
210 RX_DRP_L3BCAST = 0xc,
211 RX_DRP_L3MCAST = 0xd,
212 RX_STATS_ENUM_LAST,
213 };
214
215 enum tx_stats_reg_offset {
216 TX_OCTS = 0x0,
217 TX_UCAST = 0x1,
218 TX_BCAST = 0x2,
219 TX_MCAST = 0x3,
220 TX_DROP = 0x4,
221 TX_STATS_ENUM_LAST,
222 };
223
224 struct nicvf_hw_stats {
225 uint64_t rx_bytes;
226 uint64_t rx_ucast_frames;
227 uint64_t rx_bcast_frames;
228 uint64_t rx_mcast_frames;
229 uint64_t rx_fcs_errors;
230 uint64_t rx_l2_errors;
231 uint64_t rx_drop_red;
232 uint64_t rx_drop_red_bytes;
233 uint64_t rx_drop_overrun;
234 uint64_t rx_drop_overrun_bytes;
235 uint64_t rx_drop_bcast;
236 uint64_t rx_drop_mcast;
237 uint64_t rx_drop_l3_bcast;
238 uint64_t rx_drop_l3_mcast;
239 uint64_t rx_bgx_truncated_pkts;
240 uint64_t rx_jabber_errs;
241 uint64_t rx_fcs_errs;
242 uint64_t rx_bgx_errs;
243 uint64_t rx_prel2_errs;
244 uint64_t rx_l2_hdr_malformed;
245 uint64_t rx_oversize;
246 uint64_t rx_undersize;
247 uint64_t rx_l2_len_mismatch;
248 uint64_t rx_l2_pclp;
249 uint64_t rx_ip_ver_errs;
250 uint64_t rx_ip_csum_errs;
251 uint64_t rx_ip_hdr_malformed;
252 uint64_t rx_ip_payload_malformed;
253 uint64_t rx_ip_ttl_errs;
254 uint64_t rx_l3_pclp;
255 uint64_t rx_l4_malformed;
256 uint64_t rx_l4_csum_errs;
257 uint64_t rx_udp_len_errs;
258 uint64_t rx_l4_port_errs;
259 uint64_t rx_tcp_flag_errs;
260 uint64_t rx_tcp_offset_errs;
261 uint64_t rx_l4_pclp;
262 uint64_t rx_truncated_pkts;
263
264 uint64_t tx_bytes_ok;
265 uint64_t tx_ucast_frames_ok;
266 uint64_t tx_bcast_frames_ok;
267 uint64_t tx_mcast_frames_ok;
268 uint64_t tx_drops;
269 };
270
271 struct nicvf_drv_stats {
272 /* Rx */
273 uint64_t rx_frames_ok;
274 uint64_t rx_frames_64;
275 uint64_t rx_frames_127;
276 uint64_t rx_frames_255;
277 uint64_t rx_frames_511;
278 uint64_t rx_frames_1023;
279 uint64_t rx_frames_1518;
280 uint64_t rx_frames_jumbo;
281 uint64_t rx_drops;
282
283 /* Tx */
284 uint64_t tx_frames_ok;
285 uint64_t tx_drops;
286 uint64_t tx_tso;
287 uint64_t txq_stop;
288 uint64_t txq_wake;
289 };
290
291 struct nicvf {
292 struct nicvf *pnicvf;
293 device_t dev;
294
295 struct ifnet * ifp;
296 struct sx core_sx;
297 struct ifmedia if_media;
298 uint32_t if_flags;
299
300 uint8_t hwaddr[ETHER_ADDR_LEN];
301 uint8_t vf_id;
302 uint8_t node;
303 boolean_t tns_mode:1;
304 boolean_t sqs_mode:1;
305 bool loopback_supported:1;
306 struct nicvf_rss_info rss_info;
307 uint16_t mtu;
308 struct queue_set *qs;
309 uint8_t rx_queues;
310 uint8_t tx_queues;
311 uint8_t max_queues;
312 struct resource *reg_base;
313 boolean_t link_up;
314 boolean_t hw_tso;
315 uint8_t duplex;
316 uint32_t speed;
317 uint8_t cpi_alg;
318 /* Interrupt coalescing settings */
319 uint32_t cq_coalesce_usecs;
320
321 uint32_t msg_enable;
322 struct nicvf_hw_stats hw_stats;
323 struct nicvf_drv_stats drv_stats;
324 struct bgx_stats bgx_stats;
325
326 /* Interface statistics */
327 struct callout stats_callout;
328 struct mtx stats_mtx;
329
330 /* MSI-X */
331 boolean_t msix_enabled;
332 uint8_t num_vec;
333 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS];
334 struct resource * msix_table_res;
335 char irq_name[NIC_VF_MSIX_VECTORS][20];
336 boolean_t irq_allocated[NIC_VF_MSIX_VECTORS];
337
338 /* VF <-> PF mailbox communication */
339 boolean_t pf_acked;
340 boolean_t pf_nacked;
341 } __aligned(CACHE_LINE_SIZE);
342
343 /*
344 * PF <--> VF Mailbox communication
345 * Eight 64bit registers are shared between PF and VF.
346 * Separate set for each VF.
347 * Writing '1' into last register mbx7 means end of message.
348 */
349
350 /* PF <--> VF mailbox communication */
351 #define NIC_PF_VF_MAILBOX_SIZE 2
352 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */
353
354 /* Mailbox message types */
355 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
356 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
357 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
358 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
359 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
360 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
361 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
362 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
363 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
364 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
365 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
366 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
367 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
368 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
369 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
370 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
371 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
372 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
373 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
374 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
375 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
376 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
377 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
378 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
379
380 struct nic_cfg_msg {
381 uint8_t msg;
382 uint8_t vf_id;
383 uint8_t node_id;
384 boolean_t tns_mode:1;
385 boolean_t sqs_mode:1;
386 boolean_t loopback_supported:1;
387 uint8_t mac_addr[ETHER_ADDR_LEN];
388 };
389
390 /* Qset configuration */
391 struct qs_cfg_msg {
392 uint8_t msg;
393 uint8_t num;
394 uint8_t sqs_count;
395 uint64_t cfg;
396 };
397
398 /* Receive queue configuration */
399 struct rq_cfg_msg {
400 uint8_t msg;
401 uint8_t qs_num;
402 uint8_t rq_num;
403 uint64_t cfg;
404 };
405
406 /* Send queue configuration */
407 struct sq_cfg_msg {
408 uint8_t msg;
409 uint8_t qs_num;
410 uint8_t sq_num;
411 boolean_t sqs_mode;
412 uint64_t cfg;
413 };
414
415 /* Set VF's MAC address */
416 struct set_mac_msg {
417 uint8_t msg;
418 uint8_t vf_id;
419 uint8_t mac_addr[ETHER_ADDR_LEN];
420 };
421
422 /* Set Maximum frame size */
423 struct set_frs_msg {
424 uint8_t msg;
425 uint8_t vf_id;
426 uint16_t max_frs;
427 };
428
429 /* Set CPI algorithm type */
430 struct cpi_cfg_msg {
431 uint8_t msg;
432 uint8_t vf_id;
433 uint8_t rq_cnt;
434 uint8_t cpi_alg;
435 };
436
437 /* Get RSS table size */
438 struct rss_sz_msg {
439 uint8_t msg;
440 uint8_t vf_id;
441 uint16_t ind_tbl_size;
442 };
443
444 /* Set RSS configuration */
445 struct rss_cfg_msg {
446 uint8_t msg;
447 uint8_t vf_id;
448 uint8_t hash_bits;
449 uint8_t tbl_len;
450 uint8_t tbl_offset;
451 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8
452 uint8_t ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
453 };
454
455 struct bgx_stats_msg {
456 uint8_t msg;
457 uint8_t vf_id;
458 uint8_t rx;
459 uint8_t idx;
460 uint64_t stats;
461 };
462
463 /* Physical interface link status */
464 struct bgx_link_status {
465 uint8_t msg;
466 uint8_t link_up;
467 uint8_t duplex;
468 uint32_t speed;
469 };
470
471 /* Set interface in loopback mode */
472 struct set_loopback {
473 uint8_t msg;
474 uint8_t vf_id;
475 boolean_t enable;
476 };
477
478 /* 128 bit shared memory between PF and each VF */
479 union nic_mbx {
480 struct {
481 uint8_t msg;
482 } msg;
483 struct nic_cfg_msg nic_cfg;
484 struct qs_cfg_msg qs;
485 struct rq_cfg_msg rq;
486 struct sq_cfg_msg sq;
487 struct set_mac_msg mac;
488 struct set_frs_msg frs;
489 struct cpi_cfg_msg cpi_cfg;
490 struct rss_sz_msg rss_size;
491 struct rss_cfg_msg rss_cfg;
492 struct bgx_stats_msg bgx_stats;
493 struct bgx_link_status link_status;
494 struct set_loopback lbk;
495 };
496
497 #define NIC_NODE_ID_MASK 0x03
498 #define NIC_NODE_ID_SHIFT 44
499
500 static __inline int
501 nic_get_node_id(struct resource *res)
502 {
503 pci_addr_t addr;
504
505 addr = rman_get_start(res);
506 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK);
507 }
508
509 static __inline boolean_t
510 pass1_silicon(device_t dev)
511 {
512
513 /* Check if the chip revision is < Pass2 */
514 return (pci_get_revid(dev) < PCI_REVID_PASS2);
515 }
516
517 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
518
519 #endif /* NIC_H */
Cache object: 3885dd88a494239201daf4eb722ef678
|