FreeBSD/Linux Kernel Cross Reference
sys/dev/vr/if_vr.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * VIA Rhine fast ethernet PCI NIC driver
38 *
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47
48 /*
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
54 * to the tulip.
55 *
56 * Some Rhine chips has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
60 * transmission.
61 */
62
63 #ifdef HAVE_KERNEL_OPTION_HEADERS
64 #include "opt_device_polling.h"
65 #endif
66
67 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/bus.h>
70 #include <sys/endian.h>
71 #include <sys/kernel.h>
72 #include <sys/malloc.h>
73 #include <sys/mbuf.h>
74 #include <sys/module.h>
75 #include <sys/rman.h>
76 #include <sys/socket.h>
77 #include <sys/sockio.h>
78 #include <sys/sysctl.h>
79 #include <sys/taskqueue.h>
80
81 #include <net/bpf.h>
82 #include <net/if.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
87 #include <net/if_vlan_var.h>
88
89 #include <dev/mii/mii.h>
90 #include <dev/mii/miivar.h>
91
92 #include <dev/pci/pcireg.h>
93 #include <dev/pci/pcivar.h>
94
95 #include <machine/bus.h>
96
97 #include <dev/vr/if_vrreg.h>
98
99 /* "device miibus" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
101
102 MODULE_DEPEND(vr, pci, 1, 1, 1);
103 MODULE_DEPEND(vr, ether, 1, 1, 1);
104 MODULE_DEPEND(vr, miibus, 1, 1, 1);
105
106 /* Define to show Rx/Tx error status. */
107 #undef VR_SHOW_ERRORS
108 #define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
109
110 /*
111 * Various supported device vendors/types, their names & quirks.
112 */
113 #define VR_Q_NEEDALIGN (1<<0)
114 #define VR_Q_CSUM (1<<1)
115 #define VR_Q_CAM (1<<2)
116
117 static struct vr_type {
118 u_int16_t vr_vid;
119 u_int16_t vr_did;
120 int vr_quirks;
121 char *vr_name;
122 } vr_devs[] = {
123 { VIA_VENDORID, VIA_DEVICEID_RHINE,
124 VR_Q_NEEDALIGN,
125 "VIA VT3043 Rhine I 10/100BaseTX" },
126 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
127 VR_Q_NEEDALIGN,
128 "VIA VT86C100A Rhine II 10/100BaseTX" },
129 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
130 0,
131 "VIA VT6102 Rhine II 10/100BaseTX" },
132 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
133 0,
134 "VIA VT6105 Rhine III 10/100BaseTX" },
135 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
136 VR_Q_CSUM,
137 "VIA VT6105M Rhine III 10/100BaseTX" },
138 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
139 VR_Q_NEEDALIGN,
140 "Delta Electronics Rhine II 10/100BaseTX" },
141 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
142 VR_Q_NEEDALIGN,
143 "Addtron Technology Rhine II 10/100BaseTX" },
144 { 0, 0, 0, NULL }
145 };
146
147 static int vr_probe(device_t);
148 static int vr_attach(device_t);
149 static int vr_detach(device_t);
150 static int vr_shutdown(device_t);
151 static int vr_suspend(device_t);
152 static int vr_resume(device_t);
153
154 static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int);
155 static int vr_dma_alloc(struct vr_softc *);
156 static void vr_dma_free(struct vr_softc *);
157 static __inline void vr_discard_rxbuf(struct vr_rxdesc *);
158 static int vr_newbuf(struct vr_softc *, int);
159
160 #ifndef __NO_STRICT_ALIGNMENT
161 static __inline void vr_fixup_rx(struct mbuf *);
162 #endif
163 static void vr_rxeof(struct vr_softc *);
164 static void vr_txeof(struct vr_softc *);
165 static void vr_tick(void *);
166 static int vr_error(struct vr_softc *, uint16_t);
167 static void vr_tx_underrun(struct vr_softc *);
168 static void vr_intr(void *);
169 static void vr_start(struct ifnet *);
170 static void vr_start_locked(struct ifnet *);
171 static int vr_encap(struct vr_softc *, struct mbuf **);
172 static int vr_ioctl(struct ifnet *, u_long, caddr_t);
173 static void vr_init(void *);
174 static void vr_init_locked(struct vr_softc *);
175 static void vr_tx_start(struct vr_softc *);
176 static void vr_rx_start(struct vr_softc *);
177 static int vr_tx_stop(struct vr_softc *);
178 static int vr_rx_stop(struct vr_softc *);
179 static void vr_stop(struct vr_softc *);
180 static void vr_watchdog(struct vr_softc *);
181 static int vr_ifmedia_upd(struct ifnet *);
182 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
183
184 static int vr_miibus_readreg(device_t, int, int);
185 static int vr_miibus_writereg(device_t, int, int, int);
186 static void vr_miibus_statchg(device_t);
187
188 static void vr_link_task(void *, int);
189 static void vr_cam_mask(struct vr_softc *, uint32_t, int);
190 static int vr_cam_data(struct vr_softc *, int, int, uint8_t *);
191 static void vr_set_filter(struct vr_softc *);
192 static void vr_reset(const struct vr_softc *);
193 static int vr_tx_ring_init(struct vr_softc *);
194 static int vr_rx_ring_init(struct vr_softc *);
195 static void vr_setwol(struct vr_softc *);
196 static void vr_clrwol(struct vr_softc *);
197 static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS);
198
199 static struct vr_tx_threshold_table {
200 int tx_cfg;
201 int bcr_cfg;
202 int value;
203 } vr_tx_threshold_tables[] = {
204 { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 },
205 { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 },
206 { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 },
207 { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 },
208 { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 },
209 { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 }
210 };
211
212 static device_method_t vr_methods[] = {
213 /* Device interface */
214 DEVMETHOD(device_probe, vr_probe),
215 DEVMETHOD(device_attach, vr_attach),
216 DEVMETHOD(device_detach, vr_detach),
217 DEVMETHOD(device_shutdown, vr_shutdown),
218 DEVMETHOD(device_suspend, vr_suspend),
219 DEVMETHOD(device_resume, vr_resume),
220
221 /* bus interface */
222 DEVMETHOD(bus_print_child, bus_generic_print_child),
223 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
224
225 /* MII interface */
226 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
227 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
228 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
229 DEVMETHOD(miibus_linkchg, vr_miibus_statchg),
230
231 { NULL, NULL }
232 };
233
234 static driver_t vr_driver = {
235 "vr",
236 vr_methods,
237 sizeof(struct vr_softc)
238 };
239
240 static devclass_t vr_devclass;
241
242 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0);
243 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
244
245 static int
246 vr_miibus_readreg(device_t dev, int phy, int reg)
247 {
248 struct vr_softc *sc;
249 int i;
250
251 sc = device_get_softc(dev);
252 if (sc->vr_phyaddr != phy)
253 return (0);
254
255 /* Set the register address. */
256 CSR_WRITE_1(sc, VR_MIIADDR, reg);
257 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
258
259 for (i = 0; i < VR_MII_TIMEOUT; i++) {
260 DELAY(1);
261 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
262 break;
263 }
264 if (i == VR_MII_TIMEOUT)
265 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);
266
267 return (CSR_READ_2(sc, VR_MIIDATA));
268 }
269
270 static int
271 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
272 {
273 struct vr_softc *sc;
274 int i;
275
276 sc = device_get_softc(dev);
277 if (sc->vr_phyaddr != phy)
278 return (0);
279
280 /* Set the register address and data to write. */
281 CSR_WRITE_1(sc, VR_MIIADDR, reg);
282 CSR_WRITE_2(sc, VR_MIIDATA, data);
283 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
284
285 for (i = 0; i < VR_MII_TIMEOUT; i++) {
286 DELAY(1);
287 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
288 break;
289 }
290 if (i == VR_MII_TIMEOUT)
291 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy,
292 reg);
293
294 return (0);
295 }
296
297 static void
298 vr_miibus_statchg(device_t dev)
299 {
300 struct vr_softc *sc;
301
302 sc = device_get_softc(dev);
303 taskqueue_enqueue(taskqueue_swi, &sc->vr_link_task);
304 }
305
306 /*
307 * In order to fiddle with the
308 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
309 * first have to put the transmit and/or receive logic in the idle state.
310 */
311 static void
312 vr_link_task(void *arg, int pending)
313 {
314 struct vr_softc *sc;
315 struct mii_data *mii;
316 struct ifnet *ifp;
317 int lfdx, mfdx;
318 uint8_t cr0, cr1, fc;
319
320 sc = (struct vr_softc *)arg;
321
322 VR_LOCK(sc);
323 mii = device_get_softc(sc->vr_miibus);
324 ifp = sc->vr_ifp;
325 if (mii == NULL || ifp == NULL ||
326 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
327 VR_UNLOCK(sc);
328 return;
329 }
330
331 if (mii->mii_media_status & IFM_ACTIVE) {
332 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
333 sc->vr_link = 1;
334 } else
335 sc->vr_link = 0;
336
337 if (sc->vr_link != 0) {
338 cr0 = CSR_READ_1(sc, VR_CR0);
339 cr1 = CSR_READ_1(sc, VR_CR1);
340 mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0;
341 lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0;
342 if (mfdx != lfdx) {
343 if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) {
344 if (vr_tx_stop(sc) != 0 ||
345 vr_rx_stop(sc) != 0) {
346 device_printf(sc->vr_dev,
347 "%s: Tx/Rx shutdown error -- "
348 "resetting\n", __func__);
349 sc->vr_flags |= VR_F_RESTART;
350 VR_UNLOCK(sc);
351 return;
352 }
353 }
354 if (lfdx)
355 cr1 |= VR_CR1_FULLDUPLEX;
356 else
357 cr1 &= ~VR_CR1_FULLDUPLEX;
358 CSR_WRITE_1(sc, VR_CR1, cr1);
359 }
360 fc = 0;
361 #ifdef notyet
362 /* Configure flow-control. */
363 if (sc->vr_revid >= REV_ID_VT6105_A0) {
364 fc = CSR_READ_1(sc, VR_FLOWCR1);
365 fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE);
366 if ((IFM_OPTIONS(mii->mii_media_active) &
367 IFM_ETH_RXPAUSE) != 0)
368 fc |= VR_FLOWCR1_RXPAUSE;
369 if ((IFM_OPTIONS(mii->mii_media_active) &
370 IFM_ETH_TXPAUSE) != 0)
371 fc |= VR_FLOWCR1_TXPAUSE;
372 CSR_WRITE_1(sc, VR_FLOWCR1, fc);
373 } else if (sc->vr_revid >= REV_ID_VT6102_A) {
374 /* No Tx puase capability available for Rhine II. */
375 fc = CSR_READ_1(sc, VR_MISC_CR0);
376 fc &= ~VR_MISCCR0_RXPAUSE;
377 if ((IFM_OPTIONS(mii->mii_media_active) &
378 IFM_ETH_RXPAUSE) != 0)
379 fc |= VR_MISCCR0_RXPAUSE;
380 CSR_WRITE_1(sc, VR_MISC_CR0, fc);
381 }
382 #endif
383 vr_rx_start(sc);
384 vr_tx_start(sc);
385 } else {
386 if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) {
387 device_printf(sc->vr_dev,
388 "%s: Tx/Rx shutdown error -- resetting\n",
389 __func__);
390 sc->vr_flags |= VR_F_RESTART;
391 VR_UNLOCK(sc);
392 return;
393 }
394 }
395 VR_UNLOCK(sc);
396 }
397
398
399 static void
400 vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type)
401 {
402
403 if (type == VR_MCAST_CAM)
404 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
405 else
406 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
407 CSR_WRITE_4(sc, VR_CAMMASK, mask);
408 CSR_WRITE_1(sc, VR_CAMCTL, 0);
409 }
410
411 static int
412 vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac)
413 {
414 int i;
415
416 if (type == VR_MCAST_CAM) {
417 if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL)
418 return (EINVAL);
419 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
420 } else
421 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
422
423 /* Set CAM entry address. */
424 CSR_WRITE_1(sc, VR_CAMADDR, idx);
425 /* Set CAM entry data. */
426 if (type == VR_MCAST_CAM) {
427 for (i = 0; i < ETHER_ADDR_LEN; i++)
428 CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]);
429 } else {
430 CSR_WRITE_1(sc, VR_VCAM0, mac[0]);
431 CSR_WRITE_1(sc, VR_VCAM1, mac[1]);
432 }
433 DELAY(10);
434 /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */
435 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE);
436 for (i = 0; i < VR_TIMEOUT; i++) {
437 DELAY(1);
438 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
439 break;
440 }
441
442 if (i == VR_TIMEOUT)
443 device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n",
444 __func__);
445 CSR_WRITE_1(sc, VR_CAMCTL, 0);
446
447 return (i == VR_TIMEOUT ? ETIMEDOUT : 0);
448 }
449
450 /*
451 * Program the 64-bit multicast hash filter.
452 */
453 static void
454 vr_set_filter(struct vr_softc *sc)
455 {
456 struct ifnet *ifp;
457 int h;
458 uint32_t hashes[2] = { 0, 0 };
459 struct ifmultiaddr *ifma;
460 uint8_t rxfilt;
461 int error, mcnt;
462 uint32_t cam_mask;
463
464 VR_LOCK_ASSERT(sc);
465
466 ifp = sc->vr_ifp;
467 rxfilt = CSR_READ_1(sc, VR_RXCFG);
468 rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD |
469 VR_RXCFG_RX_MULTI);
470 if (ifp->if_flags & IFF_BROADCAST)
471 rxfilt |= VR_RXCFG_RX_BROAD;
472 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
473 rxfilt |= VR_RXCFG_RX_MULTI;
474 if (ifp->if_flags & IFF_PROMISC)
475 rxfilt |= VR_RXCFG_RX_PROMISC;
476 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
477 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
478 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
479 return;
480 }
481
482 /* Now program new ones. */
483 error = 0;
484 mcnt = 0;
485 IF_ADDR_LOCK(ifp);
486 if ((sc->vr_quirks & VR_Q_CAM) != 0) {
487 /*
488 * For hardwares that have CAM capability, use
489 * 32 entries multicast perfect filter.
490 */
491 cam_mask = 0;
492 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
493 if (ifma->ifma_addr->sa_family != AF_LINK)
494 continue;
495 error = vr_cam_data(sc, VR_MCAST_CAM, mcnt,
496 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
497 if (error != 0) {
498 cam_mask = 0;
499 break;
500 }
501 cam_mask |= 1 << mcnt;
502 mcnt++;
503 }
504 vr_cam_mask(sc, VR_MCAST_CAM, cam_mask);
505 }
506
507 if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) {
508 /*
509 * If there are too many multicast addresses or
510 * setting multicast CAM filter failed, use hash
511 * table based filtering.
512 */
513 mcnt = 0;
514 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
515 if (ifma->ifma_addr->sa_family != AF_LINK)
516 continue;
517 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
518 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
519 if (h < 32)
520 hashes[0] |= (1 << h);
521 else
522 hashes[1] |= (1 << (h - 32));
523 mcnt++;
524 }
525 }
526 IF_ADDR_UNLOCK(ifp);
527
528 if (mcnt > 0)
529 rxfilt |= VR_RXCFG_RX_MULTI;
530
531 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
532 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
533 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
534 }
535
536 static void
537 vr_reset(const struct vr_softc *sc)
538 {
539 int i;
540
541 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */
542
543 CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET);
544 if (sc->vr_revid < REV_ID_VT6102_A) {
545 /* VT86C100A needs more delay after reset. */
546 DELAY(100);
547 }
548 for (i = 0; i < VR_TIMEOUT; i++) {
549 DELAY(10);
550 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
551 break;
552 }
553 if (i == VR_TIMEOUT) {
554 if (sc->vr_revid < REV_ID_VT6102_A)
555 device_printf(sc->vr_dev, "reset never completed!\n");
556 else {
557 /* Use newer force reset command. */
558 device_printf(sc->vr_dev,
559 "Using force reset command.\n");
560 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
561 /*
562 * Wait a little while for the chip to get its brains
563 * in order.
564 */
565 DELAY(2000);
566 }
567 }
568
569 }
570
571 /*
572 * Probe for a VIA Rhine chip. Check the PCI vendor and device
573 * IDs against our list and return a match or NULL
574 */
575 static struct vr_type *
576 vr_match(device_t dev)
577 {
578 struct vr_type *t = vr_devs;
579
580 for (t = vr_devs; t->vr_name != NULL; t++)
581 if ((pci_get_vendor(dev) == t->vr_vid) &&
582 (pci_get_device(dev) == t->vr_did))
583 return (t);
584 return (NULL);
585 }
586
587 /*
588 * Probe for a VIA Rhine chip. Check the PCI vendor and device
589 * IDs against our list and return a device name if we find a match.
590 */
591 static int
592 vr_probe(device_t dev)
593 {
594 struct vr_type *t;
595
596 t = vr_match(dev);
597 if (t != NULL) {
598 device_set_desc(dev, t->vr_name);
599 return (BUS_PROBE_DEFAULT);
600 }
601 return (ENXIO);
602 }
603
604 /*
605 * Attach the interface. Allocate softc structures, do ifmedia
606 * setup and ethernet/BPF attach.
607 */
608 static int
609 vr_attach(device_t dev)
610 {
611 struct vr_softc *sc;
612 struct ifnet *ifp;
613 struct vr_type *t;
614 uint8_t eaddr[ETHER_ADDR_LEN];
615 int error, rid;
616 int i, pmc;
617
618 sc = device_get_softc(dev);
619 sc->vr_dev = dev;
620 t = vr_match(dev);
621 KASSERT(t != NULL, ("Lost if_vr device match"));
622 sc->vr_quirks = t->vr_quirks;
623 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks);
624
625 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
626 MTX_DEF);
627 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0);
628 TASK_INIT(&sc->vr_link_task, 0, vr_link_task, sc);
629 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
630 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
631 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
632 vr_sysctl_stats, "I", "Statistics");
633
634 error = 0;
635
636 /*
637 * Map control/status registers.
638 */
639 pci_enable_busmaster(dev);
640 sc->vr_revid = pci_get_revid(dev);
641 device_printf(dev, "Revision: 0x%x\n", sc->vr_revid);
642
643 sc->vr_res_id = PCIR_BAR(0);
644 sc->vr_res_type = SYS_RES_IOPORT;
645 sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type,
646 &sc->vr_res_id, RF_ACTIVE);
647 if (sc->vr_res == NULL) {
648 device_printf(dev, "couldn't map ports\n");
649 error = ENXIO;
650 goto fail;
651 }
652
653 /* Allocate interrupt. */
654 rid = 0;
655 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
656 RF_SHAREABLE | RF_ACTIVE);
657
658 if (sc->vr_irq == NULL) {
659 device_printf(dev, "couldn't map interrupt\n");
660 error = ENXIO;
661 goto fail;
662 }
663
664 /* Allocate ifnet structure. */
665 ifp = sc->vr_ifp = if_alloc(IFT_ETHER);
666 if (ifp == NULL) {
667 device_printf(dev, "couldn't allocate ifnet structure\n");
668 error = ENOSPC;
669 goto fail;
670 }
671 ifp->if_softc = sc;
672 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
673 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
674 ifp->if_ioctl = vr_ioctl;
675 ifp->if_start = vr_start;
676 ifp->if_init = vr_init;
677 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1);
678 ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1;
679 IFQ_SET_READY(&ifp->if_snd);
680
681 /* Configure Tx FIFO threshold. */
682 sc->vr_txthresh = VR_TXTHRESH_MIN;
683 if (sc->vr_revid < REV_ID_VT6105_A0) {
684 /*
685 * Use store and forward mode for Rhine I/II.
686 * Otherwise they produce a lot of Tx underruns and
687 * it would take a while to get working FIFO threshold
688 * value.
689 */
690 sc->vr_txthresh = VR_TXTHRESH_MAX;
691 }
692 if ((sc->vr_quirks & VR_Q_CSUM) != 0) {
693 ifp->if_hwassist = VR_CSUM_FEATURES;
694 ifp->if_capabilities |= IFCAP_HWCSUM;
695 /*
696 * To update checksum field the hardware may need to
697 * store entire frames into FIFO before transmitting.
698 */
699 sc->vr_txthresh = VR_TXTHRESH_MAX;
700 }
701
702 if (sc->vr_revid >= REV_ID_VT6102_A &&
703 pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
704 ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC;
705
706 /* Rhine supports oversized VLAN frame. */
707 ifp->if_capabilities |= IFCAP_VLAN_MTU;
708 ifp->if_capenable = ifp->if_capabilities;
709 #ifdef DEVICE_POLLING
710 ifp->if_capabilities |= IFCAP_POLLING;
711 #endif
712
713 /*
714 * Windows may put the chip in suspend mode when it
715 * shuts down. Be sure to kick it in the head to wake it
716 * up again.
717 */
718 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
719 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
720
721 /*
722 * Get station address. The way the Rhine chips work,
723 * you're not allowed to directly access the EEPROM once
724 * they've been programmed a special way. Consequently,
725 * we need to read the node address from the PAR0 and PAR1
726 * registers.
727 * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB,
728 * VR_CFGC and VR_CFGD such that memory mapped IO configured
729 * by driver is reset to default state.
730 */
731 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
732 for (i = VR_TIMEOUT; i > 0; i--) {
733 DELAY(1);
734 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0)
735 break;
736 }
737 if (i == 0)
738 device_printf(dev, "Reloading EEPROM timeout!\n");
739 for (i = 0; i < ETHER_ADDR_LEN; i++)
740 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
741
742 /* Reset the adapter. */
743 vr_reset(sc);
744 /* Ack intr & disable further interrupts. */
745 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
746 CSR_WRITE_2(sc, VR_IMR, 0);
747 if (sc->vr_revid >= REV_ID_VT6102_A)
748 CSR_WRITE_2(sc, VR_MII_IMR, 0);
749
750 if (sc->vr_revid < REV_ID_VT6102_A) {
751 pci_write_config(dev, VR_PCI_MODE2,
752 pci_read_config(dev, VR_PCI_MODE2, 1) |
753 VR_MODE2_MODE10T, 1);
754 } else {
755 /* Report error instead of retrying forever. */
756 pci_write_config(dev, VR_PCI_MODE2,
757 pci_read_config(dev, VR_PCI_MODE2, 1) |
758 VR_MODE2_PCEROPT, 1);
759 /* Detect MII coding error. */
760 pci_write_config(dev, VR_PCI_MODE3,
761 pci_read_config(dev, VR_PCI_MODE3, 1) |
762 VR_MODE3_MIION, 1);
763 if (sc->vr_revid >= REV_ID_VT6105_LOM &&
764 sc->vr_revid < REV_ID_VT6105M_A0)
765 pci_write_config(dev, VR_PCI_MODE2,
766 pci_read_config(dev, VR_PCI_MODE2, 1) |
767 VR_MODE2_MODE10T, 1);
768 /* Enable Memory-Read-Multiple. */
769 if (sc->vr_revid >= REV_ID_VT6107_A1 &&
770 sc->vr_revid < REV_ID_VT6105M_A0)
771 pci_write_config(dev, VR_PCI_MODE2,
772 pci_read_config(dev, VR_PCI_MODE2, 1) |
773 VR_MODE2_MRDPL, 1);
774 }
775 /* Disable MII AUTOPOLL. */
776 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
777
778 if (vr_dma_alloc(sc) != 0) {
779 error = ENXIO;
780 goto fail;
781 }
782
783 /* Save PHY address. */
784 if (sc->vr_revid >= REV_ID_VT6105_A0)
785 sc->vr_phyaddr = 1;
786 else
787 sc->vr_phyaddr = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
788
789 /* Do MII setup. */
790 if (mii_phy_probe(dev, &sc->vr_miibus,
791 vr_ifmedia_upd, vr_ifmedia_sts)) {
792 device_printf(dev, "MII without any phy!\n");
793 error = ENXIO;
794 goto fail;
795 }
796
797 /* Call MI attach routine. */
798 ether_ifattach(ifp, eaddr);
799 /*
800 * Tell the upper layer(s) we support long frames.
801 * Must appear after the call to ether_ifattach() because
802 * ether_ifattach() sets ifi_hdrlen to the default value.
803 */
804 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
805
806 /* Hook interrupt last to avoid having to lock softc. */
807 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE,
808 NULL, vr_intr, sc, &sc->vr_intrhand);
809
810 if (error) {
811 device_printf(dev, "couldn't set up irq\n");
812 ether_ifdetach(ifp);
813 goto fail;
814 }
815
816 fail:
817 if (error)
818 vr_detach(dev);
819
820 return (error);
821 }
822
823 /*
824 * Shutdown hardware and free up resources. This can be called any
825 * time after the mutex has been initialized. It is called in both
826 * the error case in attach and the normal detach case so it needs
827 * to be careful about only freeing resources that have actually been
828 * allocated.
829 */
830 static int
831 vr_detach(device_t dev)
832 {
833 struct vr_softc *sc = device_get_softc(dev);
834 struct ifnet *ifp = sc->vr_ifp;
835
836 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized"));
837
838 #ifdef DEVICE_POLLING
839 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
840 ether_poll_deregister(ifp);
841 #endif
842
843 /* These should only be active if attach succeeded. */
844 if (device_is_attached(dev)) {
845 VR_LOCK(sc);
846 sc->vr_detach = 1;
847 vr_stop(sc);
848 VR_UNLOCK(sc);
849 callout_drain(&sc->vr_stat_callout);
850 taskqueue_drain(taskqueue_swi, &sc->vr_link_task);
851 ether_ifdetach(ifp);
852 }
853 if (sc->vr_miibus)
854 device_delete_child(dev, sc->vr_miibus);
855 bus_generic_detach(dev);
856
857 if (sc->vr_intrhand)
858 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
859 if (sc->vr_irq)
860 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
861 if (sc->vr_res)
862 bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id,
863 sc->vr_res);
864
865 if (ifp)
866 if_free(ifp);
867
868 vr_dma_free(sc);
869
870 mtx_destroy(&sc->vr_mtx);
871
872 return (0);
873 }
874
875 struct vr_dmamap_arg {
876 bus_addr_t vr_busaddr;
877 };
878
879 static void
880 vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
881 {
882 struct vr_dmamap_arg *ctx;
883
884 if (error != 0)
885 return;
886 ctx = arg;
887 ctx->vr_busaddr = segs[0].ds_addr;
888 }
889
890 static int
891 vr_dma_alloc(struct vr_softc *sc)
892 {
893 struct vr_dmamap_arg ctx;
894 struct vr_txdesc *txd;
895 struct vr_rxdesc *rxd;
896 bus_size_t tx_alignment;
897 int error, i;
898
899 /* Create parent DMA tag. */
900 error = bus_dma_tag_create(
901 bus_get_dma_tag(sc->vr_dev), /* parent */
902 1, 0, /* alignment, boundary */
903 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
904 BUS_SPACE_MAXADDR, /* highaddr */
905 NULL, NULL, /* filter, filterarg */
906 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
907 0, /* nsegments */
908 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
909 0, /* flags */
910 NULL, NULL, /* lockfunc, lockarg */
911 &sc->vr_cdata.vr_parent_tag);
912 if (error != 0) {
913 device_printf(sc->vr_dev, "failed to create parent DMA tag\n");
914 goto fail;
915 }
916 /* Create tag for Tx ring. */
917 error = bus_dma_tag_create(
918 sc->vr_cdata.vr_parent_tag, /* parent */
919 VR_RING_ALIGN, 0, /* alignment, boundary */
920 BUS_SPACE_MAXADDR, /* lowaddr */
921 BUS_SPACE_MAXADDR, /* highaddr */
922 NULL, NULL, /* filter, filterarg */
923 VR_TX_RING_SIZE, /* maxsize */
924 1, /* nsegments */
925 VR_TX_RING_SIZE, /* maxsegsize */
926 0, /* flags */
927 NULL, NULL, /* lockfunc, lockarg */
928 &sc->vr_cdata.vr_tx_ring_tag);
929 if (error != 0) {
930 device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n");
931 goto fail;
932 }
933
934 /* Create tag for Rx ring. */
935 error = bus_dma_tag_create(
936 sc->vr_cdata.vr_parent_tag, /* parent */
937 VR_RING_ALIGN, 0, /* alignment, boundary */
938 BUS_SPACE_MAXADDR, /* lowaddr */
939 BUS_SPACE_MAXADDR, /* highaddr */
940 NULL, NULL, /* filter, filterarg */
941 VR_RX_RING_SIZE, /* maxsize */
942 1, /* nsegments */
943 VR_RX_RING_SIZE, /* maxsegsize */
944 0, /* flags */
945 NULL, NULL, /* lockfunc, lockarg */
946 &sc->vr_cdata.vr_rx_ring_tag);
947 if (error != 0) {
948 device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n");
949 goto fail;
950 }
951
952 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0)
953 tx_alignment = sizeof(uint32_t);
954 else
955 tx_alignment = 1;
956 /* Create tag for Tx buffers. */
957 error = bus_dma_tag_create(
958 sc->vr_cdata.vr_parent_tag, /* parent */
959 tx_alignment, 0, /* alignment, boundary */
960 BUS_SPACE_MAXADDR, /* lowaddr */
961 BUS_SPACE_MAXADDR, /* highaddr */
962 NULL, NULL, /* filter, filterarg */
963 MCLBYTES * VR_MAXFRAGS, /* maxsize */
964 VR_MAXFRAGS, /* nsegments */
965 MCLBYTES, /* maxsegsize */
966 0, /* flags */
967 NULL, NULL, /* lockfunc, lockarg */
968 &sc->vr_cdata.vr_tx_tag);
969 if (error != 0) {
970 device_printf(sc->vr_dev, "failed to create Tx DMA tag\n");
971 goto fail;
972 }
973
974 /* Create tag for Rx buffers. */
975 error = bus_dma_tag_create(
976 sc->vr_cdata.vr_parent_tag, /* parent */
977 VR_RX_ALIGN, 0, /* alignment, boundary */
978 BUS_SPACE_MAXADDR, /* lowaddr */
979 BUS_SPACE_MAXADDR, /* highaddr */
980 NULL, NULL, /* filter, filterarg */
981 MCLBYTES, /* maxsize */
982 1, /* nsegments */
983 MCLBYTES, /* maxsegsize */
984 0, /* flags */
985 NULL, NULL, /* lockfunc, lockarg */
986 &sc->vr_cdata.vr_rx_tag);
987 if (error != 0) {
988 device_printf(sc->vr_dev, "failed to create Rx DMA tag\n");
989 goto fail;
990 }
991
992 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
993 error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag,
994 (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK |
995 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map);
996 if (error != 0) {
997 device_printf(sc->vr_dev,
998 "failed to allocate DMA'able memory for Tx ring\n");
999 goto fail;
1000 }
1001
1002 ctx.vr_busaddr = 0;
1003 error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag,
1004 sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring,
1005 VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
1006 if (error != 0 || ctx.vr_busaddr == 0) {
1007 device_printf(sc->vr_dev,
1008 "failed to load DMA'able memory for Tx ring\n");
1009 goto fail;
1010 }
1011 sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr;
1012
1013 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1014 error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag,
1015 (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK |
1016 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map);
1017 if (error != 0) {
1018 device_printf(sc->vr_dev,
1019 "failed to allocate DMA'able memory for Rx ring\n");
1020 goto fail;
1021 }
1022
1023 ctx.vr_busaddr = 0;
1024 error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag,
1025 sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring,
1026 VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
1027 if (error != 0 || ctx.vr_busaddr == 0) {
1028 device_printf(sc->vr_dev,
1029 "failed to load DMA'able memory for Rx ring\n");
1030 goto fail;
1031 }
1032 sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr;
1033
1034 /* Create DMA maps for Tx buffers. */
1035 for (i = 0; i < VR_TX_RING_CNT; i++) {
1036 txd = &sc->vr_cdata.vr_txdesc[i];
1037 txd->tx_m = NULL;
1038 txd->tx_dmamap = NULL;
1039 error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0,
1040 &txd->tx_dmamap);
1041 if (error != 0) {
1042 device_printf(sc->vr_dev,
1043 "failed to create Tx dmamap\n");
1044 goto fail;
1045 }
1046 }
1047 /* Create DMA maps for Rx buffers. */
1048 if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
1049 &sc->vr_cdata.vr_rx_sparemap)) != 0) {
1050 device_printf(sc->vr_dev,
1051 "failed to create spare Rx dmamap\n");
1052 goto fail;
1053 }
1054 for (i = 0; i < VR_RX_RING_CNT; i++) {
1055 rxd = &sc->vr_cdata.vr_rxdesc[i];
1056 rxd->rx_m = NULL;
1057 rxd->rx_dmamap = NULL;
1058 error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
1059 &rxd->rx_dmamap);
1060 if (error != 0) {
1061 device_printf(sc->vr_dev,
1062 "failed to create Rx dmamap\n");
1063 goto fail;
1064 }
1065 }
1066
1067 fail:
1068 return (error);
1069 }
1070
1071 static void
1072 vr_dma_free(struct vr_softc *sc)
1073 {
1074 struct vr_txdesc *txd;
1075 struct vr_rxdesc *rxd;
1076 int i;
1077
1078 /* Tx ring. */
1079 if (sc->vr_cdata.vr_tx_ring_tag) {
1080 if (sc->vr_cdata.vr_tx_ring_map)
1081 bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag,
1082 sc->vr_cdata.vr_tx_ring_map);
1083 if (sc->vr_cdata.vr_tx_ring_map &&
1084 sc->vr_rdata.vr_tx_ring)
1085 bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag,
1086 sc->vr_rdata.vr_tx_ring,
1087 sc->vr_cdata.vr_tx_ring_map);
1088 sc->vr_rdata.vr_tx_ring = NULL;
1089 sc->vr_cdata.vr_tx_ring_map = NULL;
1090 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag);
1091 sc->vr_cdata.vr_tx_ring_tag = NULL;
1092 }
1093 /* Rx ring. */
1094 if (sc->vr_cdata.vr_rx_ring_tag) {
1095 if (sc->vr_cdata.vr_rx_ring_map)
1096 bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag,
1097 sc->vr_cdata.vr_rx_ring_map);
1098 if (sc->vr_cdata.vr_rx_ring_map &&
1099 sc->vr_rdata.vr_rx_ring)
1100 bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag,
1101 sc->vr_rdata.vr_rx_ring,
1102 sc->vr_cdata.vr_rx_ring_map);
1103 sc->vr_rdata.vr_rx_ring = NULL;
1104 sc->vr_cdata.vr_rx_ring_map = NULL;
1105 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag);
1106 sc->vr_cdata.vr_rx_ring_tag = NULL;
1107 }
1108 /* Tx buffers. */
1109 if (sc->vr_cdata.vr_tx_tag) {
1110 for (i = 0; i < VR_TX_RING_CNT; i++) {
1111 txd = &sc->vr_cdata.vr_txdesc[i];
1112 if (txd->tx_dmamap) {
1113 bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag,
1114 txd->tx_dmamap);
1115 txd->tx_dmamap = NULL;
1116 }
1117 }
1118 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag);
1119 sc->vr_cdata.vr_tx_tag = NULL;
1120 }
1121 /* Rx buffers. */
1122 if (sc->vr_cdata.vr_rx_tag) {
1123 for (i = 0; i < VR_RX_RING_CNT; i++) {
1124 rxd = &sc->vr_cdata.vr_rxdesc[i];
1125 if (rxd->rx_dmamap) {
1126 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
1127 rxd->rx_dmamap);
1128 rxd->rx_dmamap = NULL;
1129 }
1130 }
1131 if (sc->vr_cdata.vr_rx_sparemap) {
1132 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
1133 sc->vr_cdata.vr_rx_sparemap);
1134 sc->vr_cdata.vr_rx_sparemap = 0;
1135 }
1136 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag);
1137 sc->vr_cdata.vr_rx_tag = NULL;
1138 }
1139
1140 if (sc->vr_cdata.vr_parent_tag) {
1141 bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag);
1142 sc->vr_cdata.vr_parent_tag = NULL;
1143 }
1144 }
1145
1146 /*
1147 * Initialize the transmit descriptors.
1148 */
1149 static int
1150 vr_tx_ring_init(struct vr_softc *sc)
1151 {
1152 struct vr_ring_data *rd;
1153 struct vr_txdesc *txd;
1154 bus_addr_t addr;
1155 int i;
1156
1157 sc->vr_cdata.vr_tx_prod = 0;
1158 sc->vr_cdata.vr_tx_cons = 0;
1159 sc->vr_cdata.vr_tx_cnt = 0;
1160 sc->vr_cdata.vr_tx_pkts = 0;
1161
1162 rd = &sc->vr_rdata;
1163 bzero(rd->vr_tx_ring, VR_TX_RING_SIZE);
1164 for (i = 0; i < VR_TX_RING_CNT; i++) {
1165 if (i == VR_TX_RING_CNT - 1)
1166 addr = VR_TX_RING_ADDR(sc, 0);
1167 else
1168 addr = VR_TX_RING_ADDR(sc, i + 1);
1169 rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
1170 txd = &sc->vr_cdata.vr_txdesc[i];
1171 txd->tx_m = NULL;
1172 }
1173
1174 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1175 sc->vr_cdata.vr_tx_ring_map,
1176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1177
1178 return (0);
1179 }
1180
1181 /*
1182 * Initialize the RX descriptors and allocate mbufs for them. Note that
1183 * we arrange the descriptors in a closed ring, so that the last descriptor
1184 * points back to the first.
1185 */
1186 static int
1187 vr_rx_ring_init(struct vr_softc *sc)
1188 {
1189 struct vr_ring_data *rd;
1190 struct vr_rxdesc *rxd;
1191 bus_addr_t addr;
1192 int i;
1193
1194 sc->vr_cdata.vr_rx_cons = 0;
1195
1196 rd = &sc->vr_rdata;
1197 bzero(rd->vr_rx_ring, VR_RX_RING_SIZE);
1198 for (i = 0; i < VR_RX_RING_CNT; i++) {
1199 rxd = &sc->vr_cdata.vr_rxdesc[i];
1200 rxd->rx_m = NULL;
1201 rxd->desc = &rd->vr_rx_ring[i];
1202 if (i == VR_RX_RING_CNT - 1)
1203 addr = VR_RX_RING_ADDR(sc, 0);
1204 else
1205 addr = VR_RX_RING_ADDR(sc, i + 1);
1206 rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
1207 if (vr_newbuf(sc, i) != 0)
1208 return (ENOBUFS);
1209 }
1210
1211 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1212 sc->vr_cdata.vr_rx_ring_map,
1213 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1214
1215 return (0);
1216 }
1217
1218 static __inline void
1219 vr_discard_rxbuf(struct vr_rxdesc *rxd)
1220 {
1221 struct vr_desc *desc;
1222
1223 desc = rxd->desc;
1224 desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t)));
1225 desc->vr_status = htole32(VR_RXSTAT_OWN);
1226 }
1227
1228 /*
1229 * Initialize an RX descriptor and attach an MBUF cluster.
1230 * Note: the length fields are only 11 bits wide, which means the
1231 * largest size we can specify is 2047. This is important because
1232 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
1233 * overflow the field and make a mess.
1234 */
1235 static int
1236 vr_newbuf(struct vr_softc *sc, int idx)
1237 {
1238 struct vr_desc *desc;
1239 struct vr_rxdesc *rxd;
1240 struct mbuf *m;
1241 bus_dma_segment_t segs[1];
1242 bus_dmamap_t map;
1243 int nsegs;
1244
1245 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1246 if (m == NULL)
1247 return (ENOBUFS);
1248 m->m_len = m->m_pkthdr.len = MCLBYTES;
1249 m_adj(m, sizeof(uint64_t));
1250
1251 if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag,
1252 sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1253 m_freem(m);
1254 return (ENOBUFS);
1255 }
1256 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1257
1258 rxd = &sc->vr_cdata.vr_rxdesc[idx];
1259 if (rxd->rx_m != NULL) {
1260 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
1261 BUS_DMASYNC_POSTREAD);
1262 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap);
1263 }
1264 map = rxd->rx_dmamap;
1265 rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap;
1266 sc->vr_cdata.vr_rx_sparemap = map;
1267 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
1268 BUS_DMASYNC_PREREAD);
1269 rxd->rx_m = m;
1270 desc = rxd->desc;
1271 desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr));
1272 desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len);
1273 desc->vr_status = htole32(VR_RXSTAT_OWN);
1274
1275 return (0);
1276 }
1277
1278 #ifndef __NO_STRICT_ALIGNMENT
1279 static __inline void
1280 vr_fixup_rx(struct mbuf *m)
1281 {
1282 uint16_t *src, *dst;
1283 int i;
1284
1285 src = mtod(m, uint16_t *);
1286 dst = src - 1;
1287
1288 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1289 *dst++ = *src++;
1290
1291 m->m_data -= ETHER_ALIGN;
1292 }
1293 #endif
1294
1295 /*
1296 * A frame has been uploaded: pass the resulting mbuf chain up to
1297 * the higher level protocols.
1298 */
1299 static void
1300 vr_rxeof(struct vr_softc *sc)
1301 {
1302 struct vr_rxdesc *rxd;
1303 struct mbuf *m;
1304 struct ifnet *ifp;
1305 struct vr_desc *cur_rx;
1306 int cons, prog, total_len;
1307 uint32_t rxstat, rxctl;
1308
1309 VR_LOCK_ASSERT(sc);
1310 ifp = sc->vr_ifp;
1311 cons = sc->vr_cdata.vr_rx_cons;
1312
1313 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1314 sc->vr_cdata.vr_rx_ring_map,
1315 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1316
1317 for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) {
1318 #ifdef DEVICE_POLLING
1319 if (ifp->if_capenable & IFCAP_POLLING) {
1320 if (sc->rxcycles <= 0)
1321 break;
1322 sc->rxcycles--;
1323 }
1324 #endif
1325 cur_rx = &sc->vr_rdata.vr_rx_ring[cons];
1326 rxstat = le32toh(cur_rx->vr_status);
1327 rxctl = le32toh(cur_rx->vr_ctl);
1328 if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN)
1329 break;
1330
1331 prog++;
1332 rxd = &sc->vr_cdata.vr_rxdesc[cons];
1333 m = rxd->rx_m;
1334
1335 /*
1336 * If an error occurs, update stats, clear the
1337 * status word and leave the mbuf cluster in place:
1338 * it should simply get re-used next time this descriptor
1339 * comes up in the ring.
1340 * We don't support SG in Rx path yet, so discard
1341 * partial frame.
1342 */
1343 if ((rxstat & VR_RXSTAT_RX_OK) == 0 ||
1344 (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) !=
1345 (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) {
1346 ifp->if_ierrors++;
1347 sc->vr_stat.rx_errors++;
1348 if (rxstat & VR_RXSTAT_CRCERR)
1349 sc->vr_stat.rx_crc_errors++;
1350 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1351 sc->vr_stat.rx_alignment++;
1352 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1353 sc->vr_stat.rx_fifo_overflows++;
1354 if (rxstat & VR_RXSTAT_GIANT)
1355 sc->vr_stat.rx_giants++;
1356 if (rxstat & VR_RXSTAT_RUNT)
1357 sc->vr_stat.rx_runts++;
1358 if (rxstat & VR_RXSTAT_BUFFERR)
1359 sc->vr_stat.rx_no_buffers++;
1360 #ifdef VR_SHOW_ERRORS
1361 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
1362 __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS);
1363 #endif
1364 vr_discard_rxbuf(rxd);
1365 continue;
1366 }
1367
1368 if (vr_newbuf(sc, cons) != 0) {
1369 ifp->if_iqdrops++;
1370 sc->vr_stat.rx_errors++;
1371 sc->vr_stat.rx_no_mbufs++;
1372 vr_discard_rxbuf(rxd);
1373 continue;
1374 }
1375
1376 /*
1377 * XXX The VIA Rhine chip includes the CRC with every
1378 * received frame, and there's no way to turn this
1379 * behavior off (at least, I can't find anything in
1380 * the manual that explains how to do it) so we have
1381 * to trim off the CRC manually.
1382 */
1383 total_len = VR_RXBYTES(rxstat);
1384 total_len -= ETHER_CRC_LEN;
1385 m->m_pkthdr.len = m->m_len = total_len;
1386 #ifndef __NO_STRICT_ALIGNMENT
1387 /*
1388 * RX buffers must be 32-bit aligned.
1389 * Ignore the alignment problems on the non-strict alignment
1390 * platform. The performance hit incurred due to unaligned
1391 * accesses is much smaller than the hit produced by forcing
1392 * buffer copies all the time.
1393 */
1394 vr_fixup_rx(m);
1395 #endif
1396 m->m_pkthdr.rcvif = ifp;
1397 ifp->if_ipackets++;
1398 sc->vr_stat.rx_ok++;
1399 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
1400 (rxstat & VR_RXSTAT_FRAG) == 0 &&
1401 (rxctl & VR_RXCTL_IP) != 0) {
1402 /* Checksum is valid for non-fragmented IP packets. */
1403 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1404 if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) {
1405 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1406 if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) {
1407 m->m_pkthdr.csum_flags |=
1408 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1409 if ((rxctl & VR_RXCTL_TCPUDPOK) != 0)
1410 m->m_pkthdr.csum_data = 0xffff;
1411 }
1412 }
1413 }
1414 VR_UNLOCK(sc);
1415 (*ifp->if_input)(ifp, m);
1416 VR_LOCK(sc);
1417 }
1418
1419 if (prog > 0) {
1420 sc->vr_cdata.vr_rx_cons = cons;
1421 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1422 sc->vr_cdata.vr_rx_ring_map,
1423 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1424 }
1425 }
1426
1427 /*
1428 * A frame was downloaded to the chip. It's safe for us to clean up
1429 * the list buffers.
1430 */
1431 static void
1432 vr_txeof(struct vr_softc *sc)
1433 {
1434 struct vr_txdesc *txd;
1435 struct vr_desc *cur_tx;
1436 struct ifnet *ifp;
1437 uint32_t txctl, txstat;
1438 int cons, prod;
1439
1440 VR_LOCK_ASSERT(sc);
1441
1442 cons = sc->vr_cdata.vr_tx_cons;
1443 prod = sc->vr_cdata.vr_tx_prod;
1444 if (cons == prod)
1445 return;
1446
1447 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1448 sc->vr_cdata.vr_tx_ring_map,
1449 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1450
1451 ifp = sc->vr_ifp;
1452 /*
1453 * Go through our tx list and free mbufs for those
1454 * frames that have been transmitted.
1455 */
1456 for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) {
1457 cur_tx = &sc->vr_rdata.vr_tx_ring[cons];
1458 txctl = le32toh(cur_tx->vr_ctl);
1459 txstat = le32toh(cur_tx->vr_status);
1460 if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN)
1461 break;
1462
1463 sc->vr_cdata.vr_tx_cnt--;
1464 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1465 /* Only the first descriptor in the chain is valid. */
1466 if ((txctl & VR_TXCTL_FIRSTFRAG) == 0)
1467 continue;
1468
1469 txd = &sc->vr_cdata.vr_txdesc[cons];
1470 KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n",
1471 __func__));
1472
1473 if ((txstat & VR_TXSTAT_ERRSUM) != 0) {
1474 ifp->if_oerrors++;
1475 sc->vr_stat.tx_errors++;
1476 if ((txstat & VR_TXSTAT_ABRT) != 0) {
1477 /* Give up and restart Tx. */
1478 sc->vr_stat.tx_abort++;
1479 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
1480 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1481 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
1482 txd->tx_dmamap);
1483 m_freem(txd->tx_m);
1484 txd->tx_m = NULL;
1485 VR_INC(cons, VR_TX_RING_CNT);
1486 sc->vr_cdata.vr_tx_cons = cons;
1487 if (vr_tx_stop(sc) != 0) {
1488 device_printf(sc->vr_dev,
1489 "%s: Tx shutdown error -- "
1490 "resetting\n", __func__);
1491 sc->vr_flags |= VR_F_RESTART;
1492 return;
1493 }
1494 vr_tx_start(sc);
1495 break;
1496 }
1497 if ((sc->vr_revid < REV_ID_VT3071_A &&
1498 (txstat & VR_TXSTAT_UNDERRUN)) ||
1499 (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) {
1500 sc->vr_stat.tx_underrun++;
1501 /* Retry and restart Tx. */
1502 sc->vr_cdata.vr_tx_cnt++;
1503 sc->vr_cdata.vr_tx_cons = cons;
1504 cur_tx->vr_status = htole32(VR_TXSTAT_OWN);
1505 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1506 sc->vr_cdata.vr_tx_ring_map,
1507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1508 vr_tx_underrun(sc);
1509 return;
1510 }
1511 if ((txstat & VR_TXSTAT_DEFER) != 0) {
1512 ifp->if_collisions++;
1513 sc->vr_stat.tx_collisions++;
1514 }
1515 if ((txstat & VR_TXSTAT_LATECOLL) != 0) {
1516 ifp->if_collisions++;
1517 sc->vr_stat.tx_late_collisions++;
1518 }
1519 } else {
1520 sc->vr_stat.tx_ok++;
1521 ifp->if_opackets++;
1522 }
1523
1524 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1525 BUS_DMASYNC_POSTWRITE);
1526 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
1527 if (sc->vr_revid < REV_ID_VT3071_A) {
1528 ifp->if_collisions +=
1529 (txstat & VR_TXSTAT_COLLCNT) >> 3;
1530 sc->vr_stat.tx_collisions +=
1531 (txstat & VR_TXSTAT_COLLCNT) >> 3;
1532 } else {
1533 ifp->if_collisions += (txstat & 0x0f);
1534 sc->vr_stat.tx_collisions += (txstat & 0x0f);
1535 }
1536 m_freem(txd->tx_m);
1537 txd->tx_m = NULL;
1538 }
1539
1540 sc->vr_cdata.vr_tx_cons = cons;
1541 if (sc->vr_cdata.vr_tx_cnt == 0)
1542 sc->vr_watchdog_timer = 0;
1543 }
1544
1545 static void
1546 vr_tick(void *xsc)
1547 {
1548 struct vr_softc *sc;
1549 struct mii_data *mii;
1550
1551 sc = (struct vr_softc *)xsc;
1552
1553 VR_LOCK_ASSERT(sc);
1554
1555 if ((sc->vr_flags & VR_F_RESTART) != 0) {
1556 device_printf(sc->vr_dev, "restarting\n");
1557 sc->vr_stat.num_restart++;
1558 vr_stop(sc);
1559 vr_reset(sc);
1560 vr_init_locked(sc);
1561 sc->vr_flags &= ~VR_F_RESTART;
1562 }
1563
1564 mii = device_get_softc(sc->vr_miibus);
1565 mii_tick(mii);
1566 vr_watchdog(sc);
1567 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
1568 }
1569
1570 #ifdef DEVICE_POLLING
1571 static poll_handler_t vr_poll;
1572 static poll_handler_t vr_poll_locked;
1573
1574 static void
1575 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1576 {
1577 struct vr_softc *sc;
1578
1579 sc = ifp->if_softc;
1580
1581 VR_LOCK(sc);
1582 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1583 vr_poll_locked(ifp, cmd, count);
1584 VR_UNLOCK(sc);
1585 }
1586
1587 static void
1588 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1589 {
1590 struct vr_softc *sc;
1591
1592 sc = ifp->if_softc;
1593
1594 VR_LOCK_ASSERT(sc);
1595
1596 sc->rxcycles = count;
1597 vr_rxeof(sc);
1598 vr_txeof(sc);
1599 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1600 vr_start_locked(ifp);
1601
1602 if (cmd == POLL_AND_CHECK_STATUS) {
1603 uint16_t status;
1604
1605 /* Also check status register. */
1606 status = CSR_READ_2(sc, VR_ISR);
1607 if (status)
1608 CSR_WRITE_2(sc, VR_ISR, status);
1609
1610 if ((status & VR_INTRS) == 0)
1611 return;
1612
1613 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
1614 VR_ISR_STATSOFLOW)) != 0) {
1615 if (vr_error(sc, status) != 0)
1616 return;
1617 }
1618 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
1619 #ifdef VR_SHOW_ERRORS
1620 device_printf(sc->vr_dev, "%s: receive error : 0x%b\n",
1621 __func__, status, VR_ISR_ERR_BITS);
1622 #endif
1623 vr_rx_start(sc);
1624 }
1625 }
1626 }
1627 #endif /* DEVICE_POLLING */
1628
1629 /* Back off the transmit threshold. */
1630 static void
1631 vr_tx_underrun(struct vr_softc *sc)
1632 {
1633 int thresh;
1634
1635 device_printf(sc->vr_dev, "Tx underrun -- ");
1636 if (sc->vr_txthresh < VR_TXTHRESH_MAX) {
1637 thresh = sc->vr_txthresh;
1638 sc->vr_txthresh++;
1639 if (sc->vr_txthresh >= VR_TXTHRESH_MAX) {
1640 sc->vr_txthresh = VR_TXTHRESH_MAX;
1641 printf("using store and forward mode\n");
1642 } else
1643 printf("increasing Tx threshold(%d -> %d)\n",
1644 vr_tx_threshold_tables[thresh].value,
1645 vr_tx_threshold_tables[thresh + 1].value);
1646 } else
1647 printf("\n");
1648 sc->vr_stat.tx_underrun++;
1649 if (vr_tx_stop(sc) != 0) {
1650 device_printf(sc->vr_dev, "%s: Tx shutdown error -- "
1651 "resetting\n", __func__);
1652 sc->vr_flags |= VR_F_RESTART;
1653 return;
1654 }
1655 vr_tx_start(sc);
1656 }
1657
1658 static void
1659 vr_intr(void *arg)
1660 {
1661 struct vr_softc *sc;
1662 struct ifnet *ifp;
1663 uint16_t status;
1664
1665 sc = (struct vr_softc *)arg;
1666
1667 VR_LOCK(sc);
1668
1669 if (sc->vr_suspended != 0)
1670 goto done_locked;
1671
1672 status = CSR_READ_2(sc, VR_ISR);
1673 if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0)
1674 goto done_locked;
1675
1676 ifp = sc->vr_ifp;
1677 #ifdef DEVICE_POLLING
1678 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1679 goto done_locked;
1680 #endif
1681
1682 /* Suppress unwanted interrupts. */
1683 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1684 (sc->vr_flags & VR_F_RESTART) != 0) {
1685 CSR_WRITE_2(sc, VR_IMR, 0);
1686 CSR_WRITE_2(sc, VR_ISR, status);
1687 goto done_locked;
1688 }
1689
1690 /* Disable interrupts. */
1691 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1692
1693 for (; (status & VR_INTRS) != 0;) {
1694 CSR_WRITE_2(sc, VR_ISR, status);
1695 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
1696 VR_ISR_STATSOFLOW)) != 0) {
1697 if (vr_error(sc, status) != 0) {
1698 VR_UNLOCK(sc);
1699 return;
1700 }
1701 }
1702 vr_rxeof(sc);
1703 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
1704 #ifdef VR_SHOW_ERRORS
1705 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
1706 __func__, status, VR_ISR_ERR_BITS);
1707 #endif
1708 /* Restart Rx if RxDMA SM was stopped. */
1709 vr_rx_start(sc);
1710 }
1711 vr_txeof(sc);
1712 status = CSR_READ_2(sc, VR_ISR);
1713 }
1714
1715 /* Re-enable interrupts. */
1716 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1717
1718 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1719 vr_start_locked(ifp);
1720
1721 done_locked:
1722 VR_UNLOCK(sc);
1723 }
1724
1725 static int
1726 vr_error(struct vr_softc *sc, uint16_t status)
1727 {
1728 uint16_t pcis;
1729
1730 status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW;
1731 if ((status & VR_ISR_BUSERR) != 0) {
1732 status &= ~VR_ISR_BUSERR;
1733 sc->vr_stat.bus_errors++;
1734 /* Disable further interrupts. */
1735 CSR_WRITE_2(sc, VR_IMR, 0);
1736 pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2);
1737 device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- "
1738 "resetting\n", pcis);
1739 pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2);
1740 sc->vr_flags |= VR_F_RESTART;
1741 return (EAGAIN);
1742 }
1743 if ((status & VR_ISR_LINKSTAT2) != 0) {
1744 /* Link state change, duplex changes etc. */
1745 status &= ~VR_ISR_LINKSTAT2;
1746 }
1747 if ((status & VR_ISR_STATSOFLOW) != 0) {
1748 status &= ~VR_ISR_STATSOFLOW;
1749 if (sc->vr_revid >= REV_ID_VT6105M_A0) {
1750 /* Update MIB counters. */
1751 }
1752 }
1753
1754 if (status != 0)
1755 device_printf(sc->vr_dev,
1756 "unhandled interrupt, status = 0x%04x\n", status);
1757 return (0);
1758 }
1759
1760 /*
1761 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1762 * pointers to the fragment pointers.
1763 */
1764 static int
1765 vr_encap(struct vr_softc *sc, struct mbuf **m_head)
1766 {
1767 struct vr_txdesc *txd;
1768 struct vr_desc *desc;
1769 struct mbuf *m;
1770 bus_dma_segment_t txsegs[VR_MAXFRAGS];
1771 uint32_t csum_flags, txctl;
1772 int error, i, nsegs, prod, si;
1773 int padlen;
1774
1775 VR_LOCK_ASSERT(sc);
1776
1777 M_ASSERTPKTHDR((*m_head));
1778
1779 /*
1780 * Some VIA Rhine wants packet buffers to be longword
1781 * aligned, but very often our mbufs aren't. Rather than
1782 * waste time trying to decide when to copy and when not
1783 * to copy, just do it all the time.
1784 */
1785 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) {
1786 m = m_defrag(*m_head, M_DONTWAIT);
1787 if (m == NULL) {
1788 m_freem(*m_head);
1789 *m_head = NULL;
1790 return (ENOBUFS);
1791 }
1792 *m_head = m;
1793 }
1794
1795 /*
1796 * The Rhine chip doesn't auto-pad, so we have to make
1797 * sure to pad short frames out to the minimum frame length
1798 * ourselves.
1799 */
1800 if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) {
1801 m = *m_head;
1802 padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len;
1803 if (M_WRITABLE(m) == 0) {
1804 /* Get a writable copy. */
1805 m = m_dup(*m_head, M_DONTWAIT);
1806 m_freem(*m_head);
1807 if (m == NULL) {
1808 *m_head = NULL;
1809 return (ENOBUFS);
1810 }
1811 *m_head = m;
1812 }
1813 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1814 m = m_defrag(m, M_DONTWAIT);
1815 if (m == NULL) {
1816 m_freem(*m_head);
1817 *m_head = NULL;
1818 return (ENOBUFS);
1819 }
1820 }
1821 /*
1822 * Manually pad short frames, and zero the pad space
1823 * to avoid leaking data.
1824 */
1825 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1826 m->m_pkthdr.len += padlen;
1827 m->m_len = m->m_pkthdr.len;
1828 *m_head = m;
1829 }
1830
1831 prod = sc->vr_cdata.vr_tx_prod;
1832 txd = &sc->vr_cdata.vr_txdesc[prod];
1833 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1834 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1835 if (error == EFBIG) {
1836 m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS);
1837 if (m == NULL) {
1838 m_freem(*m_head);
1839 *m_head = NULL;
1840 return (ENOBUFS);
1841 }
1842 *m_head = m;
1843 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag,
1844 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1845 if (error != 0) {
1846 m_freem(*m_head);
1847 *m_head = NULL;
1848 return (error);
1849 }
1850 } else if (error != 0)
1851 return (error);
1852 if (nsegs == 0) {
1853 m_freem(*m_head);
1854 *m_head = NULL;
1855 return (EIO);
1856 }
1857
1858 /* Check number of available descriptors. */
1859 if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) {
1860 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
1861 return (ENOBUFS);
1862 }
1863
1864 txd->tx_m = *m_head;
1865 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1866 BUS_DMASYNC_PREWRITE);
1867
1868 /* Set checksum offload. */
1869 csum_flags = 0;
1870 if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) {
1871 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1872 csum_flags |= VR_TXCTL_IPCSUM;
1873 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1874 csum_flags |= VR_TXCTL_TCPCSUM;
1875 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1876 csum_flags |= VR_TXCTL_UDPCSUM;
1877 }
1878
1879 /*
1880 * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit
1881 * is required for all descriptors regardless of single or
1882 * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for
1883 * the first descriptor for a multi-fragmented frames. Without
1884 * that VIA Rhine chip generates Tx underrun interrupts and can't
1885 * send any frames.
1886 */
1887 si = prod;
1888 for (i = 0; i < nsegs; i++) {
1889 desc = &sc->vr_rdata.vr_tx_ring[prod];
1890 desc->vr_status = 0;
1891 txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags;
1892 if (i == 0)
1893 txctl |= VR_TXCTL_FIRSTFRAG;
1894 desc->vr_ctl = htole32(txctl);
1895 desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr));
1896 sc->vr_cdata.vr_tx_cnt++;
1897 VR_INC(prod, VR_TX_RING_CNT);
1898 }
1899 /* Update producer index. */
1900 sc->vr_cdata.vr_tx_prod = prod;
1901
1902 prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT;
1903 desc = &sc->vr_rdata.vr_tx_ring[prod];
1904
1905 /*
1906 * Set EOP on the last desciptor and reuqest Tx completion
1907 * interrupt for every VR_TX_INTR_THRESH-th frames.
1908 */
1909 VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH);
1910 if (sc->vr_cdata.vr_tx_pkts == 0)
1911 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
1912 else
1913 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG);
1914
1915 /* Lastly turn the first descriptor ownership to hardware. */
1916 desc = &sc->vr_rdata.vr_tx_ring[si];
1917 desc->vr_status |= htole32(VR_TXSTAT_OWN);
1918
1919 /* Sync descriptors. */
1920 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1921 sc->vr_cdata.vr_tx_ring_map,
1922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1923
1924 return (0);
1925 }
1926
1927 static void
1928 vr_start(struct ifnet *ifp)
1929 {
1930 struct vr_softc *sc;
1931
1932 sc = ifp->if_softc;
1933 VR_LOCK(sc);
1934 vr_start_locked(ifp);
1935 VR_UNLOCK(sc);
1936 }
1937
1938 static void
1939 vr_start_locked(struct ifnet *ifp)
1940 {
1941 struct vr_softc *sc;
1942 struct mbuf *m_head;
1943 int enq;
1944
1945 sc = ifp->if_softc;
1946
1947 VR_LOCK_ASSERT(sc);
1948
1949 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1950 IFF_DRV_RUNNING || sc->vr_link == 0)
1951 return;
1952
1953 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1954 sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) {
1955 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1956 if (m_head == NULL)
1957 break;
1958 /*
1959 * Pack the data into the transmit ring. If we
1960 * don't have room, set the OACTIVE flag and wait
1961 * for the NIC to drain the ring.
1962 */
1963 if (vr_encap(sc, &m_head)) {
1964 if (m_head == NULL)
1965 break;
1966 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1967 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1968 break;
1969 }
1970
1971 enq++;
1972 /*
1973 * If there's a BPF listener, bounce a copy of this frame
1974 * to him.
1975 */
1976 ETHER_BPF_MTAP(ifp, m_head);
1977 }
1978
1979 if (enq > 0) {
1980 /* Tell the chip to start transmitting. */
1981 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
1982 /* Set a timeout in case the chip goes out to lunch. */
1983 sc->vr_watchdog_timer = 5;
1984 }
1985 }
1986
1987 static void
1988 vr_init(void *xsc)
1989 {
1990 struct vr_softc *sc;
1991
1992 sc = (struct vr_softc *)xsc;
1993 VR_LOCK(sc);
1994 vr_init_locked(sc);
1995 VR_UNLOCK(sc);
1996 }
1997
1998 static void
1999 vr_init_locked(struct vr_softc *sc)
2000 {
2001 struct ifnet *ifp;
2002 struct mii_data *mii;
2003 bus_addr_t addr;
2004 int i;
2005
2006 VR_LOCK_ASSERT(sc);
2007
2008 ifp = sc->vr_ifp;
2009 mii = device_get_softc(sc->vr_miibus);
2010
2011 /* Cancel pending I/O and free all RX/TX buffers. */
2012 vr_stop(sc);
2013 vr_reset(sc);
2014
2015 /* Set our station address. */
2016 for (i = 0; i < ETHER_ADDR_LEN; i++)
2017 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]);
2018
2019 /* Set DMA size. */
2020 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
2021 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
2022
2023 /*
2024 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
2025 * so we must set both.
2026 */
2027 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
2028 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
2029
2030 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
2031 VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg);
2032
2033 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
2034 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
2035
2036 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
2037 VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg);
2038
2039 /* Init circular RX list. */
2040 if (vr_rx_ring_init(sc) != 0) {
2041 device_printf(sc->vr_dev,
2042 "initialization failed: no memory for rx buffers\n");
2043 vr_stop(sc);
2044 return;
2045 }
2046
2047 /* Init tx descriptors. */
2048 vr_tx_ring_init(sc);
2049
2050 if ((sc->vr_quirks & VR_Q_CAM) != 0) {
2051 uint8_t vcam[2] = { 0, 0 };
2052
2053 /* Disable VLAN hardware tag insertion/stripping. */
2054 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL);
2055 /* Disable VLAN hardware filtering. */
2056 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB);
2057 /* Disable all CAM entries. */
2058 vr_cam_mask(sc, VR_MCAST_CAM, 0);
2059 vr_cam_mask(sc, VR_VLAN_CAM, 0);
2060 /* Enable the first VLAN CAM. */
2061 vr_cam_data(sc, VR_VLAN_CAM, 0, vcam);
2062 vr_cam_mask(sc, VR_VLAN_CAM, 1);
2063 }
2064
2065 /*
2066 * Set up receive filter.
2067 */
2068 vr_set_filter(sc);
2069
2070 /*
2071 * Load the address of the RX ring.
2072 */
2073 addr = VR_RX_RING_ADDR(sc, 0);
2074 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
2075 /*
2076 * Load the address of the TX ring.
2077 */
2078 addr = VR_TX_RING_ADDR(sc, 0);
2079 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
2080 /* Default : full-duplex, no Tx poll. */
2081 CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL);
2082
2083 /* Set flow-control parameters for Rhine III. */
2084 if (sc->vr_revid >= REV_ID_VT6105_A0) {
2085 /* Rx buffer count available for incoming packet. */
2086 CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT);
2087 /*
2088 * Tx pause low threshold : 16 free receive buffers
2089 * Tx pause XON high threshold : 48 free receive buffers
2090 */
2091 CSR_WRITE_1(sc, VR_FLOWCR1,
2092 VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF);
2093 /* Set Tx pause timer. */
2094 CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff);
2095 }
2096
2097 /* Enable receiver and transmitter. */
2098 CSR_WRITE_1(sc, VR_CR0,
2099 VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO);
2100
2101 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
2102 #ifdef DEVICE_POLLING
2103 /*
2104 * Disable interrupts if we are polling.
2105 */
2106 if (ifp->if_capenable & IFCAP_POLLING)
2107 CSR_WRITE_2(sc, VR_IMR, 0);
2108 else
2109 #endif
2110 /*
2111 * Enable interrupts and disable MII intrs.
2112 */
2113 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
2114 if (sc->vr_revid > REV_ID_VT6102_A)
2115 CSR_WRITE_2(sc, VR_MII_IMR, 0);
2116
2117 sc->vr_link = 0;
2118 mii_mediachg(mii);
2119
2120 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2121 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2122
2123 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
2124 }
2125
2126 /*
2127 * Set media options.
2128 */
2129 static int
2130 vr_ifmedia_upd(struct ifnet *ifp)
2131 {
2132 struct vr_softc *sc;
2133 struct mii_data *mii;
2134 struct mii_softc *miisc;
2135 int error;
2136
2137 sc = ifp->if_softc;
2138 VR_LOCK(sc);
2139 mii = device_get_softc(sc->vr_miibus);
2140 if (mii->mii_instance) {
2141 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2142 mii_phy_reset(miisc);
2143 }
2144 error = mii_mediachg(mii);
2145 VR_UNLOCK(sc);
2146
2147 return (error);
2148 }
2149
2150 /*
2151 * Report current media status.
2152 */
2153 static void
2154 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2155 {
2156 struct vr_softc *sc;
2157 struct mii_data *mii;
2158
2159 sc = ifp->if_softc;
2160 mii = device_get_softc(sc->vr_miibus);
2161 VR_LOCK(sc);
2162 mii_pollstat(mii);
2163 VR_UNLOCK(sc);
2164 ifmr->ifm_active = mii->mii_media_active;
2165 ifmr->ifm_status = mii->mii_media_status;
2166 }
2167
2168 static int
2169 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2170 {
2171 struct vr_softc *sc;
2172 struct ifreq *ifr;
2173 struct mii_data *mii;
2174 int error, mask;
2175
2176 sc = ifp->if_softc;
2177 ifr = (struct ifreq *)data;
2178 error = 0;
2179
2180 switch (command) {
2181 case SIOCSIFFLAGS:
2182 VR_LOCK(sc);
2183 if (ifp->if_flags & IFF_UP) {
2184 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2185 if ((ifp->if_flags ^ sc->vr_if_flags) &
2186 (IFF_PROMISC | IFF_ALLMULTI))
2187 vr_set_filter(sc);
2188 } else {
2189 if (sc->vr_detach == 0)
2190 vr_init_locked(sc);
2191 }
2192 } else {
2193 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2194 vr_stop(sc);
2195 }
2196 sc->vr_if_flags = ifp->if_flags;
2197 VR_UNLOCK(sc);
2198 break;
2199 case SIOCADDMULTI:
2200 case SIOCDELMULTI:
2201 VR_LOCK(sc);
2202 vr_set_filter(sc);
2203 VR_UNLOCK(sc);
2204 break;
2205 case SIOCGIFMEDIA:
2206 case SIOCSIFMEDIA:
2207 mii = device_get_softc(sc->vr_miibus);
2208 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2209 break;
2210 case SIOCSIFCAP:
2211 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2212 #ifdef DEVICE_POLLING
2213 if (mask & IFCAP_POLLING) {
2214 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2215 error = ether_poll_register(vr_poll, ifp);
2216 if (error != 0)
2217 break;
2218 VR_LOCK(sc);
2219 /* Disable interrupts. */
2220 CSR_WRITE_2(sc, VR_IMR, 0x0000);
2221 ifp->if_capenable |= IFCAP_POLLING;
2222 VR_UNLOCK(sc);
2223 } else {
2224 error = ether_poll_deregister(ifp);
2225 /* Enable interrupts. */
2226 VR_LOCK(sc);
2227 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
2228 ifp->if_capenable &= ~IFCAP_POLLING;
2229 VR_UNLOCK(sc);
2230 }
2231 }
2232 #endif /* DEVICE_POLLING */
2233 if ((mask & IFCAP_TXCSUM) != 0 &&
2234 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
2235 ifp->if_capenable ^= IFCAP_TXCSUM;
2236 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
2237 ifp->if_hwassist |= VR_CSUM_FEATURES;
2238 else
2239 ifp->if_hwassist &= ~VR_CSUM_FEATURES;
2240 }
2241 if ((mask & IFCAP_RXCSUM) != 0 &&
2242 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
2243 ifp->if_capenable ^= IFCAP_RXCSUM;
2244 if ((mask & IFCAP_WOL_UCAST) != 0 &&
2245 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0)
2246 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2247 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2248 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2249 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2250 break;
2251 default:
2252 error = ether_ioctl(ifp, command, data);
2253 break;
2254 }
2255
2256 return (error);
2257 }
2258
2259 static void
2260 vr_watchdog(struct vr_softc *sc)
2261 {
2262 struct ifnet *ifp;
2263
2264 VR_LOCK_ASSERT(sc);
2265
2266 if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer)
2267 return;
2268
2269 ifp = sc->vr_ifp;
2270 /*
2271 * Reclaim first as we don't request interrupt for every packets.
2272 */
2273 vr_txeof(sc);
2274 if (sc->vr_cdata.vr_tx_cnt == 0)
2275 return;
2276
2277 if (sc->vr_link == 0) {
2278 if (bootverbose)
2279 if_printf(sc->vr_ifp, "watchdog timeout "
2280 "(missed link)\n");
2281 ifp->if_oerrors++;
2282 vr_init_locked(sc);
2283 return;
2284 }
2285
2286 ifp->if_oerrors++;
2287 if_printf(ifp, "watchdog timeout\n");
2288
2289 vr_stop(sc);
2290 vr_reset(sc);
2291 vr_init_locked(sc);
2292
2293 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2294 vr_start_locked(ifp);
2295 }
2296
2297 static void
2298 vr_tx_start(struct vr_softc *sc)
2299 {
2300 bus_addr_t addr;
2301 uint8_t cmd;
2302
2303 cmd = CSR_READ_1(sc, VR_CR0);
2304 if ((cmd & VR_CR0_TX_ON) == 0) {
2305 addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons);
2306 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
2307 cmd |= VR_CR0_TX_ON;
2308 CSR_WRITE_1(sc, VR_CR0, cmd);
2309 }
2310 if (sc->vr_cdata.vr_tx_cnt != 0) {
2311 sc->vr_watchdog_timer = 5;
2312 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
2313 }
2314 }
2315
2316 static void
2317 vr_rx_start(struct vr_softc *sc)
2318 {
2319 bus_addr_t addr;
2320 uint8_t cmd;
2321
2322 cmd = CSR_READ_1(sc, VR_CR0);
2323 if ((cmd & VR_CR0_RX_ON) == 0) {
2324 addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons);
2325 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
2326 cmd |= VR_CR0_RX_ON;
2327 CSR_WRITE_1(sc, VR_CR0, cmd);
2328 }
2329 CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO);
2330 }
2331
2332 static int
2333 vr_tx_stop(struct vr_softc *sc)
2334 {
2335 int i;
2336 uint8_t cmd;
2337
2338 cmd = CSR_READ_1(sc, VR_CR0);
2339 if ((cmd & VR_CR0_TX_ON) != 0) {
2340 cmd &= ~VR_CR0_TX_ON;
2341 CSR_WRITE_1(sc, VR_CR0, cmd);
2342 for (i = VR_TIMEOUT; i > 0; i--) {
2343 DELAY(5);
2344 cmd = CSR_READ_1(sc, VR_CR0);
2345 if ((cmd & VR_CR0_TX_ON) == 0)
2346 break;
2347 }
2348 if (i == 0)
2349 return (ETIMEDOUT);
2350 }
2351 return (0);
2352 }
2353
2354 static int
2355 vr_rx_stop(struct vr_softc *sc)
2356 {
2357 int i;
2358 uint8_t cmd;
2359
2360 cmd = CSR_READ_1(sc, VR_CR0);
2361 if ((cmd & VR_CR0_RX_ON) != 0) {
2362 cmd &= ~VR_CR0_RX_ON;
2363 CSR_WRITE_1(sc, VR_CR0, cmd);
2364 for (i = VR_TIMEOUT; i > 0; i--) {
2365 DELAY(5);
2366 cmd = CSR_READ_1(sc, VR_CR0);
2367 if ((cmd & VR_CR0_RX_ON) == 0)
2368 break;
2369 }
2370 if (i == 0)
2371 return (ETIMEDOUT);
2372 }
2373 return (0);
2374 }
2375
2376 /*
2377 * Stop the adapter and free any mbufs allocated to the
2378 * RX and TX lists.
2379 */
2380 static void
2381 vr_stop(struct vr_softc *sc)
2382 {
2383 struct vr_txdesc *txd;
2384 struct vr_rxdesc *rxd;
2385 struct ifnet *ifp;
2386 int i;
2387
2388 VR_LOCK_ASSERT(sc);
2389
2390 ifp = sc->vr_ifp;
2391 sc->vr_watchdog_timer = 0;
2392
2393 callout_stop(&sc->vr_stat_callout);
2394 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2395
2396 CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP);
2397 if (vr_rx_stop(sc) != 0)
2398 device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__);
2399 if (vr_tx_stop(sc) != 0)
2400 device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__);
2401 /* Clear pending interrupts. */
2402 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
2403 CSR_WRITE_2(sc, VR_IMR, 0x0000);
2404 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
2405 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
2406
2407 /*
2408 * Free RX and TX mbufs still in the queues.
2409 */
2410 for (i = 0; i < VR_RX_RING_CNT; i++) {
2411 rxd = &sc->vr_cdata.vr_rxdesc[i];
2412 if (rxd->rx_m != NULL) {
2413 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag,
2414 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2415 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag,
2416 rxd->rx_dmamap);
2417 m_freem(rxd->rx_m);
2418 rxd->rx_m = NULL;
2419 }
2420 }
2421 for (i = 0; i < VR_TX_RING_CNT; i++) {
2422 txd = &sc->vr_cdata.vr_txdesc[i];
2423 if (txd->tx_m != NULL) {
2424 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
2425 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2426 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
2427 txd->tx_dmamap);
2428 m_freem(txd->tx_m);
2429 txd->tx_m = NULL;
2430 }
2431 }
2432 }
2433
2434 /*
2435 * Stop all chip I/O so that the kernel's probe routines don't
2436 * get confused by errant DMAs when rebooting.
2437 */
2438 static int
2439 vr_shutdown(device_t dev)
2440 {
2441
2442 return (vr_suspend(dev));
2443 }
2444
2445 static int
2446 vr_suspend(device_t dev)
2447 {
2448 struct vr_softc *sc;
2449
2450 sc = device_get_softc(dev);
2451
2452 VR_LOCK(sc);
2453 vr_stop(sc);
2454 vr_setwol(sc);
2455 sc->vr_suspended = 1;
2456 VR_UNLOCK(sc);
2457
2458 return (0);
2459 }
2460
2461 static int
2462 vr_resume(device_t dev)
2463 {
2464 struct vr_softc *sc;
2465 struct ifnet *ifp;
2466
2467 sc = device_get_softc(dev);
2468
2469 VR_LOCK(sc);
2470 ifp = sc->vr_ifp;
2471 vr_clrwol(sc);
2472 vr_reset(sc);
2473 if (ifp->if_flags & IFF_UP)
2474 vr_init_locked(sc);
2475
2476 sc->vr_suspended = 0;
2477 VR_UNLOCK(sc);
2478
2479 return (0);
2480 }
2481
2482 static void
2483 vr_setwol(struct vr_softc *sc)
2484 {
2485 struct ifnet *ifp;
2486 int pmc;
2487 uint16_t pmstat;
2488 uint8_t v;
2489
2490 VR_LOCK_ASSERT(sc);
2491
2492 if (sc->vr_revid < REV_ID_VT6102_A ||
2493 pci_find_extcap(sc->vr_dev, PCIY_PMG, &pmc) != 0)
2494 return;
2495
2496 ifp = sc->vr_ifp;
2497
2498 /* Clear WOL configuration. */
2499 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
2500 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
2501 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
2502 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
2503 if (sc->vr_revid > REV_ID_VT6105_B0) {
2504 /* Newer Rhine III supports two additional patterns. */
2505 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
2506 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
2507 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
2508 }
2509 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2510 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST);
2511 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2512 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC);
2513 /*
2514 * It seems that multicast wakeup frames require programming pattern
2515 * registers and valid CRC as well as pattern mask for each pattern.
2516 * While it's possible to setup such a pattern it would complicate
2517 * WOL configuration so ignore multicast wakeup frames.
2518 */
2519 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2520 CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
2521 v = CSR_READ_1(sc, VR_STICKHW);
2522 CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB);
2523 CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN);
2524 }
2525
2526 /* Put hardware into sleep. */
2527 v = CSR_READ_1(sc, VR_STICKHW);
2528 v |= VR_STICKHW_DS0 | VR_STICKHW_DS1;
2529 CSR_WRITE_1(sc, VR_STICKHW, v);
2530
2531 /* Request PME if WOL is requested. */
2532 pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2);
2533 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2534 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2535 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2536 pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2537 }
2538
2539 static void
2540 vr_clrwol(struct vr_softc *sc)
2541 {
2542 uint8_t v;
2543
2544 VR_LOCK_ASSERT(sc);
2545
2546 if (sc->vr_revid < REV_ID_VT6102_A)
2547 return;
2548
2549 /* Take hardware out of sleep. */
2550 v = CSR_READ_1(sc, VR_STICKHW);
2551 v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB);
2552 CSR_WRITE_1(sc, VR_STICKHW, v);
2553
2554 /* Clear WOL configuration as WOL may interfere normal operation. */
2555 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
2556 CSR_WRITE_1(sc, VR_WOLCFG_CLR,
2557 VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR);
2558 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
2559 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
2560 if (sc->vr_revid > REV_ID_VT6105_B0) {
2561 /* Newer Rhine III supports two additional patterns. */
2562 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
2563 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
2564 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
2565 }
2566 }
2567
2568 static int
2569 vr_sysctl_stats(SYSCTL_HANDLER_ARGS)
2570 {
2571 struct vr_softc *sc;
2572 struct vr_statistics *stat;
2573 int error;
2574 int result;
2575
2576 result = -1;
2577 error = sysctl_handle_int(oidp, &result, 0, req);
2578
2579 if (error != 0 || req->newptr == NULL)
2580 return (error);
2581
2582 if (result == 1) {
2583 sc = (struct vr_softc *)arg1;
2584 stat = &sc->vr_stat;
2585
2586 printf("%s statistics:\n", device_get_nameunit(sc->vr_dev));
2587 printf("Outbound good frames : %ju\n",
2588 (uintmax_t)stat->tx_ok);
2589 printf("Inbound good frames : %ju\n",
2590 (uintmax_t)stat->rx_ok);
2591 printf("Outbound errors : %u\n", stat->tx_errors);
2592 printf("Inbound errors : %u\n", stat->rx_errors);
2593 printf("Inbound no buffers : %u\n", stat->rx_no_buffers);
2594 printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs);
2595 printf("Inbound FIFO overflows : %d\n",
2596 stat->rx_fifo_overflows);
2597 printf("Inbound CRC errors : %u\n", stat->rx_crc_errors);
2598 printf("Inbound frame alignment errors : %u\n",
2599 stat->rx_alignment);
2600 printf("Inbound giant frames : %u\n", stat->rx_giants);
2601 printf("Inbound runt frames : %u\n", stat->rx_runts);
2602 printf("Outbound aborted with excessive collisions : %u\n",
2603 stat->tx_abort);
2604 printf("Outbound collisions : %u\n", stat->tx_collisions);
2605 printf("Outbound late collisions : %u\n",
2606 stat->tx_late_collisions);
2607 printf("Outbound underrun : %u\n", stat->tx_underrun);
2608 printf("PCI bus errors : %u\n", stat->bus_errors);
2609 printf("driver restarted due to Rx/Tx shutdown failure : %u\n",
2610 stat->num_restart);
2611 }
2612
2613 return (error);
2614 }
Cache object: c91103b0dc7a2a0658aec0fcfecf7981
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