Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/vr/if_vr.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #ifdef HAVE_KERNEL_OPTION_HEADERS 64 #include "opt_device_polling.h" 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/bus.h> 70 #include <sys/endian.h> 71 #include <sys/kernel.h> 72 #include <sys/malloc.h> 73 #include <sys/mbuf.h> 74 #include <sys/module.h> 75 #include <sys/rman.h> 76 #include <sys/socket.h> 77 #include <sys/sockio.h> 78 #include <sys/sysctl.h> 79 #include <sys/taskqueue.h> 80 81 #include <net/bpf.h> 82 #include <net/if.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 95 #include <machine/bus.h> 96 97 #include <dev/vr/if_vrreg.h> 98 99 /* "device miibus" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 MODULE_DEPEND(vr, pci, 1, 1, 1); 103 MODULE_DEPEND(vr, ether, 1, 1, 1); 104 MODULE_DEPEND(vr, miibus, 1, 1, 1); 105 106 /* Define to show Rx/Tx error status. */ 107 #undef VR_SHOW_ERRORS 108 #define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 109 110 /* 111 * Various supported device vendors/types, their names & quirks. 112 */ 113 #define VR_Q_NEEDALIGN (1<<0) 114 #define VR_Q_CSUM (1<<1) 115 #define VR_Q_CAM (1<<2) 116 117 static struct vr_type { 118 u_int16_t vr_vid; 119 u_int16_t vr_did; 120 int vr_quirks; 121 char *vr_name; 122 } vr_devs[] = { 123 { VIA_VENDORID, VIA_DEVICEID_RHINE, 124 VR_Q_NEEDALIGN, 125 "VIA VT3043 Rhine I 10/100BaseTX" }, 126 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127 VR_Q_NEEDALIGN, 128 "VIA VT86C100A Rhine II 10/100BaseTX" }, 129 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130 0, 131 "VIA VT6102 Rhine II 10/100BaseTX" }, 132 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133 0, 134 "VIA VT6105 Rhine III 10/100BaseTX" }, 135 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136 VR_Q_CSUM, 137 "VIA VT6105M Rhine III 10/100BaseTX" }, 138 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139 VR_Q_NEEDALIGN, 140 "Delta Electronics Rhine II 10/100BaseTX" }, 141 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142 VR_Q_NEEDALIGN, 143 "Addtron Technology Rhine II 10/100BaseTX" }, 144 { 0, 0, 0, NULL } 145 }; 146 147 static int vr_probe(device_t); 148 static int vr_attach(device_t); 149 static int vr_detach(device_t); 150 static int vr_shutdown(device_t); 151 static int vr_suspend(device_t); 152 static int vr_resume(device_t); 153 154 static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155 static int vr_dma_alloc(struct vr_softc *); 156 static void vr_dma_free(struct vr_softc *); 157 static __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158 static int vr_newbuf(struct vr_softc *, int); 159 160 #ifndef __NO_STRICT_ALIGNMENT 161 static __inline void vr_fixup_rx(struct mbuf *); 162 #endif 163 static void vr_rxeof(struct vr_softc *); 164 static void vr_txeof(struct vr_softc *); 165 static void vr_tick(void *); 166 static int vr_error(struct vr_softc *, uint16_t); 167 static void vr_tx_underrun(struct vr_softc *); 168 static void vr_intr(void *); 169 static void vr_start(struct ifnet *); 170 static void vr_start_locked(struct ifnet *); 171 static int vr_encap(struct vr_softc *, struct mbuf **); 172 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 173 static void vr_init(void *); 174 static void vr_init_locked(struct vr_softc *); 175 static void vr_tx_start(struct vr_softc *); 176 static void vr_rx_start(struct vr_softc *); 177 static int vr_tx_stop(struct vr_softc *); 178 static int vr_rx_stop(struct vr_softc *); 179 static void vr_stop(struct vr_softc *); 180 static void vr_watchdog(struct vr_softc *); 181 static int vr_ifmedia_upd(struct ifnet *); 182 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 183 184 static int vr_miibus_readreg(device_t, int, int); 185 static int vr_miibus_writereg(device_t, int, int, int); 186 static void vr_miibus_statchg(device_t); 187 188 static void vr_cam_mask(struct vr_softc *, uint32_t, int); 189 static int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 190 static void vr_set_filter(struct vr_softc *); 191 static void vr_reset(const struct vr_softc *); 192 static int vr_tx_ring_init(struct vr_softc *); 193 static int vr_rx_ring_init(struct vr_softc *); 194 static void vr_setwol(struct vr_softc *); 195 static void vr_clrwol(struct vr_softc *); 196 static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 197 198 static struct vr_tx_threshold_table { 199 int tx_cfg; 200 int bcr_cfg; 201 int value; 202 } vr_tx_threshold_tables[] = { 203 { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 204 { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 205 { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 206 { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 207 { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 208 { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 209 }; 210 211 static device_method_t vr_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, vr_probe), 214 DEVMETHOD(device_attach, vr_attach), 215 DEVMETHOD(device_detach, vr_detach), 216 DEVMETHOD(device_shutdown, vr_shutdown), 217 DEVMETHOD(device_suspend, vr_suspend), 218 DEVMETHOD(device_resume, vr_resume), 219 220 /* bus interface */ 221 DEVMETHOD(bus_print_child, bus_generic_print_child), 222 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 223 224 /* MII interface */ 225 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 226 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 227 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 228 229 { NULL, NULL } 230 }; 231 232 static driver_t vr_driver = { 233 "vr", 234 vr_methods, 235 sizeof(struct vr_softc) 236 }; 237 238 static devclass_t vr_devclass; 239 240 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 241 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 242 243 static int 244 vr_miibus_readreg(device_t dev, int phy, int reg) 245 { 246 struct vr_softc *sc; 247 int i; 248 249 sc = device_get_softc(dev); 250 251 /* Set the register address. */ 252 CSR_WRITE_1(sc, VR_MIIADDR, reg); 253 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 254 255 for (i = 0; i < VR_MII_TIMEOUT; i++) { 256 DELAY(1); 257 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 258 break; 259 } 260 if (i == VR_MII_TIMEOUT) 261 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 262 263 return (CSR_READ_2(sc, VR_MIIDATA)); 264 } 265 266 static int 267 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 268 { 269 struct vr_softc *sc; 270 int i; 271 272 sc = device_get_softc(dev); 273 274 /* Set the register address and data to write. */ 275 CSR_WRITE_1(sc, VR_MIIADDR, reg); 276 CSR_WRITE_2(sc, VR_MIIDATA, data); 277 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 278 279 for (i = 0; i < VR_MII_TIMEOUT; i++) { 280 DELAY(1); 281 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 282 break; 283 } 284 if (i == VR_MII_TIMEOUT) 285 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 286 reg); 287 288 return (0); 289 } 290 291 /* 292 * In order to fiddle with the 293 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 294 * first have to put the transmit and/or receive logic in the idle state. 295 */ 296 static void 297 vr_miibus_statchg(device_t dev) 298 { 299 struct vr_softc *sc; 300 struct mii_data *mii; 301 struct ifnet *ifp; 302 int lfdx, mfdx; 303 uint8_t cr0, cr1, fc; 304 305 sc = device_get_softc(dev); 306 mii = device_get_softc(sc->vr_miibus); 307 ifp = sc->vr_ifp; 308 if (mii == NULL || ifp == NULL || 309 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 310 return; 311 312 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 313 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 314 (IFM_ACTIVE | IFM_AVALID)) { 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_10_T: 317 case IFM_100_TX: 318 sc->vr_flags |= VR_F_LINK; 319 break; 320 default: 321 break; 322 } 323 } 324 325 if ((sc->vr_flags & VR_F_LINK) != 0) { 326 cr0 = CSR_READ_1(sc, VR_CR0); 327 cr1 = CSR_READ_1(sc, VR_CR1); 328 mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 329 lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 330 if (mfdx != lfdx) { 331 if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 332 if (vr_tx_stop(sc) != 0 || 333 vr_rx_stop(sc) != 0) { 334 device_printf(sc->vr_dev, 335 "%s: Tx/Rx shutdown error -- " 336 "resetting\n", __func__); 337 sc->vr_flags |= VR_F_RESTART; 338 VR_UNLOCK(sc); 339 return; 340 } 341 } 342 if (lfdx) 343 cr1 |= VR_CR1_FULLDUPLEX; 344 else 345 cr1 &= ~VR_CR1_FULLDUPLEX; 346 CSR_WRITE_1(sc, VR_CR1, cr1); 347 } 348 fc = 0; 349 /* Configure flow-control. */ 350 if (sc->vr_revid >= REV_ID_VT6105_A0) { 351 fc = CSR_READ_1(sc, VR_FLOWCR1); 352 fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 353 if ((IFM_OPTIONS(mii->mii_media_active) & 354 IFM_ETH_RXPAUSE) != 0) 355 fc |= VR_FLOWCR1_RXPAUSE; 356 if ((IFM_OPTIONS(mii->mii_media_active) & 357 IFM_ETH_TXPAUSE) != 0) { 358 fc |= VR_FLOWCR1_TXPAUSE; 359 sc->vr_flags |= VR_F_TXPAUSE; 360 } 361 CSR_WRITE_1(sc, VR_FLOWCR1, fc); 362 } else if (sc->vr_revid >= REV_ID_VT6102_A) { 363 /* No Tx puase capability available for Rhine II. */ 364 fc = CSR_READ_1(sc, VR_MISC_CR0); 365 fc &= ~VR_MISCCR0_RXPAUSE; 366 if ((IFM_OPTIONS(mii->mii_media_active) & 367 IFM_ETH_RXPAUSE) != 0) 368 fc |= VR_MISCCR0_RXPAUSE; 369 CSR_WRITE_1(sc, VR_MISC_CR0, fc); 370 } 371 vr_rx_start(sc); 372 vr_tx_start(sc); 373 } else { 374 if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 375 device_printf(sc->vr_dev, 376 "%s: Tx/Rx shutdown error -- resetting\n", 377 __func__); 378 sc->vr_flags |= VR_F_RESTART; 379 } 380 } 381 } 382 383 384 static void 385 vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 386 { 387 388 if (type == VR_MCAST_CAM) 389 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 390 else 391 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 392 CSR_WRITE_4(sc, VR_CAMMASK, mask); 393 CSR_WRITE_1(sc, VR_CAMCTL, 0); 394 } 395 396 static int 397 vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 398 { 399 int i; 400 401 if (type == VR_MCAST_CAM) { 402 if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 403 return (EINVAL); 404 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 405 } else 406 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 407 408 /* Set CAM entry address. */ 409 CSR_WRITE_1(sc, VR_CAMADDR, idx); 410 /* Set CAM entry data. */ 411 if (type == VR_MCAST_CAM) { 412 for (i = 0; i < ETHER_ADDR_LEN; i++) 413 CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 414 } else { 415 CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 416 CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 417 } 418 DELAY(10); 419 /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 420 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 421 for (i = 0; i < VR_TIMEOUT; i++) { 422 DELAY(1); 423 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 424 break; 425 } 426 427 if (i == VR_TIMEOUT) 428 device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 429 __func__); 430 CSR_WRITE_1(sc, VR_CAMCTL, 0); 431 432 return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 433 } 434 435 /* 436 * Program the 64-bit multicast hash filter. 437 */ 438 static void 439 vr_set_filter(struct vr_softc *sc) 440 { 441 struct ifnet *ifp; 442 int h; 443 uint32_t hashes[2] = { 0, 0 }; 444 struct ifmultiaddr *ifma; 445 uint8_t rxfilt; 446 int error, mcnt; 447 uint32_t cam_mask; 448 449 VR_LOCK_ASSERT(sc); 450 451 ifp = sc->vr_ifp; 452 rxfilt = CSR_READ_1(sc, VR_RXCFG); 453 rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 454 VR_RXCFG_RX_MULTI); 455 if (ifp->if_flags & IFF_BROADCAST) 456 rxfilt |= VR_RXCFG_RX_BROAD; 457 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 458 rxfilt |= VR_RXCFG_RX_MULTI; 459 if (ifp->if_flags & IFF_PROMISC) 460 rxfilt |= VR_RXCFG_RX_PROMISC; 461 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 462 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 463 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 464 return; 465 } 466 467 /* Now program new ones. */ 468 error = 0; 469 mcnt = 0; 470 IF_ADDR_LOCK(ifp); 471 if ((sc->vr_quirks & VR_Q_CAM) != 0) { 472 /* 473 * For hardwares that have CAM capability, use 474 * 32 entries multicast perfect filter. 475 */ 476 cam_mask = 0; 477 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 478 if (ifma->ifma_addr->sa_family != AF_LINK) 479 continue; 480 error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 481 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 482 if (error != 0) { 483 cam_mask = 0; 484 break; 485 } 486 cam_mask |= 1 << mcnt; 487 mcnt++; 488 } 489 vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 490 } 491 492 if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 493 /* 494 * If there are too many multicast addresses or 495 * setting multicast CAM filter failed, use hash 496 * table based filtering. 497 */ 498 mcnt = 0; 499 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 500 if (ifma->ifma_addr->sa_family != AF_LINK) 501 continue; 502 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 503 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 504 if (h < 32) 505 hashes[0] |= (1 << h); 506 else 507 hashes[1] |= (1 << (h - 32)); 508 mcnt++; 509 } 510 } 511 IF_ADDR_UNLOCK(ifp); 512 513 if (mcnt > 0) 514 rxfilt |= VR_RXCFG_RX_MULTI; 515 516 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 517 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 518 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 519 } 520 521 static void 522 vr_reset(const struct vr_softc *sc) 523 { 524 int i; 525 526 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 527 528 CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 529 if (sc->vr_revid < REV_ID_VT6102_A) { 530 /* VT86C100A needs more delay after reset. */ 531 DELAY(100); 532 } 533 for (i = 0; i < VR_TIMEOUT; i++) { 534 DELAY(10); 535 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 536 break; 537 } 538 if (i == VR_TIMEOUT) { 539 if (sc->vr_revid < REV_ID_VT6102_A) 540 device_printf(sc->vr_dev, "reset never completed!\n"); 541 else { 542 /* Use newer force reset command. */ 543 device_printf(sc->vr_dev, 544 "Using force reset command.\n"); 545 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 546 /* 547 * Wait a little while for the chip to get its brains 548 * in order. 549 */ 550 DELAY(2000); 551 } 552 } 553 554 } 555 556 /* 557 * Probe for a VIA Rhine chip. Check the PCI vendor and device 558 * IDs against our list and return a match or NULL 559 */ 560 static struct vr_type * 561 vr_match(device_t dev) 562 { 563 struct vr_type *t = vr_devs; 564 565 for (t = vr_devs; t->vr_name != NULL; t++) 566 if ((pci_get_vendor(dev) == t->vr_vid) && 567 (pci_get_device(dev) == t->vr_did)) 568 return (t); 569 return (NULL); 570 } 571 572 /* 573 * Probe for a VIA Rhine chip. Check the PCI vendor and device 574 * IDs against our list and return a device name if we find a match. 575 */ 576 static int 577 vr_probe(device_t dev) 578 { 579 struct vr_type *t; 580 581 t = vr_match(dev); 582 if (t != NULL) { 583 device_set_desc(dev, t->vr_name); 584 return (BUS_PROBE_DEFAULT); 585 } 586 return (ENXIO); 587 } 588 589 /* 590 * Attach the interface. Allocate softc structures, do ifmedia 591 * setup and ethernet/BPF attach. 592 */ 593 static int 594 vr_attach(device_t dev) 595 { 596 struct vr_softc *sc; 597 struct ifnet *ifp; 598 struct vr_type *t; 599 uint8_t eaddr[ETHER_ADDR_LEN]; 600 int error, rid; 601 int i, phy, pmc; 602 603 sc = device_get_softc(dev); 604 sc->vr_dev = dev; 605 t = vr_match(dev); 606 KASSERT(t != NULL, ("Lost if_vr device match")); 607 sc->vr_quirks = t->vr_quirks; 608 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 609 610 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 611 MTX_DEF); 612 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 613 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 614 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 615 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 616 vr_sysctl_stats, "I", "Statistics"); 617 618 error = 0; 619 620 /* 621 * Map control/status registers. 622 */ 623 pci_enable_busmaster(dev); 624 sc->vr_revid = pci_get_revid(dev); 625 device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 626 627 sc->vr_res_id = PCIR_BAR(0); 628 sc->vr_res_type = SYS_RES_IOPORT; 629 sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 630 &sc->vr_res_id, RF_ACTIVE); 631 if (sc->vr_res == NULL) { 632 device_printf(dev, "couldn't map ports\n"); 633 error = ENXIO; 634 goto fail; 635 } 636 637 /* Allocate interrupt. */ 638 rid = 0; 639 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 640 RF_SHAREABLE | RF_ACTIVE); 641 642 if (sc->vr_irq == NULL) { 643 device_printf(dev, "couldn't map interrupt\n"); 644 error = ENXIO; 645 goto fail; 646 } 647 648 /* Allocate ifnet structure. */ 649 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 650 if (ifp == NULL) { 651 device_printf(dev, "couldn't allocate ifnet structure\n"); 652 error = ENOSPC; 653 goto fail; 654 } 655 ifp->if_softc = sc; 656 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 658 ifp->if_ioctl = vr_ioctl; 659 ifp->if_start = vr_start; 660 ifp->if_init = vr_init; 661 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 662 ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 663 IFQ_SET_READY(&ifp->if_snd); 664 665 /* Configure Tx FIFO threshold. */ 666 sc->vr_txthresh = VR_TXTHRESH_MIN; 667 if (sc->vr_revid < REV_ID_VT6105_A0) { 668 /* 669 * Use store and forward mode for Rhine I/II. 670 * Otherwise they produce a lot of Tx underruns and 671 * it would take a while to get working FIFO threshold 672 * value. 673 */ 674 sc->vr_txthresh = VR_TXTHRESH_MAX; 675 } 676 if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 677 ifp->if_hwassist = VR_CSUM_FEATURES; 678 ifp->if_capabilities |= IFCAP_HWCSUM; 679 /* 680 * To update checksum field the hardware may need to 681 * store entire frames into FIFO before transmitting. 682 */ 683 sc->vr_txthresh = VR_TXTHRESH_MAX; 684 } 685 686 if (sc->vr_revid >= REV_ID_VT6102_A && 687 pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 688 ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 689 690 /* Rhine supports oversized VLAN frame. */ 691 ifp->if_capabilities |= IFCAP_VLAN_MTU; 692 ifp->if_capenable = ifp->if_capabilities; 693 #ifdef DEVICE_POLLING 694 ifp->if_capabilities |= IFCAP_POLLING; 695 #endif 696 697 /* 698 * Windows may put the chip in suspend mode when it 699 * shuts down. Be sure to kick it in the head to wake it 700 * up again. 701 */ 702 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 703 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 704 705 /* 706 * Get station address. The way the Rhine chips work, 707 * you're not allowed to directly access the EEPROM once 708 * they've been programmed a special way. Consequently, 709 * we need to read the node address from the PAR0 and PAR1 710 * registers. 711 * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 712 * VR_CFGC and VR_CFGD such that memory mapped IO configured 713 * by driver is reset to default state. 714 */ 715 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 716 for (i = VR_TIMEOUT; i > 0; i--) { 717 DELAY(1); 718 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 719 break; 720 } 721 if (i == 0) 722 device_printf(dev, "Reloading EEPROM timeout!\n"); 723 for (i = 0; i < ETHER_ADDR_LEN; i++) 724 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 725 726 /* Reset the adapter. */ 727 vr_reset(sc); 728 /* Ack intr & disable further interrupts. */ 729 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 730 CSR_WRITE_2(sc, VR_IMR, 0); 731 if (sc->vr_revid >= REV_ID_VT6102_A) 732 CSR_WRITE_2(sc, VR_MII_IMR, 0); 733 734 if (sc->vr_revid < REV_ID_VT6102_A) { 735 pci_write_config(dev, VR_PCI_MODE2, 736 pci_read_config(dev, VR_PCI_MODE2, 1) | 737 VR_MODE2_MODE10T, 1); 738 } else { 739 /* Report error instead of retrying forever. */ 740 pci_write_config(dev, VR_PCI_MODE2, 741 pci_read_config(dev, VR_PCI_MODE2, 1) | 742 VR_MODE2_PCEROPT, 1); 743 /* Detect MII coding error. */ 744 pci_write_config(dev, VR_PCI_MODE3, 745 pci_read_config(dev, VR_PCI_MODE3, 1) | 746 VR_MODE3_MIION, 1); 747 if (sc->vr_revid >= REV_ID_VT6105_LOM && 748 sc->vr_revid < REV_ID_VT6105M_A0) 749 pci_write_config(dev, VR_PCI_MODE2, 750 pci_read_config(dev, VR_PCI_MODE2, 1) | 751 VR_MODE2_MODE10T, 1); 752 /* Enable Memory-Read-Multiple. */ 753 if (sc->vr_revid >= REV_ID_VT6107_A1 && 754 sc->vr_revid < REV_ID_VT6105M_A0) 755 pci_write_config(dev, VR_PCI_MODE2, 756 pci_read_config(dev, VR_PCI_MODE2, 1) | 757 VR_MODE2_MRDPL, 1); 758 } 759 /* Disable MII AUTOPOLL. */ 760 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 761 762 if (vr_dma_alloc(sc) != 0) { 763 error = ENXIO; 764 goto fail; 765 } 766 767 /* Do MII setup. */ 768 if (sc->vr_revid >= REV_ID_VT6105_A0) 769 phy = 1; 770 else 771 phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 772 error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 773 vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 774 sc->vr_revid >= REV_ID_VT6102_A ? MIIF_DOPAUSE : 0); 775 if (error != 0) { 776 device_printf(dev, "attaching PHYs failed\n"); 777 goto fail; 778 } 779 780 /* Call MI attach routine. */ 781 ether_ifattach(ifp, eaddr); 782 /* 783 * Tell the upper layer(s) we support long frames. 784 * Must appear after the call to ether_ifattach() because 785 * ether_ifattach() sets ifi_hdrlen to the default value. 786 */ 787 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 788 789 /* Hook interrupt last to avoid having to lock softc. */ 790 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 791 NULL, vr_intr, sc, &sc->vr_intrhand); 792 793 if (error) { 794 device_printf(dev, "couldn't set up irq\n"); 795 ether_ifdetach(ifp); 796 goto fail; 797 } 798 799 fail: 800 if (error) 801 vr_detach(dev); 802 803 return (error); 804 } 805 806 /* 807 * Shutdown hardware and free up resources. This can be called any 808 * time after the mutex has been initialized. It is called in both 809 * the error case in attach and the normal detach case so it needs 810 * to be careful about only freeing resources that have actually been 811 * allocated. 812 */ 813 static int 814 vr_detach(device_t dev) 815 { 816 struct vr_softc *sc = device_get_softc(dev); 817 struct ifnet *ifp = sc->vr_ifp; 818 819 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 820 821 #ifdef DEVICE_POLLING 822 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 823 ether_poll_deregister(ifp); 824 #endif 825 826 /* These should only be active if attach succeeded. */ 827 if (device_is_attached(dev)) { 828 VR_LOCK(sc); 829 sc->vr_flags |= VR_F_DETACHED; 830 vr_stop(sc); 831 VR_UNLOCK(sc); 832 callout_drain(&sc->vr_stat_callout); 833 ether_ifdetach(ifp); 834 } 835 if (sc->vr_miibus) 836 device_delete_child(dev, sc->vr_miibus); 837 bus_generic_detach(dev); 838 839 if (sc->vr_intrhand) 840 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 841 if (sc->vr_irq) 842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 843 if (sc->vr_res) 844 bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 845 sc->vr_res); 846 847 if (ifp) 848 if_free(ifp); 849 850 vr_dma_free(sc); 851 852 mtx_destroy(&sc->vr_mtx); 853 854 return (0); 855 } 856 857 struct vr_dmamap_arg { 858 bus_addr_t vr_busaddr; 859 }; 860 861 static void 862 vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 863 { 864 struct vr_dmamap_arg *ctx; 865 866 if (error != 0) 867 return; 868 ctx = arg; 869 ctx->vr_busaddr = segs[0].ds_addr; 870 } 871 872 static int 873 vr_dma_alloc(struct vr_softc *sc) 874 { 875 struct vr_dmamap_arg ctx; 876 struct vr_txdesc *txd; 877 struct vr_rxdesc *rxd; 878 bus_size_t tx_alignment; 879 int error, i; 880 881 /* Create parent DMA tag. */ 882 error = bus_dma_tag_create( 883 bus_get_dma_tag(sc->vr_dev), /* parent */ 884 1, 0, /* alignment, boundary */ 885 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 886 BUS_SPACE_MAXADDR, /* highaddr */ 887 NULL, NULL, /* filter, filterarg */ 888 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 889 0, /* nsegments */ 890 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 891 0, /* flags */ 892 NULL, NULL, /* lockfunc, lockarg */ 893 &sc->vr_cdata.vr_parent_tag); 894 if (error != 0) { 895 device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 896 goto fail; 897 } 898 /* Create tag for Tx ring. */ 899 error = bus_dma_tag_create( 900 sc->vr_cdata.vr_parent_tag, /* parent */ 901 VR_RING_ALIGN, 0, /* alignment, boundary */ 902 BUS_SPACE_MAXADDR, /* lowaddr */ 903 BUS_SPACE_MAXADDR, /* highaddr */ 904 NULL, NULL, /* filter, filterarg */ 905 VR_TX_RING_SIZE, /* maxsize */ 906 1, /* nsegments */ 907 VR_TX_RING_SIZE, /* maxsegsize */ 908 0, /* flags */ 909 NULL, NULL, /* lockfunc, lockarg */ 910 &sc->vr_cdata.vr_tx_ring_tag); 911 if (error != 0) { 912 device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 913 goto fail; 914 } 915 916 /* Create tag for Rx ring. */ 917 error = bus_dma_tag_create( 918 sc->vr_cdata.vr_parent_tag, /* parent */ 919 VR_RING_ALIGN, 0, /* alignment, boundary */ 920 BUS_SPACE_MAXADDR, /* lowaddr */ 921 BUS_SPACE_MAXADDR, /* highaddr */ 922 NULL, NULL, /* filter, filterarg */ 923 VR_RX_RING_SIZE, /* maxsize */ 924 1, /* nsegments */ 925 VR_RX_RING_SIZE, /* maxsegsize */ 926 0, /* flags */ 927 NULL, NULL, /* lockfunc, lockarg */ 928 &sc->vr_cdata.vr_rx_ring_tag); 929 if (error != 0) { 930 device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 931 goto fail; 932 } 933 934 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 935 tx_alignment = sizeof(uint32_t); 936 else 937 tx_alignment = 1; 938 /* Create tag for Tx buffers. */ 939 error = bus_dma_tag_create( 940 sc->vr_cdata.vr_parent_tag, /* parent */ 941 tx_alignment, 0, /* alignment, boundary */ 942 BUS_SPACE_MAXADDR, /* lowaddr */ 943 BUS_SPACE_MAXADDR, /* highaddr */ 944 NULL, NULL, /* filter, filterarg */ 945 MCLBYTES * VR_MAXFRAGS, /* maxsize */ 946 VR_MAXFRAGS, /* nsegments */ 947 MCLBYTES, /* maxsegsize */ 948 0, /* flags */ 949 NULL, NULL, /* lockfunc, lockarg */ 950 &sc->vr_cdata.vr_tx_tag); 951 if (error != 0) { 952 device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 953 goto fail; 954 } 955 956 /* Create tag for Rx buffers. */ 957 error = bus_dma_tag_create( 958 sc->vr_cdata.vr_parent_tag, /* parent */ 959 VR_RX_ALIGN, 0, /* alignment, boundary */ 960 BUS_SPACE_MAXADDR, /* lowaddr */ 961 BUS_SPACE_MAXADDR, /* highaddr */ 962 NULL, NULL, /* filter, filterarg */ 963 MCLBYTES, /* maxsize */ 964 1, /* nsegments */ 965 MCLBYTES, /* maxsegsize */ 966 0, /* flags */ 967 NULL, NULL, /* lockfunc, lockarg */ 968 &sc->vr_cdata.vr_rx_tag); 969 if (error != 0) { 970 device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 971 goto fail; 972 } 973 974 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 975 error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 976 (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 977 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 978 if (error != 0) { 979 device_printf(sc->vr_dev, 980 "failed to allocate DMA'able memory for Tx ring\n"); 981 goto fail; 982 } 983 984 ctx.vr_busaddr = 0; 985 error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 986 sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 987 VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 988 if (error != 0 || ctx.vr_busaddr == 0) { 989 device_printf(sc->vr_dev, 990 "failed to load DMA'able memory for Tx ring\n"); 991 goto fail; 992 } 993 sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 994 995 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 996 error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 997 (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 998 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 999 if (error != 0) { 1000 device_printf(sc->vr_dev, 1001 "failed to allocate DMA'able memory for Rx ring\n"); 1002 goto fail; 1003 } 1004 1005 ctx.vr_busaddr = 0; 1006 error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1007 sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1008 VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1009 if (error != 0 || ctx.vr_busaddr == 0) { 1010 device_printf(sc->vr_dev, 1011 "failed to load DMA'able memory for Rx ring\n"); 1012 goto fail; 1013 } 1014 sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1015 1016 /* Create DMA maps for Tx buffers. */ 1017 for (i = 0; i < VR_TX_RING_CNT; i++) { 1018 txd = &sc->vr_cdata.vr_txdesc[i]; 1019 txd->tx_m = NULL; 1020 txd->tx_dmamap = NULL; 1021 error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1022 &txd->tx_dmamap); 1023 if (error != 0) { 1024 device_printf(sc->vr_dev, 1025 "failed to create Tx dmamap\n"); 1026 goto fail; 1027 } 1028 } 1029 /* Create DMA maps for Rx buffers. */ 1030 if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1031 &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1032 device_printf(sc->vr_dev, 1033 "failed to create spare Rx dmamap\n"); 1034 goto fail; 1035 } 1036 for (i = 0; i < VR_RX_RING_CNT; i++) { 1037 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1038 rxd->rx_m = NULL; 1039 rxd->rx_dmamap = NULL; 1040 error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1041 &rxd->rx_dmamap); 1042 if (error != 0) { 1043 device_printf(sc->vr_dev, 1044 "failed to create Rx dmamap\n"); 1045 goto fail; 1046 } 1047 } 1048 1049 fail: 1050 return (error); 1051 } 1052 1053 static void 1054 vr_dma_free(struct vr_softc *sc) 1055 { 1056 struct vr_txdesc *txd; 1057 struct vr_rxdesc *rxd; 1058 int i; 1059 1060 /* Tx ring. */ 1061 if (sc->vr_cdata.vr_tx_ring_tag) { 1062 if (sc->vr_cdata.vr_tx_ring_map) 1063 bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1064 sc->vr_cdata.vr_tx_ring_map); 1065 if (sc->vr_cdata.vr_tx_ring_map && 1066 sc->vr_rdata.vr_tx_ring) 1067 bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1068 sc->vr_rdata.vr_tx_ring, 1069 sc->vr_cdata.vr_tx_ring_map); 1070 sc->vr_rdata.vr_tx_ring = NULL; 1071 sc->vr_cdata.vr_tx_ring_map = NULL; 1072 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1073 sc->vr_cdata.vr_tx_ring_tag = NULL; 1074 } 1075 /* Rx ring. */ 1076 if (sc->vr_cdata.vr_rx_ring_tag) { 1077 if (sc->vr_cdata.vr_rx_ring_map) 1078 bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1079 sc->vr_cdata.vr_rx_ring_map); 1080 if (sc->vr_cdata.vr_rx_ring_map && 1081 sc->vr_rdata.vr_rx_ring) 1082 bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1083 sc->vr_rdata.vr_rx_ring, 1084 sc->vr_cdata.vr_rx_ring_map); 1085 sc->vr_rdata.vr_rx_ring = NULL; 1086 sc->vr_cdata.vr_rx_ring_map = NULL; 1087 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1088 sc->vr_cdata.vr_rx_ring_tag = NULL; 1089 } 1090 /* Tx buffers. */ 1091 if (sc->vr_cdata.vr_tx_tag) { 1092 for (i = 0; i < VR_TX_RING_CNT; i++) { 1093 txd = &sc->vr_cdata.vr_txdesc[i]; 1094 if (txd->tx_dmamap) { 1095 bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1096 txd->tx_dmamap); 1097 txd->tx_dmamap = NULL; 1098 } 1099 } 1100 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1101 sc->vr_cdata.vr_tx_tag = NULL; 1102 } 1103 /* Rx buffers. */ 1104 if (sc->vr_cdata.vr_rx_tag) { 1105 for (i = 0; i < VR_RX_RING_CNT; i++) { 1106 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1107 if (rxd->rx_dmamap) { 1108 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1109 rxd->rx_dmamap); 1110 rxd->rx_dmamap = NULL; 1111 } 1112 } 1113 if (sc->vr_cdata.vr_rx_sparemap) { 1114 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1115 sc->vr_cdata.vr_rx_sparemap); 1116 sc->vr_cdata.vr_rx_sparemap = 0; 1117 } 1118 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1119 sc->vr_cdata.vr_rx_tag = NULL; 1120 } 1121 1122 if (sc->vr_cdata.vr_parent_tag) { 1123 bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1124 sc->vr_cdata.vr_parent_tag = NULL; 1125 } 1126 } 1127 1128 /* 1129 * Initialize the transmit descriptors. 1130 */ 1131 static int 1132 vr_tx_ring_init(struct vr_softc *sc) 1133 { 1134 struct vr_ring_data *rd; 1135 struct vr_txdesc *txd; 1136 bus_addr_t addr; 1137 int i; 1138 1139 sc->vr_cdata.vr_tx_prod = 0; 1140 sc->vr_cdata.vr_tx_cons = 0; 1141 sc->vr_cdata.vr_tx_cnt = 0; 1142 sc->vr_cdata.vr_tx_pkts = 0; 1143 1144 rd = &sc->vr_rdata; 1145 bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1146 for (i = 0; i < VR_TX_RING_CNT; i++) { 1147 if (i == VR_TX_RING_CNT - 1) 1148 addr = VR_TX_RING_ADDR(sc, 0); 1149 else 1150 addr = VR_TX_RING_ADDR(sc, i + 1); 1151 rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1152 txd = &sc->vr_cdata.vr_txdesc[i]; 1153 txd->tx_m = NULL; 1154 } 1155 1156 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1157 sc->vr_cdata.vr_tx_ring_map, 1158 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1159 1160 return (0); 1161 } 1162 1163 /* 1164 * Initialize the RX descriptors and allocate mbufs for them. Note that 1165 * we arrange the descriptors in a closed ring, so that the last descriptor 1166 * points back to the first. 1167 */ 1168 static int 1169 vr_rx_ring_init(struct vr_softc *sc) 1170 { 1171 struct vr_ring_data *rd; 1172 struct vr_rxdesc *rxd; 1173 bus_addr_t addr; 1174 int i; 1175 1176 sc->vr_cdata.vr_rx_cons = 0; 1177 1178 rd = &sc->vr_rdata; 1179 bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1180 for (i = 0; i < VR_RX_RING_CNT; i++) { 1181 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1182 rxd->rx_m = NULL; 1183 rxd->desc = &rd->vr_rx_ring[i]; 1184 if (i == VR_RX_RING_CNT - 1) 1185 addr = VR_RX_RING_ADDR(sc, 0); 1186 else 1187 addr = VR_RX_RING_ADDR(sc, i + 1); 1188 rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1189 if (vr_newbuf(sc, i) != 0) 1190 return (ENOBUFS); 1191 } 1192 1193 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1194 sc->vr_cdata.vr_rx_ring_map, 1195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1196 1197 return (0); 1198 } 1199 1200 static __inline void 1201 vr_discard_rxbuf(struct vr_rxdesc *rxd) 1202 { 1203 struct vr_desc *desc; 1204 1205 desc = rxd->desc; 1206 desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1207 desc->vr_status = htole32(VR_RXSTAT_OWN); 1208 } 1209 1210 /* 1211 * Initialize an RX descriptor and attach an MBUF cluster. 1212 * Note: the length fields are only 11 bits wide, which means the 1213 * largest size we can specify is 2047. This is important because 1214 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1215 * overflow the field and make a mess. 1216 */ 1217 static int 1218 vr_newbuf(struct vr_softc *sc, int idx) 1219 { 1220 struct vr_desc *desc; 1221 struct vr_rxdesc *rxd; 1222 struct mbuf *m; 1223 bus_dma_segment_t segs[1]; 1224 bus_dmamap_t map; 1225 int nsegs; 1226 1227 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1228 if (m == NULL) 1229 return (ENOBUFS); 1230 m->m_len = m->m_pkthdr.len = MCLBYTES; 1231 m_adj(m, sizeof(uint64_t)); 1232 1233 if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1234 sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1235 m_freem(m); 1236 return (ENOBUFS); 1237 } 1238 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1239 1240 rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1241 if (rxd->rx_m != NULL) { 1242 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1243 BUS_DMASYNC_POSTREAD); 1244 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1245 } 1246 map = rxd->rx_dmamap; 1247 rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1248 sc->vr_cdata.vr_rx_sparemap = map; 1249 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1250 BUS_DMASYNC_PREREAD); 1251 rxd->rx_m = m; 1252 desc = rxd->desc; 1253 desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1254 desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1255 desc->vr_status = htole32(VR_RXSTAT_OWN); 1256 1257 return (0); 1258 } 1259 1260 #ifndef __NO_STRICT_ALIGNMENT 1261 static __inline void 1262 vr_fixup_rx(struct mbuf *m) 1263 { 1264 uint16_t *src, *dst; 1265 int i; 1266 1267 src = mtod(m, uint16_t *); 1268 dst = src - 1; 1269 1270 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1271 *dst++ = *src++; 1272 1273 m->m_data -= ETHER_ALIGN; 1274 } 1275 #endif 1276 1277 /* 1278 * A frame has been uploaded: pass the resulting mbuf chain up to 1279 * the higher level protocols. 1280 */ 1281 static void 1282 vr_rxeof(struct vr_softc *sc) 1283 { 1284 struct vr_rxdesc *rxd; 1285 struct mbuf *m; 1286 struct ifnet *ifp; 1287 struct vr_desc *cur_rx; 1288 int cons, prog, total_len; 1289 uint32_t rxstat, rxctl; 1290 1291 VR_LOCK_ASSERT(sc); 1292 ifp = sc->vr_ifp; 1293 cons = sc->vr_cdata.vr_rx_cons; 1294 1295 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1296 sc->vr_cdata.vr_rx_ring_map, 1297 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1298 1299 for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1300 #ifdef DEVICE_POLLING 1301 if (ifp->if_capenable & IFCAP_POLLING) { 1302 if (sc->rxcycles <= 0) 1303 break; 1304 sc->rxcycles--; 1305 } 1306 #endif 1307 cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1308 rxstat = le32toh(cur_rx->vr_status); 1309 rxctl = le32toh(cur_rx->vr_ctl); 1310 if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1311 break; 1312 1313 prog++; 1314 rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1315 m = rxd->rx_m; 1316 1317 /* 1318 * If an error occurs, update stats, clear the 1319 * status word and leave the mbuf cluster in place: 1320 * it should simply get re-used next time this descriptor 1321 * comes up in the ring. 1322 * We don't support SG in Rx path yet, so discard 1323 * partial frame. 1324 */ 1325 if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1326 (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1327 (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 1328 ifp->if_ierrors++; 1329 sc->vr_stat.rx_errors++; 1330 if (rxstat & VR_RXSTAT_CRCERR) 1331 sc->vr_stat.rx_crc_errors++; 1332 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1333 sc->vr_stat.rx_alignment++; 1334 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1335 sc->vr_stat.rx_fifo_overflows++; 1336 if (rxstat & VR_RXSTAT_GIANT) 1337 sc->vr_stat.rx_giants++; 1338 if (rxstat & VR_RXSTAT_RUNT) 1339 sc->vr_stat.rx_runts++; 1340 if (rxstat & VR_RXSTAT_BUFFERR) 1341 sc->vr_stat.rx_no_buffers++; 1342 #ifdef VR_SHOW_ERRORS 1343 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1344 __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1345 #endif 1346 vr_discard_rxbuf(rxd); 1347 continue; 1348 } 1349 1350 if (vr_newbuf(sc, cons) != 0) { 1351 ifp->if_iqdrops++; 1352 sc->vr_stat.rx_errors++; 1353 sc->vr_stat.rx_no_mbufs++; 1354 vr_discard_rxbuf(rxd); 1355 continue; 1356 } 1357 1358 /* 1359 * XXX The VIA Rhine chip includes the CRC with every 1360 * received frame, and there's no way to turn this 1361 * behavior off (at least, I can't find anything in 1362 * the manual that explains how to do it) so we have 1363 * to trim off the CRC manually. 1364 */ 1365 total_len = VR_RXBYTES(rxstat); 1366 total_len -= ETHER_CRC_LEN; 1367 m->m_pkthdr.len = m->m_len = total_len; 1368 #ifndef __NO_STRICT_ALIGNMENT 1369 /* 1370 * RX buffers must be 32-bit aligned. 1371 * Ignore the alignment problems on the non-strict alignment 1372 * platform. The performance hit incurred due to unaligned 1373 * accesses is much smaller than the hit produced by forcing 1374 * buffer copies all the time. 1375 */ 1376 vr_fixup_rx(m); 1377 #endif 1378 m->m_pkthdr.rcvif = ifp; 1379 ifp->if_ipackets++; 1380 sc->vr_stat.rx_ok++; 1381 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1382 (rxstat & VR_RXSTAT_FRAG) == 0 && 1383 (rxctl & VR_RXCTL_IP) != 0) { 1384 /* Checksum is valid for non-fragmented IP packets. */ 1385 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1386 if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1387 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1388 if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1389 m->m_pkthdr.csum_flags |= 1390 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1391 if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1392 m->m_pkthdr.csum_data = 0xffff; 1393 } 1394 } 1395 } 1396 VR_UNLOCK(sc); 1397 (*ifp->if_input)(ifp, m); 1398 VR_LOCK(sc); 1399 } 1400 1401 if (prog > 0) { 1402 /* 1403 * Let controller know how many number of RX buffers 1404 * are posted but avoid expensive register access if 1405 * TX pause capability was not negotiated with link 1406 * partner. 1407 */ 1408 if ((sc->vr_flags & VR_F_TXPAUSE) != 0) { 1409 if (prog >= VR_RX_RING_CNT) 1410 prog = VR_RX_RING_CNT - 1; 1411 CSR_WRITE_1(sc, VR_FLOWCR0, prog); 1412 } 1413 sc->vr_cdata.vr_rx_cons = cons; 1414 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1415 sc->vr_cdata.vr_rx_ring_map, 1416 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1417 } 1418 } 1419 1420 /* 1421 * A frame was downloaded to the chip. It's safe for us to clean up 1422 * the list buffers. 1423 */ 1424 static void 1425 vr_txeof(struct vr_softc *sc) 1426 { 1427 struct vr_txdesc *txd; 1428 struct vr_desc *cur_tx; 1429 struct ifnet *ifp; 1430 uint32_t txctl, txstat; 1431 int cons, prod; 1432 1433 VR_LOCK_ASSERT(sc); 1434 1435 cons = sc->vr_cdata.vr_tx_cons; 1436 prod = sc->vr_cdata.vr_tx_prod; 1437 if (cons == prod) 1438 return; 1439 1440 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1441 sc->vr_cdata.vr_tx_ring_map, 1442 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1443 1444 ifp = sc->vr_ifp; 1445 /* 1446 * Go through our tx list and free mbufs for those 1447 * frames that have been transmitted. 1448 */ 1449 for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1450 cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1451 txctl = le32toh(cur_tx->vr_ctl); 1452 txstat = le32toh(cur_tx->vr_status); 1453 if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1454 break; 1455 1456 sc->vr_cdata.vr_tx_cnt--; 1457 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1458 /* Only the first descriptor in the chain is valid. */ 1459 if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1460 continue; 1461 1462 txd = &sc->vr_cdata.vr_txdesc[cons]; 1463 KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1464 __func__)); 1465 1466 if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1467 ifp->if_oerrors++; 1468 sc->vr_stat.tx_errors++; 1469 if ((txstat & VR_TXSTAT_ABRT) != 0) { 1470 /* Give up and restart Tx. */ 1471 sc->vr_stat.tx_abort++; 1472 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1473 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1474 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1475 txd->tx_dmamap); 1476 m_freem(txd->tx_m); 1477 txd->tx_m = NULL; 1478 VR_INC(cons, VR_TX_RING_CNT); 1479 sc->vr_cdata.vr_tx_cons = cons; 1480 if (vr_tx_stop(sc) != 0) { 1481 device_printf(sc->vr_dev, 1482 "%s: Tx shutdown error -- " 1483 "resetting\n", __func__); 1484 sc->vr_flags |= VR_F_RESTART; 1485 return; 1486 } 1487 vr_tx_start(sc); 1488 break; 1489 } 1490 if ((sc->vr_revid < REV_ID_VT3071_A && 1491 (txstat & VR_TXSTAT_UNDERRUN)) || 1492 (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1493 sc->vr_stat.tx_underrun++; 1494 /* Retry and restart Tx. */ 1495 sc->vr_cdata.vr_tx_cnt++; 1496 sc->vr_cdata.vr_tx_cons = cons; 1497 cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1498 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1499 sc->vr_cdata.vr_tx_ring_map, 1500 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1501 vr_tx_underrun(sc); 1502 return; 1503 } 1504 if ((txstat & VR_TXSTAT_DEFER) != 0) { 1505 ifp->if_collisions++; 1506 sc->vr_stat.tx_collisions++; 1507 } 1508 if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 1509 ifp->if_collisions++; 1510 sc->vr_stat.tx_late_collisions++; 1511 } 1512 } else { 1513 sc->vr_stat.tx_ok++; 1514 ifp->if_opackets++; 1515 } 1516 1517 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1518 BUS_DMASYNC_POSTWRITE); 1519 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1520 if (sc->vr_revid < REV_ID_VT3071_A) { 1521 ifp->if_collisions += 1522 (txstat & VR_TXSTAT_COLLCNT) >> 3; 1523 sc->vr_stat.tx_collisions += 1524 (txstat & VR_TXSTAT_COLLCNT) >> 3; 1525 } else { 1526 ifp->if_collisions += (txstat & 0x0f); 1527 sc->vr_stat.tx_collisions += (txstat & 0x0f); 1528 } 1529 m_freem(txd->tx_m); 1530 txd->tx_m = NULL; 1531 } 1532 1533 sc->vr_cdata.vr_tx_cons = cons; 1534 if (sc->vr_cdata.vr_tx_cnt == 0) 1535 sc->vr_watchdog_timer = 0; 1536 } 1537 1538 static void 1539 vr_tick(void *xsc) 1540 { 1541 struct vr_softc *sc; 1542 struct mii_data *mii; 1543 1544 sc = (struct vr_softc *)xsc; 1545 1546 VR_LOCK_ASSERT(sc); 1547 1548 if ((sc->vr_flags & VR_F_RESTART) != 0) { 1549 device_printf(sc->vr_dev, "restarting\n"); 1550 sc->vr_stat.num_restart++; 1551 sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1552 vr_init_locked(sc); 1553 sc->vr_flags &= ~VR_F_RESTART; 1554 } 1555 1556 mii = device_get_softc(sc->vr_miibus); 1557 mii_tick(mii); 1558 if ((sc->vr_flags & VR_F_LINK) == 0) 1559 vr_miibus_statchg(sc->vr_dev); 1560 vr_watchdog(sc); 1561 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1562 } 1563 1564 #ifdef DEVICE_POLLING 1565 static poll_handler_t vr_poll; 1566 static poll_handler_t vr_poll_locked; 1567 1568 static void 1569 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1570 { 1571 struct vr_softc *sc; 1572 1573 sc = ifp->if_softc; 1574 1575 VR_LOCK(sc); 1576 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1577 vr_poll_locked(ifp, cmd, count); 1578 VR_UNLOCK(sc); 1579 } 1580 1581 static void 1582 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1583 { 1584 struct vr_softc *sc; 1585 1586 sc = ifp->if_softc; 1587 1588 VR_LOCK_ASSERT(sc); 1589 1590 sc->rxcycles = count; 1591 vr_rxeof(sc); 1592 vr_txeof(sc); 1593 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1594 vr_start_locked(ifp); 1595 1596 if (cmd == POLL_AND_CHECK_STATUS) { 1597 uint16_t status; 1598 1599 /* Also check status register. */ 1600 status = CSR_READ_2(sc, VR_ISR); 1601 if (status) 1602 CSR_WRITE_2(sc, VR_ISR, status); 1603 1604 if ((status & VR_INTRS) == 0) 1605 return; 1606 1607 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1608 VR_ISR_STATSOFLOW)) != 0) { 1609 if (vr_error(sc, status) != 0) 1610 return; 1611 } 1612 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1613 #ifdef VR_SHOW_ERRORS 1614 device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1615 __func__, status, VR_ISR_ERR_BITS); 1616 #endif 1617 vr_rx_start(sc); 1618 } 1619 } 1620 } 1621 #endif /* DEVICE_POLLING */ 1622 1623 /* Back off the transmit threshold. */ 1624 static void 1625 vr_tx_underrun(struct vr_softc *sc) 1626 { 1627 int thresh; 1628 1629 device_printf(sc->vr_dev, "Tx underrun -- "); 1630 if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1631 thresh = sc->vr_txthresh; 1632 sc->vr_txthresh++; 1633 if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1634 sc->vr_txthresh = VR_TXTHRESH_MAX; 1635 printf("using store and forward mode\n"); 1636 } else 1637 printf("increasing Tx threshold(%d -> %d)\n", 1638 vr_tx_threshold_tables[thresh].value, 1639 vr_tx_threshold_tables[thresh + 1].value); 1640 } else 1641 printf("\n"); 1642 sc->vr_stat.tx_underrun++; 1643 if (vr_tx_stop(sc) != 0) { 1644 device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1645 "resetting\n", __func__); 1646 sc->vr_flags |= VR_F_RESTART; 1647 return; 1648 } 1649 vr_tx_start(sc); 1650 } 1651 1652 static void 1653 vr_intr(void *arg) 1654 { 1655 struct vr_softc *sc; 1656 struct ifnet *ifp; 1657 uint16_t status; 1658 1659 sc = (struct vr_softc *)arg; 1660 1661 VR_LOCK(sc); 1662 1663 if ((sc->vr_flags & VR_F_SUSPENDED) != 0) 1664 goto done_locked; 1665 1666 status = CSR_READ_2(sc, VR_ISR); 1667 if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1668 goto done_locked; 1669 1670 ifp = sc->vr_ifp; 1671 #ifdef DEVICE_POLLING 1672 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1673 goto done_locked; 1674 #endif 1675 1676 /* Suppress unwanted interrupts. */ 1677 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1678 (sc->vr_flags & VR_F_RESTART) != 0) { 1679 CSR_WRITE_2(sc, VR_IMR, 0); 1680 CSR_WRITE_2(sc, VR_ISR, status); 1681 goto done_locked; 1682 } 1683 1684 /* Disable interrupts. */ 1685 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1686 1687 for (; (status & VR_INTRS) != 0;) { 1688 CSR_WRITE_2(sc, VR_ISR, status); 1689 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1690 VR_ISR_STATSOFLOW)) != 0) { 1691 if (vr_error(sc, status) != 0) { 1692 VR_UNLOCK(sc); 1693 return; 1694 } 1695 } 1696 vr_rxeof(sc); 1697 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1698 #ifdef VR_SHOW_ERRORS 1699 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1700 __func__, status, VR_ISR_ERR_BITS); 1701 #endif 1702 /* Restart Rx if RxDMA SM was stopped. */ 1703 vr_rx_start(sc); 1704 } 1705 vr_txeof(sc); 1706 status = CSR_READ_2(sc, VR_ISR); 1707 } 1708 1709 /* Re-enable interrupts. */ 1710 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1711 1712 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1713 vr_start_locked(ifp); 1714 1715 done_locked: 1716 VR_UNLOCK(sc); 1717 } 1718 1719 static int 1720 vr_error(struct vr_softc *sc, uint16_t status) 1721 { 1722 uint16_t pcis; 1723 1724 status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1725 if ((status & VR_ISR_BUSERR) != 0) { 1726 status &= ~VR_ISR_BUSERR; 1727 sc->vr_stat.bus_errors++; 1728 /* Disable further interrupts. */ 1729 CSR_WRITE_2(sc, VR_IMR, 0); 1730 pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1731 device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1732 "resetting\n", pcis); 1733 pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1734 sc->vr_flags |= VR_F_RESTART; 1735 return (EAGAIN); 1736 } 1737 if ((status & VR_ISR_LINKSTAT2) != 0) { 1738 /* Link state change, duplex changes etc. */ 1739 status &= ~VR_ISR_LINKSTAT2; 1740 } 1741 if ((status & VR_ISR_STATSOFLOW) != 0) { 1742 status &= ~VR_ISR_STATSOFLOW; 1743 if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1744 /* Update MIB counters. */ 1745 } 1746 } 1747 1748 if (status != 0) 1749 device_printf(sc->vr_dev, 1750 "unhandled interrupt, status = 0x%04x\n", status); 1751 return (0); 1752 } 1753 1754 /* 1755 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1756 * pointers to the fragment pointers. 1757 */ 1758 static int 1759 vr_encap(struct vr_softc *sc, struct mbuf **m_head) 1760 { 1761 struct vr_txdesc *txd; 1762 struct vr_desc *desc; 1763 struct mbuf *m; 1764 bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1765 uint32_t csum_flags, txctl; 1766 int error, i, nsegs, prod, si; 1767 int padlen; 1768 1769 VR_LOCK_ASSERT(sc); 1770 1771 M_ASSERTPKTHDR((*m_head)); 1772 1773 /* 1774 * Some VIA Rhine wants packet buffers to be longword 1775 * aligned, but very often our mbufs aren't. Rather than 1776 * waste time trying to decide when to copy and when not 1777 * to copy, just do it all the time. 1778 */ 1779 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1780 m = m_defrag(*m_head, M_DONTWAIT); 1781 if (m == NULL) { 1782 m_freem(*m_head); 1783 *m_head = NULL; 1784 return (ENOBUFS); 1785 } 1786 *m_head = m; 1787 } 1788 1789 /* 1790 * The Rhine chip doesn't auto-pad, so we have to make 1791 * sure to pad short frames out to the minimum frame length 1792 * ourselves. 1793 */ 1794 if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1795 m = *m_head; 1796 padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1797 if (M_WRITABLE(m) == 0) { 1798 /* Get a writable copy. */ 1799 m = m_dup(*m_head, M_DONTWAIT); 1800 m_freem(*m_head); 1801 if (m == NULL) { 1802 *m_head = NULL; 1803 return (ENOBUFS); 1804 } 1805 *m_head = m; 1806 } 1807 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1808 m = m_defrag(m, M_DONTWAIT); 1809 if (m == NULL) { 1810 m_freem(*m_head); 1811 *m_head = NULL; 1812 return (ENOBUFS); 1813 } 1814 } 1815 /* 1816 * Manually pad short frames, and zero the pad space 1817 * to avoid leaking data. 1818 */ 1819 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1820 m->m_pkthdr.len += padlen; 1821 m->m_len = m->m_pkthdr.len; 1822 *m_head = m; 1823 } 1824 1825 prod = sc->vr_cdata.vr_tx_prod; 1826 txd = &sc->vr_cdata.vr_txdesc[prod]; 1827 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1828 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1829 if (error == EFBIG) { 1830 m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); 1831 if (m == NULL) { 1832 m_freem(*m_head); 1833 *m_head = NULL; 1834 return (ENOBUFS); 1835 } 1836 *m_head = m; 1837 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1838 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1839 if (error != 0) { 1840 m_freem(*m_head); 1841 *m_head = NULL; 1842 return (error); 1843 } 1844 } else if (error != 0) 1845 return (error); 1846 if (nsegs == 0) { 1847 m_freem(*m_head); 1848 *m_head = NULL; 1849 return (EIO); 1850 } 1851 1852 /* Check number of available descriptors. */ 1853 if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1854 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1855 return (ENOBUFS); 1856 } 1857 1858 txd->tx_m = *m_head; 1859 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1860 BUS_DMASYNC_PREWRITE); 1861 1862 /* Set checksum offload. */ 1863 csum_flags = 0; 1864 if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1865 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1866 csum_flags |= VR_TXCTL_IPCSUM; 1867 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1868 csum_flags |= VR_TXCTL_TCPCSUM; 1869 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1870 csum_flags |= VR_TXCTL_UDPCSUM; 1871 } 1872 1873 /* 1874 * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1875 * is required for all descriptors regardless of single or 1876 * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1877 * the first descriptor for a multi-fragmented frames. Without 1878 * that VIA Rhine chip generates Tx underrun interrupts and can't 1879 * send any frames. 1880 */ 1881 si = prod; 1882 for (i = 0; i < nsegs; i++) { 1883 desc = &sc->vr_rdata.vr_tx_ring[prod]; 1884 desc->vr_status = 0; 1885 txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1886 if (i == 0) 1887 txctl |= VR_TXCTL_FIRSTFRAG; 1888 desc->vr_ctl = htole32(txctl); 1889 desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1890 sc->vr_cdata.vr_tx_cnt++; 1891 VR_INC(prod, VR_TX_RING_CNT); 1892 } 1893 /* Update producer index. */ 1894 sc->vr_cdata.vr_tx_prod = prod; 1895 1896 prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1897 desc = &sc->vr_rdata.vr_tx_ring[prod]; 1898 1899 /* 1900 * Set EOP on the last desciptor and reuqest Tx completion 1901 * interrupt for every VR_TX_INTR_THRESH-th frames. 1902 */ 1903 VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1904 if (sc->vr_cdata.vr_tx_pkts == 0) 1905 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1906 else 1907 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1908 1909 /* Lastly turn the first descriptor ownership to hardware. */ 1910 desc = &sc->vr_rdata.vr_tx_ring[si]; 1911 desc->vr_status |= htole32(VR_TXSTAT_OWN); 1912 1913 /* Sync descriptors. */ 1914 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1915 sc->vr_cdata.vr_tx_ring_map, 1916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1917 1918 return (0); 1919 } 1920 1921 static void 1922 vr_start(struct ifnet *ifp) 1923 { 1924 struct vr_softc *sc; 1925 1926 sc = ifp->if_softc; 1927 VR_LOCK(sc); 1928 vr_start_locked(ifp); 1929 VR_UNLOCK(sc); 1930 } 1931 1932 static void 1933 vr_start_locked(struct ifnet *ifp) 1934 { 1935 struct vr_softc *sc; 1936 struct mbuf *m_head; 1937 int enq; 1938 1939 sc = ifp->if_softc; 1940 1941 VR_LOCK_ASSERT(sc); 1942 1943 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1944 IFF_DRV_RUNNING || (sc->vr_flags & VR_F_LINK) == 0) 1945 return; 1946 1947 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1948 sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1949 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1950 if (m_head == NULL) 1951 break; 1952 /* 1953 * Pack the data into the transmit ring. If we 1954 * don't have room, set the OACTIVE flag and wait 1955 * for the NIC to drain the ring. 1956 */ 1957 if (vr_encap(sc, &m_head)) { 1958 if (m_head == NULL) 1959 break; 1960 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1961 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1962 break; 1963 } 1964 1965 enq++; 1966 /* 1967 * If there's a BPF listener, bounce a copy of this frame 1968 * to him. 1969 */ 1970 ETHER_BPF_MTAP(ifp, m_head); 1971 } 1972 1973 if (enq > 0) { 1974 /* Tell the chip to start transmitting. */ 1975 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1976 /* Set a timeout in case the chip goes out to lunch. */ 1977 sc->vr_watchdog_timer = 5; 1978 } 1979 } 1980 1981 static void 1982 vr_init(void *xsc) 1983 { 1984 struct vr_softc *sc; 1985 1986 sc = (struct vr_softc *)xsc; 1987 VR_LOCK(sc); 1988 vr_init_locked(sc); 1989 VR_UNLOCK(sc); 1990 } 1991 1992 static void 1993 vr_init_locked(struct vr_softc *sc) 1994 { 1995 struct ifnet *ifp; 1996 struct mii_data *mii; 1997 bus_addr_t addr; 1998 int i; 1999 2000 VR_LOCK_ASSERT(sc); 2001 2002 ifp = sc->vr_ifp; 2003 mii = device_get_softc(sc->vr_miibus); 2004 2005 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2006 return; 2007 2008 /* Cancel pending I/O and free all RX/TX buffers. */ 2009 vr_stop(sc); 2010 vr_reset(sc); 2011 2012 /* Set our station address. */ 2013 for (i = 0; i < ETHER_ADDR_LEN; i++) 2014 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2015 2016 /* Set DMA size. */ 2017 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2018 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 2019 2020 /* 2021 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2022 * so we must set both. 2023 */ 2024 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2025 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2026 2027 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2028 VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2029 2030 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2031 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 2032 2033 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2034 VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 2035 2036 /* Init circular RX list. */ 2037 if (vr_rx_ring_init(sc) != 0) { 2038 device_printf(sc->vr_dev, 2039 "initialization failed: no memory for rx buffers\n"); 2040 vr_stop(sc); 2041 return; 2042 } 2043 2044 /* Init tx descriptors. */ 2045 vr_tx_ring_init(sc); 2046 2047 if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2048 uint8_t vcam[2] = { 0, 0 }; 2049 2050 /* Disable VLAN hardware tag insertion/stripping. */ 2051 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2052 /* Disable VLAN hardware filtering. */ 2053 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2054 /* Disable all CAM entries. */ 2055 vr_cam_mask(sc, VR_MCAST_CAM, 0); 2056 vr_cam_mask(sc, VR_VLAN_CAM, 0); 2057 /* Enable the first VLAN CAM. */ 2058 vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2059 vr_cam_mask(sc, VR_VLAN_CAM, 1); 2060 } 2061 2062 /* 2063 * Set up receive filter. 2064 */ 2065 vr_set_filter(sc); 2066 2067 /* 2068 * Load the address of the RX ring. 2069 */ 2070 addr = VR_RX_RING_ADDR(sc, 0); 2071 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2072 /* 2073 * Load the address of the TX ring. 2074 */ 2075 addr = VR_TX_RING_ADDR(sc, 0); 2076 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2077 /* Default : full-duplex, no Tx poll. */ 2078 CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 2079 2080 /* Set flow-control parameters for Rhine III. */ 2081 if (sc->vr_revid >= REV_ID_VT6105_A0) { 2082 /* 2083 * Configure Rx buffer count available for incoming 2084 * packet. 2085 * Even though data sheet says almost nothing about 2086 * this register, this register should be updated 2087 * whenever driver adds new RX buffers to controller. 2088 * Otherwise, XON frame is not sent to link partner 2089 * even if controller has enough RX buffers and you 2090 * would be isolated from network. 2091 * The controller is not smart enough to know number 2092 * of available RX buffers so driver have to let 2093 * controller know how many RX buffers are posted. 2094 * In other words, this register works like a residue 2095 * counter for RX buffers and should be initialized 2096 * to the number of total RX buffers - 1 before 2097 * enabling RX MAC. Note, this register is 8bits so 2098 * it effectively limits the maximum number of RX 2099 * buffer to be configured by controller is 255. 2100 */ 2101 CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1); 2102 /* 2103 * Tx pause low threshold : 8 free receive buffers 2104 * Tx pause XON high threshold : 24 free receive buffers 2105 */ 2106 CSR_WRITE_1(sc, VR_FLOWCR1, 2107 VR_FLOWCR1_TXLO8 | VR_FLOWCR1_TXHI24 | VR_FLOWCR1_XONXOFF); 2108 /* Set Tx pause timer. */ 2109 CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2110 } 2111 2112 /* Enable receiver and transmitter. */ 2113 CSR_WRITE_1(sc, VR_CR0, 2114 VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 2115 2116 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2117 #ifdef DEVICE_POLLING 2118 /* 2119 * Disable interrupts if we are polling. 2120 */ 2121 if (ifp->if_capenable & IFCAP_POLLING) 2122 CSR_WRITE_2(sc, VR_IMR, 0); 2123 else 2124 #endif 2125 /* 2126 * Enable interrupts and disable MII intrs. 2127 */ 2128 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2129 if (sc->vr_revid > REV_ID_VT6102_A) 2130 CSR_WRITE_2(sc, VR_MII_IMR, 0); 2131 2132 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2133 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2134 2135 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 2136 mii_mediachg(mii); 2137 2138 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 2139 } 2140 2141 /* 2142 * Set media options. 2143 */ 2144 static int 2145 vr_ifmedia_upd(struct ifnet *ifp) 2146 { 2147 struct vr_softc *sc; 2148 struct mii_data *mii; 2149 struct mii_softc *miisc; 2150 int error; 2151 2152 sc = ifp->if_softc; 2153 VR_LOCK(sc); 2154 mii = device_get_softc(sc->vr_miibus); 2155 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2156 mii_phy_reset(miisc); 2157 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 2158 error = mii_mediachg(mii); 2159 VR_UNLOCK(sc); 2160 2161 return (error); 2162 } 2163 2164 /* 2165 * Report current media status. 2166 */ 2167 static void 2168 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2169 { 2170 struct vr_softc *sc; 2171 struct mii_data *mii; 2172 2173 sc = ifp->if_softc; 2174 mii = device_get_softc(sc->vr_miibus); 2175 VR_LOCK(sc); 2176 if ((ifp->if_flags & IFF_UP) == 0) { 2177 VR_UNLOCK(sc); 2178 return; 2179 } 2180 mii_pollstat(mii); 2181 ifmr->ifm_active = mii->mii_media_active; 2182 ifmr->ifm_status = mii->mii_media_status; 2183 VR_UNLOCK(sc); 2184 } 2185 2186 static int 2187 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2188 { 2189 struct vr_softc *sc; 2190 struct ifreq *ifr; 2191 struct mii_data *mii; 2192 int error, mask; 2193 2194 sc = ifp->if_softc; 2195 ifr = (struct ifreq *)data; 2196 error = 0; 2197 2198 switch (command) { 2199 case SIOCSIFFLAGS: 2200 VR_LOCK(sc); 2201 if (ifp->if_flags & IFF_UP) { 2202 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2203 if ((ifp->if_flags ^ sc->vr_if_flags) & 2204 (IFF_PROMISC | IFF_ALLMULTI)) 2205 vr_set_filter(sc); 2206 } else { 2207 if ((sc->vr_flags & VR_F_DETACHED) == 0) 2208 vr_init_locked(sc); 2209 } 2210 } else { 2211 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2212 vr_stop(sc); 2213 } 2214 sc->vr_if_flags = ifp->if_flags; 2215 VR_UNLOCK(sc); 2216 break; 2217 case SIOCADDMULTI: 2218 case SIOCDELMULTI: 2219 VR_LOCK(sc); 2220 vr_set_filter(sc); 2221 VR_UNLOCK(sc); 2222 break; 2223 case SIOCGIFMEDIA: 2224 case SIOCSIFMEDIA: 2225 mii = device_get_softc(sc->vr_miibus); 2226 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2227 break; 2228 case SIOCSIFCAP: 2229 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2230 #ifdef DEVICE_POLLING 2231 if (mask & IFCAP_POLLING) { 2232 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2233 error = ether_poll_register(vr_poll, ifp); 2234 if (error != 0) 2235 break; 2236 VR_LOCK(sc); 2237 /* Disable interrupts. */ 2238 CSR_WRITE_2(sc, VR_IMR, 0x0000); 2239 ifp->if_capenable |= IFCAP_POLLING; 2240 VR_UNLOCK(sc); 2241 } else { 2242 error = ether_poll_deregister(ifp); 2243 /* Enable interrupts. */ 2244 VR_LOCK(sc); 2245 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2246 ifp->if_capenable &= ~IFCAP_POLLING; 2247 VR_UNLOCK(sc); 2248 } 2249 } 2250 #endif /* DEVICE_POLLING */ 2251 if ((mask & IFCAP_TXCSUM) != 0 && 2252 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2253 ifp->if_capenable ^= IFCAP_TXCSUM; 2254 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2255 ifp->if_hwassist |= VR_CSUM_FEATURES; 2256 else 2257 ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2258 } 2259 if ((mask & IFCAP_RXCSUM) != 0 && 2260 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2261 ifp->if_capenable ^= IFCAP_RXCSUM; 2262 if ((mask & IFCAP_WOL_UCAST) != 0 && 2263 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2264 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2265 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2266 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2267 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2268 break; 2269 default: 2270 error = ether_ioctl(ifp, command, data); 2271 break; 2272 } 2273 2274 return (error); 2275 } 2276 2277 static void 2278 vr_watchdog(struct vr_softc *sc) 2279 { 2280 struct ifnet *ifp; 2281 2282 VR_LOCK_ASSERT(sc); 2283 2284 if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2285 return; 2286 2287 ifp = sc->vr_ifp; 2288 /* 2289 * Reclaim first as we don't request interrupt for every packets. 2290 */ 2291 vr_txeof(sc); 2292 if (sc->vr_cdata.vr_tx_cnt == 0) 2293 return; 2294 2295 if ((sc->vr_flags & VR_F_LINK) == 0) { 2296 if (bootverbose) 2297 if_printf(sc->vr_ifp, "watchdog timeout " 2298 "(missed link)\n"); 2299 ifp->if_oerrors++; 2300 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2301 vr_init_locked(sc); 2302 return; 2303 } 2304 2305 ifp->if_oerrors++; 2306 if_printf(ifp, "watchdog timeout\n"); 2307 2308 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2309 vr_init_locked(sc); 2310 2311 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2312 vr_start_locked(ifp); 2313 } 2314 2315 static void 2316 vr_tx_start(struct vr_softc *sc) 2317 { 2318 bus_addr_t addr; 2319 uint8_t cmd; 2320 2321 cmd = CSR_READ_1(sc, VR_CR0); 2322 if ((cmd & VR_CR0_TX_ON) == 0) { 2323 addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2324 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2325 cmd |= VR_CR0_TX_ON; 2326 CSR_WRITE_1(sc, VR_CR0, cmd); 2327 } 2328 if (sc->vr_cdata.vr_tx_cnt != 0) { 2329 sc->vr_watchdog_timer = 5; 2330 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2331 } 2332 } 2333 2334 static void 2335 vr_rx_start(struct vr_softc *sc) 2336 { 2337 bus_addr_t addr; 2338 uint8_t cmd; 2339 2340 cmd = CSR_READ_1(sc, VR_CR0); 2341 if ((cmd & VR_CR0_RX_ON) == 0) { 2342 addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2343 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2344 cmd |= VR_CR0_RX_ON; 2345 CSR_WRITE_1(sc, VR_CR0, cmd); 2346 } 2347 CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2348 } 2349 2350 static int 2351 vr_tx_stop(struct vr_softc *sc) 2352 { 2353 int i; 2354 uint8_t cmd; 2355 2356 cmd = CSR_READ_1(sc, VR_CR0); 2357 if ((cmd & VR_CR0_TX_ON) != 0) { 2358 cmd &= ~VR_CR0_TX_ON; 2359 CSR_WRITE_1(sc, VR_CR0, cmd); 2360 for (i = VR_TIMEOUT; i > 0; i--) { 2361 DELAY(5); 2362 cmd = CSR_READ_1(sc, VR_CR0); 2363 if ((cmd & VR_CR0_TX_ON) == 0) 2364 break; 2365 } 2366 if (i == 0) 2367 return (ETIMEDOUT); 2368 } 2369 return (0); 2370 } 2371 2372 static int 2373 vr_rx_stop(struct vr_softc *sc) 2374 { 2375 int i; 2376 uint8_t cmd; 2377 2378 cmd = CSR_READ_1(sc, VR_CR0); 2379 if ((cmd & VR_CR0_RX_ON) != 0) { 2380 cmd &= ~VR_CR0_RX_ON; 2381 CSR_WRITE_1(sc, VR_CR0, cmd); 2382 for (i = VR_TIMEOUT; i > 0; i--) { 2383 DELAY(5); 2384 cmd = CSR_READ_1(sc, VR_CR0); 2385 if ((cmd & VR_CR0_RX_ON) == 0) 2386 break; 2387 } 2388 if (i == 0) 2389 return (ETIMEDOUT); 2390 } 2391 return (0); 2392 } 2393 2394 /* 2395 * Stop the adapter and free any mbufs allocated to the 2396 * RX and TX lists. 2397 */ 2398 static void 2399 vr_stop(struct vr_softc *sc) 2400 { 2401 struct vr_txdesc *txd; 2402 struct vr_rxdesc *rxd; 2403 struct ifnet *ifp; 2404 int i; 2405 2406 VR_LOCK_ASSERT(sc); 2407 2408 ifp = sc->vr_ifp; 2409 sc->vr_watchdog_timer = 0; 2410 2411 callout_stop(&sc->vr_stat_callout); 2412 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2413 2414 CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2415 if (vr_rx_stop(sc) != 0) 2416 device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2417 if (vr_tx_stop(sc) != 0) 2418 device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2419 /* Clear pending interrupts. */ 2420 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2421 CSR_WRITE_2(sc, VR_IMR, 0x0000); 2422 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 2423 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 2424 2425 /* 2426 * Free RX and TX mbufs still in the queues. 2427 */ 2428 for (i = 0; i < VR_RX_RING_CNT; i++) { 2429 rxd = &sc->vr_cdata.vr_rxdesc[i]; 2430 if (rxd->rx_m != NULL) { 2431 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2432 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2433 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2434 rxd->rx_dmamap); 2435 m_freem(rxd->rx_m); 2436 rxd->rx_m = NULL; 2437 } 2438 } 2439 for (i = 0; i < VR_TX_RING_CNT; i++) { 2440 txd = &sc->vr_cdata.vr_txdesc[i]; 2441 if (txd->tx_m != NULL) { 2442 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2443 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2444 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2445 txd->tx_dmamap); 2446 m_freem(txd->tx_m); 2447 txd->tx_m = NULL; 2448 } 2449 } 2450 } 2451 2452 /* 2453 * Stop all chip I/O so that the kernel's probe routines don't 2454 * get confused by errant DMAs when rebooting. 2455 */ 2456 static int 2457 vr_shutdown(device_t dev) 2458 { 2459 2460 return (vr_suspend(dev)); 2461 } 2462 2463 static int 2464 vr_suspend(device_t dev) 2465 { 2466 struct vr_softc *sc; 2467 2468 sc = device_get_softc(dev); 2469 2470 VR_LOCK(sc); 2471 vr_stop(sc); 2472 vr_setwol(sc); 2473 sc->vr_flags |= VR_F_SUSPENDED; 2474 VR_UNLOCK(sc); 2475 2476 return (0); 2477 } 2478 2479 static int 2480 vr_resume(device_t dev) 2481 { 2482 struct vr_softc *sc; 2483 struct ifnet *ifp; 2484 2485 sc = device_get_softc(dev); 2486 2487 VR_LOCK(sc); 2488 ifp = sc->vr_ifp; 2489 vr_clrwol(sc); 2490 vr_reset(sc); 2491 if (ifp->if_flags & IFF_UP) 2492 vr_init_locked(sc); 2493 2494 sc->vr_flags &= ~VR_F_SUSPENDED; 2495 VR_UNLOCK(sc); 2496 2497 return (0); 2498 } 2499 2500 static void 2501 vr_setwol(struct vr_softc *sc) 2502 { 2503 struct ifnet *ifp; 2504 int pmc; 2505 uint16_t pmstat; 2506 uint8_t v; 2507 2508 VR_LOCK_ASSERT(sc); 2509 2510 if (sc->vr_revid < REV_ID_VT6102_A || 2511 pci_find_extcap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2512 return; 2513 2514 ifp = sc->vr_ifp; 2515 2516 /* Clear WOL configuration. */ 2517 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2518 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2519 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2520 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2521 if (sc->vr_revid > REV_ID_VT6105_B0) { 2522 /* Newer Rhine III supports two additional patterns. */ 2523 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2524 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2525 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2526 } 2527 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2528 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2529 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2530 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2531 /* 2532 * It seems that multicast wakeup frames require programming pattern 2533 * registers and valid CRC as well as pattern mask for each pattern. 2534 * While it's possible to setup such a pattern it would complicate 2535 * WOL configuration so ignore multicast wakeup frames. 2536 */ 2537 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2538 CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2539 v = CSR_READ_1(sc, VR_STICKHW); 2540 CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2541 CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2542 } 2543 2544 /* Put hardware into sleep. */ 2545 v = CSR_READ_1(sc, VR_STICKHW); 2546 v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2547 CSR_WRITE_1(sc, VR_STICKHW, v); 2548 2549 /* Request PME if WOL is requested. */ 2550 pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2551 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2552 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2553 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2554 pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2555 } 2556 2557 static void 2558 vr_clrwol(struct vr_softc *sc) 2559 { 2560 uint8_t v; 2561 2562 VR_LOCK_ASSERT(sc); 2563 2564 if (sc->vr_revid < REV_ID_VT6102_A) 2565 return; 2566 2567 /* Take hardware out of sleep. */ 2568 v = CSR_READ_1(sc, VR_STICKHW); 2569 v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2570 CSR_WRITE_1(sc, VR_STICKHW, v); 2571 2572 /* Clear WOL configuration as WOL may interfere normal operation. */ 2573 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2574 CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2575 VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2576 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2577 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2578 if (sc->vr_revid > REV_ID_VT6105_B0) { 2579 /* Newer Rhine III supports two additional patterns. */ 2580 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2581 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2582 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2583 } 2584 } 2585 2586 static int 2587 vr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2588 { 2589 struct vr_softc *sc; 2590 struct vr_statistics *stat; 2591 int error; 2592 int result; 2593 2594 result = -1; 2595 error = sysctl_handle_int(oidp, &result, 0, req); 2596 2597 if (error != 0 || req->newptr == NULL) 2598 return (error); 2599 2600 if (result == 1) { 2601 sc = (struct vr_softc *)arg1; 2602 stat = &sc->vr_stat; 2603 2604 printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2605 printf("Outbound good frames : %ju\n", 2606 (uintmax_t)stat->tx_ok); 2607 printf("Inbound good frames : %ju\n", 2608 (uintmax_t)stat->rx_ok); 2609 printf("Outbound errors : %u\n", stat->tx_errors); 2610 printf("Inbound errors : %u\n", stat->rx_errors); 2611 printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2612 printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2613 printf("Inbound FIFO overflows : %d\n", 2614 stat->rx_fifo_overflows); 2615 printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2616 printf("Inbound frame alignment errors : %u\n", 2617 stat->rx_alignment); 2618 printf("Inbound giant frames : %u\n", stat->rx_giants); 2619 printf("Inbound runt frames : %u\n", stat->rx_runts); 2620 printf("Outbound aborted with excessive collisions : %u\n", 2621 stat->tx_abort); 2622 printf("Outbound collisions : %u\n", stat->tx_collisions); 2623 printf("Outbound late collisions : %u\n", 2624 stat->tx_late_collisions); 2625 printf("Outbound underrun : %u\n", stat->tx_underrun); 2626 printf("PCI bus errors : %u\n", stat->bus_errors); 2627 printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2628 stat->num_restart); 2629 } 2630 2631 return (error); 2632 }
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