Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/vte/if_vtereg.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _IF_VTEREG_H 33 #define _IF_VTEREG_H 34 35 /* 36 * RDC Semiconductor PCI vendor ID 37 */ 38 #define VENDORID_RDC 0x17F3 39 40 /* 41 * Vortex86 RDC R6040 FastEthernet device ID 42 */ 43 #define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */ 44 45 /* MAC control register 0 */ 46 #define VTE_MCR0 0x00 47 #define MCR0_ACCPT_ERR 0x0001 48 #define MCR0_RX_ENB 0x0002 49 #define MCR0_ACCPT_RUNT 0x0004 50 #define MCR0_ACCPT_LONG_PKT 0x0008 51 #define MCR0_ACCPT_DRIBBLE 0x0010 52 #define MCR0_PROMISC 0x0020 53 #define MCR0_BROADCAST_DIS 0x0040 54 #define MCR0_RX_EARLY_INTR 0x0080 55 #define MCR0_MULTICAST 0x0100 56 #define MCR0_FC_ENB 0x0200 57 #define MCR0_TX_ENB 0x1000 58 #define MCR0_TX_EARLY_INTR 0x4000 59 #define MCR0_FULL_DUPLEX 0x8000 60 61 /* MAC control register 1 */ 62 #define VTE_MCR1 0x04 63 #define MCR1_MAC_RESET 0x0001 64 #define MCR1_MAC_LOOPBACK 0x0002 65 #define MCR1_EXCESS_COL_RETRANS_DIS 0x0004 66 #define MCR1_AUTO_CHG_DUPLEX 0x0008 67 #define MCR1_PKT_LENGTH_1518 0x0010 68 #define MCR1_PKT_LENGTH_1522 0x0020 69 #define MCR1_PKT_LENGTH_1534 0x0030 70 #define MCR1_PKT_LENGTH_1537 0x0000 71 #define MCR1_EARLY_INTR_THRESH_1129 0x0000 72 #define MCR1_EARLY_INTR_THRESH_1257 0x0040 73 #define MCR1_EARLY_INTR_THRESH_1385 0x0080 74 #define MCR1_EARLY_INTR_THRESH_1513 0x00C0 75 #define MCR1_EXCESS_COL_RETRY_16 0x0000 76 #define MCR1_EXCESS_COL_RETRY_32 0x0100 77 #define MCR1_FC_ACTIVE 0x0200 78 #define MCR1_RX_DESC_HASH_IDX 0x4000 79 #define MCR1_RX_UNICAST_HASH 0x8000 80 81 #define MCR1_PKT_LENGTH_MASK 0x0030 82 #define MCR1_EARLY_INTR_THRESH_MASK 0x00C0 83 84 /* MAC bus control register */ 85 #define VTE_MBCR 0x08 86 #define MBCR_FIFO_XFER_LENGTH_4 0x0000 87 #define MBCR_FIFO_XFER_LENGTH_8 0x0001 88 #define MBCR_FIFO_XFER_LENGTH_16 0x0002 89 #define MBCR_FIFO_XFER_LENGTH_32 0x0003 90 #define MBCR_TX_FIFO_THRESH_16 0x0000 91 #define MBCR_TX_FIFO_THRESH_32 0x0004 92 #define MBCR_TX_FIFO_THRESH_64 0x0008 93 #define MBCR_TX_FIFO_THRESH_96 0x000C 94 #define MBCR_RX_FIFO_THRESH_8 0x0000 95 #define MBCR_RX_FIFO_THRESH_16 0x0010 96 #define MBCR_RX_FIFO_THRESH_32 0x0020 97 #define MBCR_RX_FIFO_THRESH_64 0x0030 98 #define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00 99 #define MBCR_SDRAM_BUS_REQ_TIMER_SHIFT 8 100 #define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00 101 102 /* MAC TX interrupt control register */ 103 #define VTE_MTICR 0x0C 104 #define MTICR_TX_TIMER_MASK 0x001F 105 #define MTICR_TX_BUNDLE_MASK 0x0F00 106 #define VTE_IM_TX_TIMER_DEFAULT 0x7F 107 #define VTE_IM_TX_BUNDLE_DEFAULT 15 108 109 #define VTE_IM_TIMER_MIN 0 110 #define VTE_IM_TIMER_MAX 82 111 #define VTE_IM_TIMER_MASK 0x001F 112 #define VTE_IM_TIMER_SHIFT 0 113 #define VTE_IM_BUNDLE_MIN 1 114 #define VTE_IM_BUNDLE_MAX 15 115 #define VTE_IM_BUNDLE_SHIFT 8 116 117 /* MAC RX interrupt control register */ 118 #define VTE_MRICR 0x10 119 #define MRICR_RX_TIMER_MASK 0x001F 120 #define MRICR_RX_BUNDLE_MASK 0x0F00 121 #define VTE_IM_RX_TIMER_DEFAULT 0x7F 122 #define VTE_IM_RX_BUNDLE_DEFAULT 15 123 124 /* MAC TX poll command register */ 125 #define VTE_TX_POLL 0x14 126 #define TX_POLL_START 0x0001 127 128 /* MAC RX buffer size register */ 129 #define VTE_MRBSR 0x18 130 #define VTE_MRBSR_SIZE_MASK 0x03FF 131 132 /* MAC RX descriptor control register */ 133 #define VTE_MRDCR 0x1A 134 #define VTE_MRDCR_RESIDUE_MASK 0x00FF 135 #define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00 136 #define VTE_MRDCR_RX_PAUSE_THRESH_SHIFT 8 137 138 /* MAC Last status register */ 139 #define VTE_MLSR 0x1C 140 #define MLSR_MULTICAST 0x0001 141 #define MLSR_BROADCAST 0x0002 142 #define MLSR_CRC_ERR 0x0004 143 #define MLSR_RUNT 0x0008 144 #define MLSR_LONG_PKT 0x0010 145 #define MLSR_TRUNC 0x0020 146 #define MLSR_DRIBBLE 0x0040 147 #define MLSR_PHY_ERR 0x0080 148 #define MLSR_TX_FIFO_UNDERRUN 0x0200 149 #define MLSR_RX_DESC_UNAVAIL 0x0400 150 #define MLSR_TX_EXCESS_COL 0x2000 151 #define MLSR_TX_LATE_COL 0x4000 152 #define MLSR_RX_FIFO_OVERRUN 0x8000 153 154 /* MAC MDIO control register */ 155 #define VTE_MMDIO 0x20 156 #define MMDIO_REG_ADDR_MASK 0x001F 157 #define MMDIO_PHY_ADDR_MASK 0x1F00 158 #define MMDIO_READ 0x2000 159 #define MMDIO_WRITE 0x4000 160 #define MMDIO_REG_ADDR_SHIFT 0 161 #define MMDIO_PHY_ADDR_SHIFT 8 162 163 /* MAC MDIO read data register */ 164 #define VTE_MMRD 0x24 165 #define MMRD_DATA_MASK 0xFFFF 166 167 /* MAC MDIO write data register */ 168 #define VTE_MMWD 0x28 169 #define MMWD_DATA_MASK 0xFFFF 170 171 /* MAC TX descriptor start address 0 */ 172 #define VTE_MTDSA0 0x2C 173 174 /* MAC TX descriptor start address 1 */ 175 #define VTE_MTDSA1 0x30 176 177 /* MAC RX descriptor start address 0 */ 178 #define VTE_MRDSA0 0x34 179 180 /* MAC RX descriptor start address 1 */ 181 #define VTE_MRDSA1 0x38 182 183 /* MAC Interrupt status register */ 184 #define VTE_MISR 0x3C 185 #define MISR_RX_DONE 0x0001 186 #define MISR_RX_DESC_UNAVAIL 0x0002 187 #define MISR_RX_FIFO_FULL 0x0004 188 #define MISR_RX_EARLY_INTR 0x0008 189 #define MISR_TX_DONE 0x0010 190 #define MISR_TX_EARLY_INTR 0x0080 191 #define MISR_EVENT_CNT_OFLOW 0x0100 192 #define MISR_PHY_MEDIA_CHG 0x0200 193 194 /* MAC Interrupt enable register */ 195 #define VTE_MIER 0x40 196 197 #define VTE_INTRS \ 198 (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | MISR_RX_FIFO_FULL | \ 199 MISR_TX_DONE | MISR_EVENT_CNT_OFLOW) 200 201 /* MAC Event counter interrupt status register */ 202 #define VTE_MECISR 0x44 203 #define MECISR_EC_RX_DONE 0x0001 204 #define MECISR_EC_MULTICAST 0x0002 205 #define MECISR_EC_BROADCAST 0x0004 206 #define MECISR_EC_CRC_ERR 0x0008 207 #define MECISR_EC_RUNT 0x0010 208 #define MESCIR_EC_LONG_PKT 0x0020 209 #define MESCIR_EC_RX_DESC_UNAVAIL 0x0080 210 #define MESCIR_EC_RX_FIFO_FULL 0x0100 211 #define MESCIR_EC_TX_DONE 0x0200 212 #define MESCIR_EC_LATE_COL 0x0400 213 #define MESCIR_EC_TX_UNDERRUN 0x0800 214 215 /* MAC Event counter interrupt enable register */ 216 #define VTE_MECIER 0x48 217 #define VTE_MECIER_INTRS \ 218 (MECISR_EC_RX_DONE | MECISR_EC_MULTICAST | MECISR_EC_BROADCAST | \ 219 MECISR_EC_CRC_ERR | MECISR_EC_RUNT | MESCIR_EC_LONG_PKT | \ 220 MESCIR_EC_RX_DESC_UNAVAIL | MESCIR_EC_RX_FIFO_FULL | \ 221 MESCIR_EC_TX_DONE | MESCIR_EC_LATE_COL | MESCIR_EC_TX_UNDERRUN) 222 223 #define VTE_CNT_RX_DONE 0x50 224 225 #define VTE_CNT_MECNT0 0x52 226 227 #define VTE_CNT_MECNT1 0x54 228 229 #define VTE_CNT_MECNT2 0x56 230 231 #define VTE_CNT_MECNT3 0x58 232 233 #define VTE_CNT_TX_DONE 0x5A 234 235 #define VTE_CNT_MECNT4 0x5C 236 237 #define VTE_CNT_PAUSE 0x5E 238 239 /* MAC Hash table register */ 240 #define VTE_MAR0 0x60 241 #define VTE_MAR1 0x62 242 #define VTE_MAR2 0x64 243 #define VTE_MAR3 0x66 244 245 /* MAC station address and multicast address register */ 246 #define VTE_MID0L 0x68 247 #define VTE_MID0M 0x6A 248 #define VTE_MID0H 0x6C 249 #define VTE_MID1L 0x70 250 #define VTE_MID1M 0x72 251 #define VTE_MID1H 0x74 252 #define VTE_MID2L 0x78 253 #define VTE_MID2M 0x7A 254 #define VTE_MID2H 0x7C 255 #define VTE_MID3L 0x80 256 #define VTE_MID3M 0x82 257 #define VTE_MID3H 0x84 258 259 #define VTE_RXFILTER_PEEFECT_BASE VTE_MID1L 260 #define VTE_RXFILT_PERFECT_CNT 3 261 262 /* MAC PHY status change configuration register */ 263 #define VTE_MPSCCR 0x88 264 #define MPSCCR_TIMER_DIVIDER_MASK 0x0007 265 #define MPSCCR_PHY_ADDR_MASK 0x1F00 266 #define MPSCCR_PHY_STS_CHG_ENB 0x8000 267 #define MPSCCR_PHY_ADDR_SHIFT 8 268 269 /* MAC PHY status register2 */ 270 #define VTE_MPSR 0x8A 271 #define MPSR_LINK_UP 0x0001 272 #define MPSR_SPEED_100 0x0002 273 #define MPSR_FULL_DUPLEX 0x0004 274 275 /* MAC Status machine(undocumented). */ 276 #define VTE_MACSM 0xAC 277 278 /* MDC Speed control register */ 279 #define VTE_MDCSC 0xB6 280 #define MDCSC_DEFAULT 0x0030 281 282 /* MAC Identifier and revision register */ 283 #define VTE_MACID_REV 0xBC 284 #define VTE_MACID_REV_MASK 0x00FF 285 #define VTE_MACID_MASK 0xFF00 286 #define VTE_MACID_REV_SHIFT 0 287 #define VTE_MACID_SHIFT 8 288 289 /* MAC Identifier register */ 290 #define VTE_MACID 0xBE 291 292 /* 293 * RX descriptor 294 * - Added one more uint16_t member to align it 4 on bytes boundary. 295 * This does not affect operation of controller since it includes 296 * next pointer address. 297 */ 298 struct vte_rx_desc { 299 uint16_t drst; 300 uint16_t drlen; 301 uint32_t drbp; 302 uint32_t drnp; 303 uint16_t hidx; 304 uint16_t rsvd2; 305 uint16_t rsvd3; 306 uint16_t __pad; /* Not actual descriptor member. */ 307 }; 308 309 #define VTE_DRST_MID_MASK 0x0003 310 #define VTE_DRST_MID_HIT 0x0004 311 #define VTE_DRST_MULTICAST_HIT 0x0008 312 #define VTE_DRST_MULTICAST 0x0010 313 #define VTE_DRST_BROADCAST 0x0020 314 #define VTE_DRST_CRC_ERR 0x0040 315 #define VTE_DRST_RUNT 0x0080 316 #define VTE_DRST_LONG 0x0100 317 #define VTE_DRST_TRUNC 0x0200 318 #define VTE_DRST_DRIBBLE 0x0400 319 #define VTE_DRST_PHY_ERR 0x0800 320 #define VTE_DRST_RX_OK 0x4000 321 #define VTE_DRST_RX_OWN 0x8000 322 323 #define VTE_RX_LEN(x) ((x) & 0x7FF) 324 325 #define VTE_RX_HIDX(x) ((x) & 0x3F) 326 327 /* 328 * TX descriptor 329 * - Added one more uint32_t member to align it on 16 bytes boundary. 330 */ 331 struct vte_tx_desc { 332 uint16_t dtst; 333 uint16_t dtlen; 334 uint32_t dtbp; 335 uint32_t dtnp; 336 uint32_t __pad; /* Not actual descriptor member. */ 337 }; 338 339 #define VTE_DTST_EXCESS_COL 0x0010 340 #define VTE_DTST_LATE_COL 0x0020 341 #define VTE_DTST_UNDERRUN 0x0040 342 #define VTE_DTST_NO_CRC 0x2000 343 #define VTE_DTST_TX_OK 0x4000 344 #define VTE_DTST_TX_OWN 0x8000 345 346 #define VTE_TX_LEN(x) ((x) & 0x7FF) 347 348 #endif /* _IF_VTEREG_H */
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