The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/vx/if_vxreg.h

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    1 /*-
    2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions are
    6  * met: 1. Redistributions of source code must retain the above copyright
    7  * notice, this list of conditions and the following disclaimer. 2. The name
    8  * of the author may not be used to endorse or promote products derived from
    9  * this software without specific prior written permission
   10  *
   11  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
   12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
   14  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   15  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   16  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
   17  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
   18  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
   19  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   20  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   21  *
   22  * $FreeBSD: head/sys/dev/vx/if_vxreg.h 339469 2018-10-20 18:32:34Z emaste $
   23  */
   24 
   25 /*
   26  * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
   27  * 3c590 family.
   28  */
   29 
   30 /*
   31  * Some global constants
   32  */
   33 
   34 #define TX_INIT_RATE            16
   35 #define TX_INIT_MAX_RATE        64
   36 #define RX_INIT_LATENCY         64
   37 #define RX_INIT_EARLY_THRESH    64
   38 #define MIN_RX_EARLY_THRESHF    16      /* not less than ether_header */
   39 #define MIN_RX_EARLY_THRESHL    4
   40 
   41 #define EEPROMSIZE      0x40
   42 #define MAX_EEPROMBUSY  1000
   43 #define VX_LAST_TAG     0xd7
   44 #define VX_MAX_BOARDS   16
   45 
   46 /*
   47  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
   48  * Offset 0xa)
   49  */
   50 #define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
   51 #define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
   52 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
   53 #define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
   54 
   55 #define EEPROM_BUSY             (1<<15)
   56 #define EEPROM_TST_MODE         (1<<14)
   57 
   58 /*
   59  * Some short functions, worth to let them be a macro
   60  */
   61 #define GO_WINDOW(x)    CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x))
   62 
   63 /**************************************************************************
   64  *                                                                        *
   65  * These define the EEPROM data structure.  They are used in the probe
   66  * function to verify the existence of the adapter after having sent
   67  * the ID_Sequence.
   68  *
   69  **************************************************************************/
   70 
   71 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
   72 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
   73 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
   74 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
   75 #define EEPROM_MFG_DATE         0x4     /* Manufacturing date */
   76 #define EEPROM_MFG_DIVSION      0x5     /* Manufacturing division */
   77 #define EEPROM_MFG_PRODUCT      0x6     /* Product code */
   78 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
   79 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
   80 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
   81 #define EEPROM_OEM_ADDR0        0xa
   82 #define EEPROM_OEM_ADDR1        0xb
   83 #define EEPROM_OEM_ADDR2        0xc
   84 #define EEPROM_SOFTINFO         0xd
   85 #define EEPROM_COMPAT           0xe
   86 #define EEPROM_SOFTINFO2        0xf
   87 #define EEPROM_CAP              0x10
   88 #define EEPROM_INT_CONFIG_0     0x12
   89 #define EEPROM_INT_CONFIG_1     0x13
   90 /* RAM Partition TX FIFO/RX FIFO */
   91 #define ICW1_RAM_PART_MASK      0x03
   92 #define ICW1_RAM_PART_35        0x00    /* 2:5 (only legal if RAM size == 000b
   93                                          * default power-up/reset */
   94 #define ICW1_RAM_PART_13        0x01    /* 1:3 (only legal if RAM size ==
   95                                          * 000b) */
   96 #define ICW1_RAM_PART_11        0x10    /* 1:1           */
   97 #define ICW1_RAM_PART_RESV      0x11    /* Reserved      */
   98 /* ISA Adapter Selection */
   99 #define ICW1_IAS_MASK           0x0c
  100 #define ICW1_IAS_DIS            0x00    /* Both mechanisms disabled (default) */
  101 #define ICW1_IAS_ISA            0x04    /* ISA contention only */
  102 #define ICW1_IAS_PNP            0x08    /* ISA Plug and Play only */
  103 #define ICW1_IAS_BOTH           0x0c    /* Both mechanisms enabled */
  104 
  105 #define EEPROM_CHECKSUM_EL3     0x17
  106 
  107 #define NO_RX_OVN_ANOMALY       (1<<5)
  108 
  109 /**************************************************************************
  110  * These are the registers for the 3Com 3c509 and their bit patterns when *
  111  * applicable.  They have been taken out the "EtherLink III Parallel      *
  112  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
  113  * from 3com.                                                             *
  114  **************************************************************************/
  115 #define VX_COMMAND              0x0e    /* Write. BASE+0x0e is always a
  116                                          * command reg. */
  117 #define VX_STATUS               0x0e    /* Read. BASE+0x0e is always status
  118                                          * reg. */
  119 #define VX_WINDOW               0x0f    /* Read. BASE+0x0f is always window
  120                                          * reg. */
  121 /*
  122  * Window 0 registers. Setup.
  123  */
  124 /* Write */
  125 #define VX_W0_EEPROM_DATA       0x0c
  126 #define VX_W0_EEPROM_COMMAND    0x0a
  127 #define VX_W0_RESOURCE_CFG      0x08
  128 #define VX_W0_ADDRESS_CFG       0x06
  129 #define VX_W0_CONFIG_CTRL       0x04
  130  /* Read */
  131 #define VX_W0_PRODUCT_ID        0x02
  132 #define VX_W0_MFG_ID            0x00
  133 
  134 /*
  135  * Window 1 registers. Operating Set.
  136  */
  137 /* Write */
  138 #define VX_W1_TX_PIO_WR_2       0x02
  139 #define VX_W1_TX_PIO_WR_1       0x00
  140 /* Read */
  141 #define VX_W1_FREE_TX           0x0c
  142 #define VX_W1_TX_STATUS         0x0b    /* byte */
  143 #define VX_W1_TIMER             0x0a    /* byte */
  144 #define VX_W1_RX_STATUS         0x08
  145 #define VX_W1_RX_PIO_RD_2       0x02
  146 #define VX_W1_RX_PIO_RD_1       0x00
  147 
  148 /*
  149  * Window 2 registers. Station Address Setup/Read
  150  */
  151 /* Read/Write */
  152 #define VX_W2_ADDR_5            0x05
  153 #define VX_W2_ADDR_4            0x04
  154 #define VX_W2_ADDR_3            0x03
  155 #define VX_W2_ADDR_2            0x02
  156 #define VX_W2_ADDR_1            0x01
  157 #define VX_W2_ADDR_0            0x00
  158 
  159 /*
  160  * Window 3 registers.  FIFO Management.
  161  */
  162 /* Read */
  163 #define VX_W3_INTERNAL_CFG      0x00
  164 #define VX_W3_RESET_OPT         0x08
  165 #define VX_W3_FREE_TX           0x0c
  166 #define VX_W3_FREE_RX           0x0a
  167 
  168 /*
  169  * Window 4 registers. Diagnostics.
  170  */
  171 /* Read/Write */
  172 #define VX_W4_MEDIA_TYPE        0x0a
  173 #define VX_W4_CTRLR_STATUS      0x08
  174 #define VX_W4_NET_DIAG          0x06
  175 #define VX_W4_FIFO_DIAG         0x04
  176 #define VX_W4_HOST_DIAG         0x02
  177 #define VX_W4_TX_DIAG           0x00
  178 
  179 /*
  180  * Window 5 Registers.  Results and Internal status.
  181  */
  182 /* Read */
  183 #define VX_W5_READ_0_MASK       0x0c
  184 #define VX_W5_INTR_MASK         0x0a
  185 #define VX_W5_RX_FILTER         0x08
  186 #define VX_W5_RX_EARLY_THRESH   0x06
  187 #define VX_W5_TX_AVAIL_THRESH   0x02
  188 #define VX_W5_TX_START_THRESH   0x00
  189 
  190 /*
  191  * Window 6 registers. Statistics.
  192  */
  193 /* Read/Write */
  194 #define TX_TOTAL_OK             0x0c
  195 #define RX_TOTAL_OK             0x0a
  196 #define TX_DEFERRALS            0x08
  197 #define RX_FRAMES_OK            0x07
  198 #define TX_FRAMES_OK            0x06
  199 #define RX_OVERRUNS             0x05
  200 #define TX_COLLISIONS           0x04
  201 #define TX_AFTER_1_COLLISION    0x03
  202 #define TX_AFTER_X_COLLISIONS   0x02
  203 #define TX_NO_SQE               0x01
  204 #define TX_CD_LOST              0x00
  205 
  206 /****************************************
  207  *
  208  * Register definitions.
  209  *
  210  ****************************************/
  211 
  212 /*
  213  * Command register. All windows.
  214  *
  215  * 16 bit register.
  216  *     15-11:  5-bit code for command to be executed.
  217  *     10-0:   11-bit arg if any. For commands with no args;
  218  *            this can be set to anything.
  219  */
  220 #define GLOBAL_RESET            (u_short) 0x0000        /* Wait at least 1ms
  221                                                          * after issuing */
  222 #define WINDOW_SELECT           (u_short) (0x1<<11)
  223 #define START_TRANSCEIVER       (u_short) (0x2<<11)     /* Read ADDR_CFG reg to
  224                                                          * determine whether
  225                                                          * this is needed. If
  226                                                          * so; wait 800 uSec
  227                                                          * before using trans-
  228                                                          * ceiver. */
  229 #define RX_DISABLE              (u_short) (0x3<<11)     /* state disabled on
  230                                                          * power-up */
  231 #define RX_ENABLE               (u_short) (0x4<<11)
  232 #define RX_RESET                (u_short) (0x5<<11)
  233 #define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
  234 #define TX_ENABLE               (u_short) (0x9<<11)
  235 #define TX_DISABLE              (u_short) (0xa<<11)
  236 #define TX_RESET                (u_short) (0xb<<11)
  237 #define REQ_INTR                (u_short) (0xc<<11)
  238 /*
  239  * The following C_* acknowledge the various interrupts.
  240  * Some of them don't do anything.  See the manual.
  241  */
  242 #define ACK_INTR                (u_short) (0x6800)
  243 #define C_INTR_LATCH            (u_short) (ACK_INTR|0x1)
  244 #define C_CARD_FAILURE          (u_short) (ACK_INTR|0x2)
  245 #define C_TX_COMPLETE           (u_short) (ACK_INTR|0x4)
  246 #define C_TX_AVAIL              (u_short) (ACK_INTR|0x8)
  247 #define C_RX_COMPLETE           (u_short) (ACK_INTR|0x10)
  248 #define C_RX_EARLY              (u_short) (ACK_INTR|0x20)
  249 #define C_INT_RQD               (u_short) (ACK_INTR|0x40)
  250 #define C_UPD_STATS             (u_short) (ACK_INTR|0x80)
  251 #define SET_INTR_MASK           (u_short) (0xe<<11)
  252 #define SET_RD_0_MASK           (u_short) (0xf<<11)
  253 #define SET_RX_FILTER           (u_short) (0x10<<11)
  254 #define FIL_INDIVIDUAL          (u_short) (0x1)
  255 #define FIL_MULTICAST           (u_short) (0x02)
  256 #define FIL_BRDCST              (u_short) (0x04)
  257 #define FIL_PROMISC             (u_short) (0x08)
  258 #define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
  259 #define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
  260 #define SET_TX_START_THRESH     (u_short) (0x13<<11)
  261 #define STATS_ENABLE            (u_short) (0x15<<11)
  262 #define STATS_DISABLE           (u_short) (0x16<<11)
  263 #define STOP_TRANSCEIVER        (u_short) (0x17<<11)
  264 
  265 /*
  266  * Status register. All windows.
  267  *
  268  *     15-13:  Window number(0-7).
  269  *     12:     Command_in_progress.
  270  *     11:     reserved.
  271  *     10:     reserved.
  272  *     9:      reserved.
  273  *     8:      reserved.
  274  *     7:      Update Statistics.
  275  *     6:      Interrupt Requested.
  276  *     5:      RX Early.
  277  *     4:      RX Complete.
  278  *     3:      TX Available.
  279  *     2:      TX Complete.
  280  *     1:      Adapter Failure.
  281  *     0:      Interrupt Latch.
  282  */
  283 #define S_INTR_LATCH            (u_short) (0x1)
  284 #define S_CARD_FAILURE          (u_short) (0x2)
  285 #define S_TX_COMPLETE           (u_short) (0x4)
  286 #define S_TX_AVAIL              (u_short) (0x8)
  287 #define S_RX_COMPLETE           (u_short) (0x10)
  288 #define S_RX_EARLY              (u_short) (0x20)
  289 #define S_INT_RQD               (u_short) (0x40)
  290 #define S_UPD_STATS             (u_short) (0x80)
  291 #define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
  292 
  293 #define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS)
  294 
  295 /* Address Config. Register.
  296  * Window 0/Port 06
  297  */
  298 
  299 #define ACF_CONNECTOR_BITS      14
  300 #define ACF_CONNECTOR_UTP       0
  301 #define ACF_CONNECTOR_AUI       1
  302 #define ACF_CONNECTOR_BNC       3
  303 
  304 #define INTERNAL_CONNECTOR_BITS 20
  305 #define INTERNAL_CONNECTOR_MASK 0x01700000
  306 
  307 /*
  308  * FIFO Registers. RX Status.
  309  *
  310  *     15:     Incomplete or FIFO empty.
  311  *     14:     1: Error in RX Packet   0: Incomplete or no error.
  312  *     13-11:  Type of error.
  313  *            1000 = Overrun.
  314  *            1011 = Run Packet Error.
  315  *            1100 = Alignment Error.
  316  *            1101 = CRC Error.
  317  *            1001 = Oversize Packet Error (>1514 bytes)
  318  *            0010 = Dribble Bits.
  319  *            (all other error codes, no errors.)
  320  *
  321  *     10-0:   RX Bytes (0-1514)
  322  */
  323 #define ERR_INCOMPLETE  (u_short) (0x8000)
  324 #define ERR_RX          (u_short) (0x4000)
  325 #define ERR_MASK        (u_short) (0x7800)
  326 #define ERR_OVERRUN     (u_short) (0x4000)
  327 #define ERR_RUNT        (u_short) (0x5800)
  328 #define ERR_ALIGNMENT   (u_short) (0x6000)
  329 #define ERR_CRC         (u_short) (0x6800)
  330 #define ERR_OVERSIZE    (u_short) (0x4800)
  331 #define ERR_DRIBBLE     (u_short) (0x1000)
  332 
  333 /*
  334  * TX Status.
  335  *
  336  *   Reports the transmit status of a completed transmission. Writing this
  337  *   register pops the transmit completion stack.
  338  *
  339  *   Window 1/Port 0x0b.
  340  *
  341  *     7:      Complete
  342  *     6:      Interrupt on successful transmission requested.
  343  *     5:      Jabber Error (TP Only, TX Reset required. )
  344  *     4:      Underrun (TX Reset required. )
  345  *     3:      Maximum Collisions.
  346  *     2:      TX Status Overflow.
  347  *     1-0:    Undefined.
  348  *
  349  */
  350 #define TXS_COMPLETE            0x80
  351 #define TXS_INTR_REQ            0x40
  352 #define TXS_JABBER              0x20
  353 #define TXS_UNDERRUN            0x10
  354 #define TXS_MAX_COLLISION       0x8
  355 #define TXS_STATUS_OVERFLOW     0x4
  356 
  357 #define RS_AUI                  (1<<5)
  358 #define RS_BNC                  (1<<4)
  359 #define RS_UTP                  (1<<3)
  360 #define RS_T4                   (1<<0)
  361 #define RS_TX                   (1<<1)
  362 #define RS_FX                   (1<<2)
  363 #define RS_MII                  (1<<6)
  364 
  365 
  366 /*
  367  * FIFO Status (Window 4)
  368  *
  369  *   Supports FIFO diagnostics
  370  *
  371  *   Window 4/Port 0x04.1
  372  *
  373  *     15:      1=RX receiving (RO). Set when a packet is being received
  374  *              into the RX FIFO.
  375  *     14:      Reserved
  376  *     13:      1=RX underrun (RO). Generates Adapter Failure interrupt.
  377  *              Requires RX Reset or Global Reset command to recover.
  378  *              It is generated when you read past the end of a packet -
  379  *              reading past what has been received so far will give bad
  380  *              data.
  381  *     12:      1=RX status overrun (RO). Set when there are already 8
  382  *              packets in the RX FIFO. While this bit is set, no additional
  383  *              packets are received. Requires no action on the part of
  384  *              the host. The condition is cleared once a packet has been
  385  *              read out of the RX FIFO.
  386  *     11:      1=RX overrun (RO). Set when the RX FIFO is full (there
  387  *              may not be an overrun packet yet). While this bit is set,
  388  *              no additional packets will be received (some additional
  389  *              bytes can still be pending between the wire and the RX
  390  *              FIFO). Requires no action on the part of the host. The
  391  *              condition is cleared once a few bytes have been read out
  392  *              from the RX FIFO.
  393  *     10:      1=TX overrun (RO). Generates adapter failure interrupt.
  394  *              Requires TX Reset or Global Reset command to recover.
  395  *              Disables Transmitter.
  396  *     9-8:     Unassigned.
  397  *     7-0:     Built in self test bits for the RX and TX FIFO's.
  398  */
  399 #define FIFOS_RX_RECEIVING      (u_short) 0x8000
  400 #define FIFOS_RX_UNDERRUN       (u_short) 0x2000
  401 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
  402 #define FIFOS_RX_OVERRUN        (u_short) 0x0800
  403 #define FIFOS_TX_OVERRUN        (u_short) 0x0400
  404 
  405 /*
  406  * Misc defines for various things.
  407  */
  408 #define TAG_ADAPTER                     0xd0
  409 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff
  410 #define ENABLE_DRQ_IRQ                  0x0001
  411 #define MFG_ID                          0x506d  /* `TCM' */
  412 #define PROD_ID                         0x5090
  413 #define JABBER_GUARD_ENABLE             0x40
  414 #define LINKBEAT_ENABLE                 0x80
  415 #define ENABLE_UTP                      (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
  416 #define DISABLE_UTP                     0x0
  417 #define RX_BYTES_MASK                   (u_short) (0x07ff)
  418 #define TX_INDICATE                     (1<<15)
  419 
  420 #define VX_IOSIZE                       0x20
  421 
  422 #define VX_CONNECTORS 8

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