The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/vx/if_vxreg.h

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    1 /*
    2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions are
    6  * met: 1. Redistributions of source code must retain the above copyright
    7  * notice, this list of conditions and the following disclaimer. 2. The name
    8  * of the author may not be used to endorse or promote products derived from
    9  * this software without specific prior written permission
   10  *
   11  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
   12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
   14  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   15  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   16  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
   17  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
   18  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
   19  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   20  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   21  *
   22  * $FreeBSD: stable/4/sys/dev/vx/if_vxreg.h 64162 2000-08-02 22:42:34Z peter $
   23  *
   24  October 2, 1994
   25 
   26  Modified by: Andres Vega Garcia
   27 
   28  INRIA - Sophia Antipolis, France
   29  e-mail: avega@sophia.inria.fr
   30  finger: avega@pax.inria.fr
   31 
   32  */
   33 
   34 /*
   35  * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
   36  * 3c590 family.
   37  */
   38 
   39 /*
   40  *  Promiscuous mode added and interrupt logic slightly changed
   41  *  to reduce the number of adapter failures. Transceiver select
   42  *  logic changed to use value from EEPROM. Autoconfiguration
   43  *  features added.
   44  *  Done by:
   45  *          Serge Babkin
   46  *          Chelindbank (Chelyabinsk, Russia)
   47  *          babkin@hq.icb.chel.su
   48  */
   49 
   50 /*
   51  * Ethernet software status per interface.
   52  */
   53 struct vx_softc {
   54     struct arpcom arpcom;       /* Ethernet common part         */
   55     int unit;                   /* unit number */
   56     u_int vx_io_addr;           /* i/o bus address              */
   57 #define MAX_MBS  8              /* # of mbufs we keep around    */
   58     struct mbuf *mb[MAX_MBS];   /* spare mbuf storage.          */
   59     int next_mb;                /* Which mbuf to use next.      */
   60     int last_mb;                /* Last mbuf.                   */
   61     char vx_connectors;         /* Connectors on this card.     */
   62     char vx_connector;          /* Connector to use.            */
   63     short tx_start_thresh;      /* Current TX_start_thresh.     */
   64     int tx_succ_ok;             /* # packets sent in sequence   */
   65                                 /* w/o underrun                 */
   66     struct callout_handle ch;   /* Callout handle for timeouts  */
   67     int buffill_pending;
   68 };
   69 
   70 /*
   71  * Some global constants
   72  */
   73 
   74 #define TX_INIT_RATE         16
   75 #define TX_INIT_MAX_RATE     64
   76 #define RX_INIT_LATENCY      64
   77 #define RX_INIT_EARLY_THRESH 64
   78 #define MIN_RX_EARLY_THRESHF   16 /* not less than ether_header */
   79 #define MIN_RX_EARLY_THRESHL   4
   80 
   81 #define EEPROMSIZE      0x40
   82 #define MAX_EEPROMBUSY  1000
   83 #define VX_LAST_TAG     0xd7
   84 #define VX_MAX_BOARDS   16
   85 #define VX_ID_PORT      0x100
   86 
   87 /*
   88  * some macros to acces long named fields
   89  */
   90 #define BASE    (sc->vx_io_addr)
   91 
   92 /*
   93  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
   94  * Offset 0xa)
   95  */
   96 #define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
   97 #define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
   98 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
   99 #define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
  100 
  101 #define EEPROM_BUSY             (1<<15)
  102 
  103 /*
  104  * Some short functions, worth to let them be a macro
  105  */
  106 
  107 /**************************************************************************
  108  *                                                                        *
  109  * These define the EEPROM data structure.  They are used in the probe
  110  * function to verify the existence of the adapter after having sent
  111  * the ID_Sequence.
  112  *
  113  * There are others but only the ones we use are defined here.
  114  *
  115  **************************************************************************/
  116 
  117 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
  118 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
  119 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
  120 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
  121 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
  122 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
  123 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
  124 #define EEPROM_OEM_ADDR_0       0xa     /* Word */
  125 #define EEPROM_OEM_ADDR_1       0xb     /* Word */
  126 #define EEPROM_OEM_ADDR_2       0xc     /* Word */
  127 #define EEPROM_SOFT_INFO_2      0xf     /* Software information 2 */
  128 
  129 #define NO_RX_OVN_ANOMALY       (1<<5)
  130 
  131 /**************************************************************************
  132  *                                                                                *
  133  * These are the registers for the 3Com 3c509 and their bit patterns when *
  134  * applicable.  They have been taken out the the "EtherLink III Parallel  *
  135  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
  136  * from 3com.                                                             *
  137  *                                                                                *
  138  **************************************************************************/
  139 
  140 #define VX_COMMAND              0x0e    /* Write. BASE+0x0e is always a
  141                                          * command reg. */
  142 #define VX_STATUS               0x0e    /* Read. BASE+0x0e is always status
  143                                          * reg. */
  144 #define VX_WINDOW               0x0f    /* Read. BASE+0x0f is always window
  145                                          * reg. */
  146 /*
  147  * Window 0 registers. Setup.
  148  */
  149 /* Write */
  150 #define VX_W0_EEPROM_DATA       0x0c
  151 #define VX_W0_EEPROM_COMMAND    0x0a
  152 #define VX_W0_RESOURCE_CFG      0x08
  153 #define VX_W0_ADDRESS_CFG       0x06 
  154 #define VX_W0_CONFIG_CTRL       0x04
  155         /* Read */
  156 #define VX_W0_PRODUCT_ID        0x02
  157 #define VX_W0_MFG_ID            0x00
  158 
  159 
  160 /*
  161  * Window 1 registers. Operating Set.
  162  */
  163 /* Write */
  164 #define VX_W1_TX_PIO_WR_2       0x02
  165 #define VX_W1_TX_PIO_WR_1       0x00
  166 /* Read */
  167 #define VX_W1_FREE_TX           0x0c
  168 #define VX_W1_TX_STATUS         0x0b    /* byte */
  169 #define VX_W1_TIMER             0x0a    /* byte */
  170 #define VX_W1_RX_STATUS         0x08
  171 #define VX_W1_RX_PIO_RD_2       0x02
  172 #define VX_W1_RX_PIO_RD_1       0x00
  173 
  174 /*
  175  * Window 2 registers. Station Address Setup/Read
  176  */
  177 /* Read/Write */
  178 #define VX_W2_ADDR_5            0x05
  179 #define VX_W2_ADDR_4            0x04
  180 #define VX_W2_ADDR_3            0x03
  181 #define VX_W2_ADDR_2            0x02
  182 #define VX_W2_ADDR_1            0x01
  183 #define VX_W2_ADDR_0            0x00
  184 
  185 /*
  186  * Window 3 registers. FIFO Management.
  187  */
  188 /* Read */
  189 #define VX_W3_INTERNAL_CFG      0x00
  190 #define VX_W3_RESET_OPT         0x08
  191 #define VX_W3_FREE_TX           0x0c
  192 #define VX_W3_FREE_RX           0x0a
  193 
  194 /*
  195  * Window 4 registers. Diagnostics.
  196  */
  197 /* Read/Write */
  198 #define VX_W4_MEDIA_TYPE        0x0a
  199 #define VX_W4_CTRLR_STATUS      0x08
  200 #define VX_W4_NET_DIAG          0x06
  201 #define VX_W4_FIFO_DIAG         0x04
  202 #define VX_W4_HOST_DIAG         0x02
  203 #define VX_W4_TX_DIAG           0x00
  204 
  205 /*
  206  * Window 5 Registers.  Results and Internal status.
  207  */
  208 /* Read */
  209 #define VX_W5_READ_0_MASK       0x0c
  210 #define VX_W5_INTR_MASK         0x0a
  211 #define VX_W5_RX_FILTER         0x08
  212 #define VX_W5_RX_EARLY_THRESH   0x06
  213 #define VX_W5_TX_AVAIL_THRESH   0x02
  214 #define VX_W5_TX_START_THRESH   0x00
  215 
  216 /*
  217  * Window 6 registers. Statistics.
  218  */
  219 /* Read/Write */
  220 #define TX_TOTAL_OK             0x0c
  221 #define RX_TOTAL_OK             0x0a
  222 #define TX_DEFERRALS            0x08
  223 #define RX_FRAMES_OK            0x07
  224 #define TX_FRAMES_OK            0x06
  225 #define RX_OVERRUNS             0x05
  226 #define TX_COLLISIONS           0x04
  227 #define TX_AFTER_1_COLLISION    0x03
  228 #define TX_AFTER_X_COLLISIONS   0x02
  229 #define TX_NO_SQE               0x01
  230 #define TX_CD_LOST              0x00
  231 
  232 /****************************************
  233  *
  234  * Register definitions.
  235  *
  236  ****************************************/
  237 
  238 /*
  239  * Command register. All windows.
  240  *
  241  * 16 bit register.
  242  *     15-11:  5-bit code for command to be executed.
  243  *     10-0:   11-bit arg if any. For commands with no args;
  244  *            this can be set to anything.
  245  */
  246 #define GLOBAL_RESET            (u_short) 0x0000        /* Wait at least 1ms
  247                                                          * after issuing */
  248 #define WINDOW_SELECT           (u_short) (0x1<<11)
  249 #define START_TRANSCEIVER       (u_short) (0x2<<11)     /* Read ADDR_CFG reg to
  250                                                          * determine whether
  251                                                          * this is needed. If
  252                                                          * so; wait 800 uSec
  253                                                          * before using trans-
  254                                                          * ceiver. */
  255 #define RX_DISABLE              (u_short) (0x3<<11)     /* state disabled on
  256                                                          * power-up */
  257 #define RX_ENABLE               (u_short) (0x4<<11)
  258 #define RX_RESET                (u_short) (0x5<<11)
  259 #define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
  260 #define TX_ENABLE               (u_short) (0x9<<11)
  261 #define TX_DISABLE              (u_short) (0xa<<11)
  262 #define TX_RESET                (u_short) (0xb<<11)
  263 #define REQ_INTR                (u_short) (0xc<<11)
  264 /*
  265  * The following C_* acknowledge the various interrupts. Some of them don't
  266  * do anything.  See the manual.
  267  */
  268 #define ACK_INTR                (u_short) (0x6800)
  269 #       define C_INTR_LATCH     (u_short) (ACK_INTR|0x1)
  270 #       define C_CARD_FAILURE   (u_short) (ACK_INTR|0x2)
  271 #       define C_TX_COMPLETE    (u_short) (ACK_INTR|0x4)
  272 #       define C_TX_AVAIL       (u_short) (ACK_INTR|0x8)
  273 #       define C_RX_COMPLETE    (u_short) (ACK_INTR|0x10)
  274 #       define C_RX_EARLY       (u_short) (ACK_INTR|0x20)
  275 #       define C_INT_RQD                (u_short) (ACK_INTR|0x40)
  276 #       define C_UPD_STATS      (u_short) (ACK_INTR|0x80)
  277 #define SET_INTR_MASK           (u_short) (0xe<<11)
  278 #define SET_RD_0_MASK           (u_short) (0xf<<11)
  279 #define SET_RX_FILTER           (u_short) (0x10<<11)
  280 #       define FIL_INDIVIDUAL   (u_short) (0x1)
  281 #       define FIL_MULTICAST     (u_short) (0x02)
  282 #       define FIL_BRDCST        (u_short) (0x04)
  283 #       define FIL_PROMISC       (u_short) (0x08)
  284 #define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
  285 #define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
  286 #define SET_TX_START_THRESH     (u_short) (0x13<<11)
  287 #define STATS_ENABLE            (u_short) (0x15<<11)
  288 #define STATS_DISABLE           (u_short) (0x16<<11)
  289 #define STOP_TRANSCEIVER        (u_short) (0x17<<11)
  290 
  291 /*
  292  * Status register. All windows.
  293  *
  294  *     15-13:  Window number(0-7).
  295  *     12:     Command_in_progress.
  296  *     11:     reserved.
  297  *     10:     reserved.
  298  *     9:      reserved.
  299  *     8:      reserved.
  300  *     7:      Update Statistics.
  301  *     6:      Interrupt Requested.
  302  *     5:      RX Early.
  303  *     4:      RX Complete.
  304  *     3:      TX Available.
  305  *     2:      TX Complete.
  306  *     1:      Adapter Failure.
  307  *     0:      Interrupt Latch.
  308  */
  309 #define S_INTR_LATCH            (u_short) (0x1)
  310 #define S_CARD_FAILURE          (u_short) (0x2)
  311 #define S_TX_COMPLETE           (u_short) (0x4)
  312 #define S_TX_AVAIL              (u_short) (0x8)
  313 #define S_RX_COMPLETE           (u_short) (0x10)
  314 #define S_RX_EARLY              (u_short) (0x20)
  315 #define S_INT_RQD               (u_short) (0x40)
  316 #define S_UPD_STATS             (u_short) (0x80)
  317 #define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
  318 
  319 #define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
  320 
  321 /* Address Config. Register.    
  322  * Window 0/Port 06
  323  */
  324 
  325 #define ACF_CONNECTOR_BITS      14  
  326 #define ACF_CONNECTOR_UTP       0
  327 #define ACF_CONNECTOR_AUI       1
  328 #define ACF_CONNECTOR_BNC       3
  329    
  330 #define INTERNAL_CONNECTOR_BITS 20
  331 #define INTERNAL_CONNECTOR_MASK 0x01700000
  332 
  333 /*
  334  * FIFO Registers. RX Status.
  335  *
  336  *     15:     Incomplete or FIFO empty.
  337  *     14:     1: Error in RX Packet   0: Incomplete or no error.
  338  *     13-11:  Type of error.
  339  *            1000 = Overrun.
  340  *            1011 = Run Packet Error.
  341  *            1100 = Alignment Error.
  342  *            1101 = CRC Error.
  343  *            1001 = Oversize Packet Error (>1514 bytes)
  344  *            0010 = Dribble Bits.
  345  *            (all other error codes, no errors.)
  346  *
  347  *     10-0:   RX Bytes (0-1514)
  348  */
  349 #define ERR_INCOMPLETE  (u_short) (0x8000)
  350 #define ERR_RX          (u_short) (0x4000)
  351 #define ERR_MASK        (u_short) (0x7800)
  352 #define ERR_OVERRUN     (u_short) (0x4000)
  353 #define ERR_RUNT        (u_short) (0x5800)
  354 #define ERR_ALIGNMENT   (u_short) (0x6000)
  355 #define ERR_CRC         (u_short) (0x6800)
  356 #define ERR_OVERSIZE    (u_short) (0x4800)
  357 #define ERR_DRIBBLE     (u_short) (0x1000)
  358 
  359 /*
  360  * TX Status. 
  361  *
  362  *   Reports the transmit status of a completed transmission. Writing this
  363  *   register pops the transmit completion stack.
  364  *
  365  *   Window 1/Port 0x0b.
  366  *
  367  *     7:      Complete
  368  *     6:      Interrupt on successful transmission requested.
  369  *     5:      Jabber Error (TP Only, TX Reset required. )
  370  *     4:      Underrun (TX Reset required. )
  371  *     3:      Maximum Collisions.
  372  *     2:      TX Status Overflow.
  373  *     1-0:    Undefined.
  374  *
  375  */
  376 #define TXS_COMPLETE            0x80
  377 #define TXS_INTR_REQ            0x40
  378 #define TXS_JABBER              0x20
  379 #define TXS_UNDERRUN            0x10
  380 #define TXS_MAX_COLLISION       0x8
  381 #define TXS_STATUS_OVERFLOW     0x4
  382 
  383 #define RS_AUI                  (1<<5)
  384 #define RS_BNC                  (1<<4)
  385 #define RS_UTP                  (1<<3)
  386 #define RS_T4                   (1<<0)
  387 #define RS_TX                   (1<<1)
  388 #define RS_FX                   (1<<2)
  389 #define RS_MII                  (1<<6)
  390 
  391 
  392 /*
  393  * FIFO Status (Window 4)
  394  *
  395  *   Supports FIFO diagnostics
  396  *
  397  *   Window 4/Port 0x04.1
  398  *
  399  *     15:      1=RX receiving (RO). Set when a packet is being received
  400  *              into the RX FIFO.
  401  *     14:      Reserved
  402  *     13:      1=RX underrun (RO). Generates Adapter Failure interrupt.
  403  *              Requires RX Reset or Global Reset command to recover.
  404  *              It is generated when you read past the end of a packet -
  405  *              reading past what has been received so far will give bad
  406  *              data.
  407  *     12:      1=RX status overrun (RO). Set when there are already 8
  408  *              packets in the RX FIFO. While this bit is set, no additional
  409  *              packets are received. Requires no action on the part of
  410  *              the host. The condition is cleared once a packet has been
  411  *              read out of the RX FIFO.
  412  *     11:      1=RX overrun (RO). Set when the RX FIFO is full (there
  413  *              may not be an overrun packet yet). While this bit is set,
  414  *              no additional packets will be received (some additional
  415  *              bytes can still be pending between the wire and the RX
  416  *              FIFO). Requires no action on the part of the host. The
  417  *              condition is cleared once a few bytes have been read out
  418  *              from the RX FIFO.
  419  *     10:      1=TX overrun (RO). Generates adapter failure interrupt.
  420  *              Requires TX Reset or Global Reset command to recover.
  421  *              Disables Transmitter.
  422  *     9-8:     Unassigned.
  423  *     7-0:     Built in self test bits for the RX and TX FIFO's.
  424  */
  425 #define FIFOS_RX_RECEIVING      (u_short) 0x8000
  426 #define FIFOS_RX_UNDERRUN       (u_short) 0x2000
  427 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
  428 #define FIFOS_RX_OVERRUN        (u_short) 0x0800
  429 #define FIFOS_TX_OVERRUN        (u_short) 0x0400
  430 
  431 /*
  432  * Misc defines for various things.
  433  */
  434 #define TAG_ADAPTER                     0xd0
  435 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff
  436 #define ENABLE_DRQ_IRQ                  0x0001
  437 #define MFG_ID                          0x506d  /* `TCM' */
  438 #define PROD_ID                         0x5090
  439 #define GO_WINDOW(x)            outw(BASE+VX_COMMAND, WINDOW_SELECT|(x))
  440 #define JABBER_GUARD_ENABLE     0x40
  441 #define LINKBEAT_ENABLE         0x80
  442 #define ENABLE_UTP              (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
  443 #define DISABLE_UTP             0x0
  444 #define RX_BYTES_MASK           (u_short) (0x07ff)
  445 #define TX_INDICATE             1<<15
  446 
  447 #define VX_IOSIZE       0x20
  448 
  449 #define VX_CONNECTORS 8
  450 
  451 extern struct vx_softc *vx_softc[];
  452 extern u_long vx_count;
  453 extern struct vx_softc *vxalloc __P((int));
  454 extern void vxfree __P((struct vx_softc *));
  455 extern int vxattach __P((struct vx_softc *));
  456 extern void vxstop __P((struct vx_softc *));
  457 extern void vxintr __P((void *));
  458 extern int vxbusyeeprom __P((struct vx_softc *));

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