The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/vx/if_vxreg.h

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    1 /*
    2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions are
    6  * met: 1. Redistributions of source code must retain the above copyright
    7  * notice, this list of conditions and the following disclaimer. 2. The name
    8  * of the author may not be used to endorse or promote products derived from
    9  * this software without specific prior written permission
   10  *
   11  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
   12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
   14  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   15  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   16  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
   17  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
   18  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
   19  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   20  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   21  *
   22  * $FreeBSD: releng/5.1/sys/dev/vx/if_vxreg.h 92739 2002-03-20 02:08:01Z alfred $
   23  *
   24  October 2, 1994
   25 
   26  Modified by: Andres Vega Garcia
   27 
   28  INRIA - Sophia Antipolis, France
   29  e-mail: avega@sophia.inria.fr
   30  finger: avega@pax.inria.fr
   31 
   32  */
   33 
   34 /*
   35  * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
   36  * 3c590 family.
   37  */
   38 
   39 /*
   40  *  Promiscuous mode added and interrupt logic slightly changed
   41  *  to reduce the number of adapter failures. Transceiver select
   42  *  logic changed to use value from EEPROM. Autoconfiguration
   43  *  features added.
   44  *  Done by:
   45  *          Serge Babkin
   46  *          Chelindbank (Chelyabinsk, Russia)
   47  *          babkin@hq.icb.chel.su
   48  */
   49 
   50 /*
   51  * Ethernet software status per interface.
   52  */
   53 struct vx_softc {
   54     struct arpcom arpcom;       /* Ethernet common part         */
   55     int unit;                   /* unit number */
   56     bus_space_handle_t          vx_bhandle;
   57     bus_space_tag_t             vx_btag;
   58     void                        *vx_intrhand;
   59     struct resource             *vx_irq;
   60     struct resource             *vx_res;
   61 #define MAX_MBS  8              /* # of mbufs we keep around    */
   62     struct mbuf *mb[MAX_MBS];   /* spare mbuf storage.          */
   63     int next_mb;                /* Which mbuf to use next.      */
   64     int last_mb;                /* Last mbuf.                   */
   65     char vx_connectors;         /* Connectors on this card.     */
   66     char vx_connector;          /* Connector to use.            */
   67     short tx_start_thresh;      /* Current TX_start_thresh.     */
   68     int tx_succ_ok;             /* # packets sent in sequence   */
   69                                 /* w/o underrun                 */
   70     struct callout_handle ch;   /* Callout handle for timeouts  */
   71     int buffill_pending;
   72 };
   73 
   74 #define CSR_WRITE_4(sc, reg, val)       \
   75         bus_space_write_4(sc->vx_btag, sc->vx_bhandle, reg, val)
   76 #define CSR_WRITE_2(sc, reg, val)       \
   77         bus_space_write_2(sc->vx_btag, sc->vx_bhandle, reg, val)
   78 #define CSR_WRITE_1(sc, reg, val)       \
   79         bus_space_write_1(sc->vx_btag, sc->vx_bhandle, reg, val)
   80 
   81 #define CSR_READ_4(sc, reg)             \
   82         bus_space_read_4(sc->vx_btag, sc->vx_bhandle, reg)
   83 #define CSR_READ_2(sc, reg)             \
   84         bus_space_read_2(sc->vx_btag, sc->vx_bhandle, reg)
   85 #define CSR_READ_1(sc, reg)             \
   86         bus_space_read_1(sc->vx_btag, sc->vx_bhandle, reg)
   87 
   88 /*
   89  * Some global constants
   90  */
   91 
   92 #define TX_INIT_RATE         16
   93 #define TX_INIT_MAX_RATE     64
   94 #define RX_INIT_LATENCY      64
   95 #define RX_INIT_EARLY_THRESH 64
   96 #define MIN_RX_EARLY_THRESHF   16 /* not less than ether_header */
   97 #define MIN_RX_EARLY_THRESHL   4
   98 
   99 #define EEPROMSIZE      0x40
  100 #define MAX_EEPROMBUSY  1000
  101 #define VX_LAST_TAG     0xd7
  102 #define VX_MAX_BOARDS   16
  103 #define VX_ID_PORT      0x100
  104 
  105 /*
  106  * some macros to acces long named fields
  107  */
  108 #define BASE    (sc->vx_io_addr)
  109 
  110 /*
  111  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
  112  * Offset 0xa)
  113  */
  114 #define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
  115 #define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
  116 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
  117 #define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
  118 
  119 #define EEPROM_BUSY             (1<<15)
  120 
  121 /*
  122  * Some short functions, worth to let them be a macro
  123  */
  124 
  125 /**************************************************************************
  126  *                                                                        *
  127  * These define the EEPROM data structure.  They are used in the probe
  128  * function to verify the existence of the adapter after having sent
  129  * the ID_Sequence.
  130  *
  131  * There are others but only the ones we use are defined here.
  132  *
  133  **************************************************************************/
  134 
  135 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
  136 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
  137 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
  138 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
  139 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
  140 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
  141 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
  142 #define EEPROM_OEM_ADDR_0       0xa     /* Word */
  143 #define EEPROM_OEM_ADDR_1       0xb     /* Word */
  144 #define EEPROM_OEM_ADDR_2       0xc     /* Word */
  145 #define EEPROM_SOFT_INFO_2      0xf     /* Software information 2 */
  146 
  147 #define NO_RX_OVN_ANOMALY       (1<<5)
  148 
  149 /**************************************************************************
  150  *                                                                                *
  151  * These are the registers for the 3Com 3c509 and their bit patterns when *
  152  * applicable.  They have been taken out the the "EtherLink III Parallel  *
  153  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
  154  * from 3com.                                                             *
  155  *                                                                                *
  156  **************************************************************************/
  157 
  158 #define VX_COMMAND              0x0e    /* Write. BASE+0x0e is always a
  159                                          * command reg. */
  160 #define VX_STATUS               0x0e    /* Read. BASE+0x0e is always status
  161                                          * reg. */
  162 #define VX_WINDOW               0x0f    /* Read. BASE+0x0f is always window
  163                                          * reg. */
  164 /*
  165  * Window 0 registers. Setup.
  166  */
  167 /* Write */
  168 #define VX_W0_EEPROM_DATA       0x0c
  169 #define VX_W0_EEPROM_COMMAND    0x0a
  170 #define VX_W0_RESOURCE_CFG      0x08
  171 #define VX_W0_ADDRESS_CFG       0x06 
  172 #define VX_W0_CONFIG_CTRL       0x04
  173         /* Read */
  174 #define VX_W0_PRODUCT_ID        0x02
  175 #define VX_W0_MFG_ID            0x00
  176 
  177 
  178 /*
  179  * Window 1 registers. Operating Set.
  180  */
  181 /* Write */
  182 #define VX_W1_TX_PIO_WR_2       0x02
  183 #define VX_W1_TX_PIO_WR_1       0x00
  184 /* Read */
  185 #define VX_W1_FREE_TX           0x0c
  186 #define VX_W1_TX_STATUS         0x0b    /* byte */
  187 #define VX_W1_TIMER             0x0a    /* byte */
  188 #define VX_W1_RX_STATUS         0x08
  189 #define VX_W1_RX_PIO_RD_2       0x02
  190 #define VX_W1_RX_PIO_RD_1       0x00
  191 
  192 /*
  193  * Window 2 registers. Station Address Setup/Read
  194  */
  195 /* Read/Write */
  196 #define VX_W2_ADDR_5            0x05
  197 #define VX_W2_ADDR_4            0x04
  198 #define VX_W2_ADDR_3            0x03
  199 #define VX_W2_ADDR_2            0x02
  200 #define VX_W2_ADDR_1            0x01
  201 #define VX_W2_ADDR_0            0x00
  202 
  203 /*
  204  * Window 3 registers. FIFO Management.
  205  */
  206 /* Read */
  207 #define VX_W3_INTERNAL_CFG      0x00
  208 #define VX_W3_RESET_OPT         0x08
  209 #define VX_W3_FREE_TX           0x0c
  210 #define VX_W3_FREE_RX           0x0a
  211 
  212 /*
  213  * Window 4 registers. Diagnostics.
  214  */
  215 /* Read/Write */
  216 #define VX_W4_MEDIA_TYPE        0x0a
  217 #define VX_W4_CTRLR_STATUS      0x08
  218 #define VX_W4_NET_DIAG          0x06
  219 #define VX_W4_FIFO_DIAG         0x04
  220 #define VX_W4_HOST_DIAG         0x02
  221 #define VX_W4_TX_DIAG           0x00
  222 
  223 /*
  224  * Window 5 Registers.  Results and Internal status.
  225  */
  226 /* Read */
  227 #define VX_W5_READ_0_MASK       0x0c
  228 #define VX_W5_INTR_MASK         0x0a
  229 #define VX_W5_RX_FILTER         0x08
  230 #define VX_W5_RX_EARLY_THRESH   0x06
  231 #define VX_W5_TX_AVAIL_THRESH   0x02
  232 #define VX_W5_TX_START_THRESH   0x00
  233 
  234 /*
  235  * Window 6 registers. Statistics.
  236  */
  237 /* Read/Write */
  238 #define TX_TOTAL_OK             0x0c
  239 #define RX_TOTAL_OK             0x0a
  240 #define TX_DEFERRALS            0x08
  241 #define RX_FRAMES_OK            0x07
  242 #define TX_FRAMES_OK            0x06
  243 #define RX_OVERRUNS             0x05
  244 #define TX_COLLISIONS           0x04
  245 #define TX_AFTER_1_COLLISION    0x03
  246 #define TX_AFTER_X_COLLISIONS   0x02
  247 #define TX_NO_SQE               0x01
  248 #define TX_CD_LOST              0x00
  249 
  250 /****************************************
  251  *
  252  * Register definitions.
  253  *
  254  ****************************************/
  255 
  256 /*
  257  * Command register. All windows.
  258  *
  259  * 16 bit register.
  260  *     15-11:  5-bit code for command to be executed.
  261  *     10-0:   11-bit arg if any. For commands with no args;
  262  *            this can be set to anything.
  263  */
  264 #define GLOBAL_RESET            (u_short) 0x0000        /* Wait at least 1ms
  265                                                          * after issuing */
  266 #define WINDOW_SELECT           (u_short) (0x1<<11)
  267 #define START_TRANSCEIVER       (u_short) (0x2<<11)     /* Read ADDR_CFG reg to
  268                                                          * determine whether
  269                                                          * this is needed. If
  270                                                          * so; wait 800 uSec
  271                                                          * before using trans-
  272                                                          * ceiver. */
  273 #define RX_DISABLE              (u_short) (0x3<<11)     /* state disabled on
  274                                                          * power-up */
  275 #define RX_ENABLE               (u_short) (0x4<<11)
  276 #define RX_RESET                (u_short) (0x5<<11)
  277 #define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
  278 #define TX_ENABLE               (u_short) (0x9<<11)
  279 #define TX_DISABLE              (u_short) (0xa<<11)
  280 #define TX_RESET                (u_short) (0xb<<11)
  281 #define REQ_INTR                (u_short) (0xc<<11)
  282 /*
  283  * The following C_* acknowledge the various interrupts. Some of them don't
  284  * do anything.  See the manual.
  285  */
  286 #define ACK_INTR                (u_short) (0x6800)
  287 #       define C_INTR_LATCH     (u_short) (ACK_INTR|0x1)
  288 #       define C_CARD_FAILURE   (u_short) (ACK_INTR|0x2)
  289 #       define C_TX_COMPLETE    (u_short) (ACK_INTR|0x4)
  290 #       define C_TX_AVAIL       (u_short) (ACK_INTR|0x8)
  291 #       define C_RX_COMPLETE    (u_short) (ACK_INTR|0x10)
  292 #       define C_RX_EARLY       (u_short) (ACK_INTR|0x20)
  293 #       define C_INT_RQD                (u_short) (ACK_INTR|0x40)
  294 #       define C_UPD_STATS      (u_short) (ACK_INTR|0x80)
  295 #define SET_INTR_MASK           (u_short) (0xe<<11)
  296 #define SET_RD_0_MASK           (u_short) (0xf<<11)
  297 #define SET_RX_FILTER           (u_short) (0x10<<11)
  298 #       define FIL_INDIVIDUAL   (u_short) (0x1)
  299 #       define FIL_MULTICAST     (u_short) (0x02)
  300 #       define FIL_BRDCST        (u_short) (0x04)
  301 #       define FIL_PROMISC       (u_short) (0x08)
  302 #define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
  303 #define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
  304 #define SET_TX_START_THRESH     (u_short) (0x13<<11)
  305 #define STATS_ENABLE            (u_short) (0x15<<11)
  306 #define STATS_DISABLE           (u_short) (0x16<<11)
  307 #define STOP_TRANSCEIVER        (u_short) (0x17<<11)
  308 
  309 /*
  310  * Status register. All windows.
  311  *
  312  *     15-13:  Window number(0-7).
  313  *     12:     Command_in_progress.
  314  *     11:     reserved.
  315  *     10:     reserved.
  316  *     9:      reserved.
  317  *     8:      reserved.
  318  *     7:      Update Statistics.
  319  *     6:      Interrupt Requested.
  320  *     5:      RX Early.
  321  *     4:      RX Complete.
  322  *     3:      TX Available.
  323  *     2:      TX Complete.
  324  *     1:      Adapter Failure.
  325  *     0:      Interrupt Latch.
  326  */
  327 #define S_INTR_LATCH            (u_short) (0x1)
  328 #define S_CARD_FAILURE          (u_short) (0x2)
  329 #define S_TX_COMPLETE           (u_short) (0x4)
  330 #define S_TX_AVAIL              (u_short) (0x8)
  331 #define S_RX_COMPLETE           (u_short) (0x10)
  332 #define S_RX_EARLY              (u_short) (0x20)
  333 #define S_INT_RQD               (u_short) (0x40)
  334 #define S_UPD_STATS             (u_short) (0x80)
  335 #define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
  336 
  337 #define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS)
  338 
  339 /* Address Config. Register.    
  340  * Window 0/Port 06
  341  */
  342 
  343 #define ACF_CONNECTOR_BITS      14  
  344 #define ACF_CONNECTOR_UTP       0
  345 #define ACF_CONNECTOR_AUI       1
  346 #define ACF_CONNECTOR_BNC       3
  347    
  348 #define INTERNAL_CONNECTOR_BITS 20
  349 #define INTERNAL_CONNECTOR_MASK 0x01700000
  350 
  351 /*
  352  * FIFO Registers. RX Status.
  353  *
  354  *     15:     Incomplete or FIFO empty.
  355  *     14:     1: Error in RX Packet   0: Incomplete or no error.
  356  *     13-11:  Type of error.
  357  *            1000 = Overrun.
  358  *            1011 = Run Packet Error.
  359  *            1100 = Alignment Error.
  360  *            1101 = CRC Error.
  361  *            1001 = Oversize Packet Error (>1514 bytes)
  362  *            0010 = Dribble Bits.
  363  *            (all other error codes, no errors.)
  364  *
  365  *     10-0:   RX Bytes (0-1514)
  366  */
  367 #define ERR_INCOMPLETE  (u_short) (0x8000)
  368 #define ERR_RX          (u_short) (0x4000)
  369 #define ERR_MASK        (u_short) (0x7800)
  370 #define ERR_OVERRUN     (u_short) (0x4000)
  371 #define ERR_RUNT        (u_short) (0x5800)
  372 #define ERR_ALIGNMENT   (u_short) (0x6000)
  373 #define ERR_CRC         (u_short) (0x6800)
  374 #define ERR_OVERSIZE    (u_short) (0x4800)
  375 #define ERR_DRIBBLE     (u_short) (0x1000)
  376 
  377 /*
  378  * TX Status. 
  379  *
  380  *   Reports the transmit status of a completed transmission. Writing this
  381  *   register pops the transmit completion stack.
  382  *
  383  *   Window 1/Port 0x0b.
  384  *
  385  *     7:      Complete
  386  *     6:      Interrupt on successful transmission requested.
  387  *     5:      Jabber Error (TP Only, TX Reset required. )
  388  *     4:      Underrun (TX Reset required. )
  389  *     3:      Maximum Collisions.
  390  *     2:      TX Status Overflow.
  391  *     1-0:    Undefined.
  392  *
  393  */
  394 #define TXS_COMPLETE            0x80
  395 #define TXS_INTR_REQ            0x40
  396 #define TXS_JABBER              0x20
  397 #define TXS_UNDERRUN            0x10
  398 #define TXS_MAX_COLLISION       0x8
  399 #define TXS_STATUS_OVERFLOW     0x4
  400 
  401 #define RS_AUI                  (1<<5)
  402 #define RS_BNC                  (1<<4)
  403 #define RS_UTP                  (1<<3)
  404 #define RS_T4                   (1<<0)
  405 #define RS_TX                   (1<<1)
  406 #define RS_FX                   (1<<2)
  407 #define RS_MII                  (1<<6)
  408 
  409 
  410 /*
  411  * FIFO Status (Window 4)
  412  *
  413  *   Supports FIFO diagnostics
  414  *
  415  *   Window 4/Port 0x04.1
  416  *
  417  *     15:      1=RX receiving (RO). Set when a packet is being received
  418  *              into the RX FIFO.
  419  *     14:      Reserved
  420  *     13:      1=RX underrun (RO). Generates Adapter Failure interrupt.
  421  *              Requires RX Reset or Global Reset command to recover.
  422  *              It is generated when you read past the end of a packet -
  423  *              reading past what has been received so far will give bad
  424  *              data.
  425  *     12:      1=RX status overrun (RO). Set when there are already 8
  426  *              packets in the RX FIFO. While this bit is set, no additional
  427  *              packets are received. Requires no action on the part of
  428  *              the host. The condition is cleared once a packet has been
  429  *              read out of the RX FIFO.
  430  *     11:      1=RX overrun (RO). Set when the RX FIFO is full (there
  431  *              may not be an overrun packet yet). While this bit is set,
  432  *              no additional packets will be received (some additional
  433  *              bytes can still be pending between the wire and the RX
  434  *              FIFO). Requires no action on the part of the host. The
  435  *              condition is cleared once a few bytes have been read out
  436  *              from the RX FIFO.
  437  *     10:      1=TX overrun (RO). Generates adapter failure interrupt.
  438  *              Requires TX Reset or Global Reset command to recover.
  439  *              Disables Transmitter.
  440  *     9-8:     Unassigned.
  441  *     7-0:     Built in self test bits for the RX and TX FIFO's.
  442  */
  443 #define FIFOS_RX_RECEIVING      (u_short) 0x8000
  444 #define FIFOS_RX_UNDERRUN       (u_short) 0x2000
  445 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
  446 #define FIFOS_RX_OVERRUN        (u_short) 0x0800
  447 #define FIFOS_TX_OVERRUN        (u_short) 0x0400
  448 
  449 /*
  450  * Misc defines for various things.
  451  */
  452 #define TAG_ADAPTER                     0xd0
  453 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff
  454 #define ENABLE_DRQ_IRQ                  0x0001
  455 #define MFG_ID                          0x506d  /* `TCM' */
  456 #define PROD_ID                         0x5090
  457 #define GO_WINDOW(x)            CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x))
  458 #define JABBER_GUARD_ENABLE     0x40
  459 #define LINKBEAT_ENABLE         0x80
  460 #define ENABLE_UTP              (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
  461 #define DISABLE_UTP             0x0
  462 #define RX_BYTES_MASK           (u_short) (0x07ff)
  463 #define TX_INDICATE             1<<15
  464 
  465 #define VX_IOSIZE       0x20
  466 
  467 #define VX_CONNECTORS 8
  468 
  469 extern struct vx_softc *vx_softc[];
  470 extern u_long vx_count;
  471 extern struct vx_softc *vxalloc(int);
  472 extern void vxfree(struct vx_softc *);
  473 extern int vxattach(struct vx_softc *);
  474 extern void vxstop(struct vx_softc *);
  475 extern void vxintr(void *);
  476 extern int vxbusyeeprom(struct vx_softc *);

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