Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/vx/if_vxreg.h
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1 /*- 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from 9 * this software without specific prior written permission 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 * 22 * $FreeBSD: releng/5.4/sys/dev/vx/if_vxreg.h 141016 2005-01-30 01:00:13Z imp $ 23 */ 24 25 /* 26 * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the 27 * 3c590 family. 28 */ 29 30 /* 31 * Some global constants 32 */ 33 34 #define TX_INIT_RATE 16 35 #define TX_INIT_MAX_RATE 64 36 #define RX_INIT_LATENCY 64 37 #define RX_INIT_EARLY_THRESH 64 38 #define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 39 #define MIN_RX_EARLY_THRESHL 4 40 41 #define EEPROMSIZE 0x40 42 #define MAX_EEPROMBUSY 1000 43 #define VX_LAST_TAG 0xd7 44 #define VX_MAX_BOARDS 16 45 46 /* 47 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 48 * Offset 0xa) 49 */ 50 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 51 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 52 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 53 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 54 55 #define EEPROM_BUSY (1<<15) 56 #define EEPROM_TST_MODE (1<<14) 57 58 /* 59 * Some short functions, worth to let them be a macro 60 */ 61 #define GO_WINDOW(x) CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x)) 62 63 /************************************************************************** 64 * * 65 * These define the EEPROM data structure. They are used in the probe 66 * function to verify the existence of the adapter after having sent 67 * the ID_Sequence. 68 * 69 **************************************************************************/ 70 71 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 72 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 73 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 74 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 75 #define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ 76 #define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ 77 #define EEPROM_MFG_PRODUCT 0x6 /* Product code */ 78 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 79 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 80 #define ADDR_CFG_EISA 0x1f 81 #define ADDR_CFG_MASK 0x1f 82 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 83 #define EEPROM_OEM_ADDR0 0xa 84 #define EEPROM_OEM_ADDR1 0xb 85 #define EEPROM_OEM_ADDR2 0xc 86 #define EEPROM_SOFTINFO 0xd 87 #define EEPROM_COMPAT 0xe 88 #define EEPROM_SOFTINFO2 0xf 89 #define EEPROM_CAP 0x10 90 #define CAP_ISA 0x2083 91 #define CAP_PCMCIA 0x2082 92 #define EEPROM_INT_CONFIG_0 0x12 93 #define EEPROM_INT_CONFIG_1 0x13 94 /* RAM Partition TX FIFO/RX FIFO */ 95 #define ICW1_RAM_PART_MASK 0x03 96 #define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b 97 * default power-up/reset */ 98 #define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size == 99 * 000b) */ 100 #define ICW1_RAM_PART_11 0x10 /* 1:1 */ 101 #define ICW1_RAM_PART_RESV 0x11 /* Reserved */ 102 /* ISA Adapter Selection */ 103 #define ICW1_IAS_MASK 0x0c 104 #define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */ 105 #define ICW1_IAS_ISA 0x04 /* ISA contention only */ 106 #define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */ 107 #define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */ 108 109 #define EEPROM_CHECKSUM_EL3 0x17 110 111 #define NO_RX_OVN_ANOMALY (1<<5) 112 113 /************************************************************************** 114 * * 115 * These are the registers for the 3Com 3c509 and their bit patterns when * 116 * applicable. They have been taken out the the "EtherLink III Parallel * 117 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 118 * from 3com. * 119 * * 120 **************************************************************************/ 121 122 #define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a 123 * command reg. */ 124 #define VX_STATUS 0x0e /* Read. BASE+0x0e is always status 125 * reg. */ 126 #define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window 127 * reg. */ 128 /* 129 * Window 0 registers. Setup. 130 */ 131 /* Write */ 132 #define VX_W0_EEPROM_DATA 0x0c 133 #define VX_W0_EEPROM_COMMAND 0x0a 134 #define VX_W0_RESOURCE_CFG 0x08 135 #define VX_W0_ADDRESS_CFG 0x06 136 #define VX_W0_CONFIG_CTRL 0x04 137 /* Read */ 138 #define VX_W0_PRODUCT_ID 0x02 139 #define VX_W0_MFG_ID 0x00 140 141 /* 142 * Window 1 registers. Operating Set. 143 */ 144 /* Write */ 145 #define VX_W1_TX_PIO_WR_2 0x02 146 #define VX_W1_TX_PIO_WR_1 0x00 147 /* Read */ 148 #define VX_W1_FREE_TX 0x0c 149 #define VX_W1_TX_STATUS 0x0b /* byte */ 150 #define VX_W1_TIMER 0x0a /* byte */ 151 #define VX_W1_RX_STATUS 0x08 152 #define VX_W1_RX_PIO_RD_2 0x02 153 #define VX_W1_RX_PIO_RD_1 0x00 154 155 /* 156 * Window 2 registers. Station Address Setup/Read 157 */ 158 /* Read/Write */ 159 #define VX_W2_ADDR_5 0x05 160 #define VX_W2_ADDR_4 0x04 161 #define VX_W2_ADDR_3 0x03 162 #define VX_W2_ADDR_2 0x02 163 #define VX_W2_ADDR_1 0x01 164 #define VX_W2_ADDR_0 0x00 165 166 /* 167 * Window 3 registers. FIFO Management. 168 */ 169 /* Read */ 170 #define VX_W3_INTERNAL_CFG 0x00 171 #define VX_W3_RESET_OPT 0x08 172 #define VX_W3_FREE_TX 0x0c 173 #define VX_W3_FREE_RX 0x0a 174 175 /* 176 * Window 4 registers. Diagnostics. 177 */ 178 /* Read/Write */ 179 #define VX_W4_MEDIA_TYPE 0x0a 180 #define VX_W4_CTRLR_STATUS 0x08 181 #define VX_W4_NET_DIAG 0x06 182 #define VX_W4_FIFO_DIAG 0x04 183 #define VX_W4_HOST_DIAG 0x02 184 #define VX_W4_TX_DIAG 0x00 185 186 /* 187 * Window 5 Registers. Results and Internal status. 188 */ 189 /* Read */ 190 #define VX_W5_READ_0_MASK 0x0c 191 #define VX_W5_INTR_MASK 0x0a 192 #define VX_W5_RX_FILTER 0x08 193 #define VX_W5_RX_EARLY_THRESH 0x06 194 #define VX_W5_TX_AVAIL_THRESH 0x02 195 #define VX_W5_TX_START_THRESH 0x00 196 197 /* 198 * Window 6 registers. Statistics. 199 */ 200 /* Read/Write */ 201 #define TX_TOTAL_OK 0x0c 202 #define RX_TOTAL_OK 0x0a 203 #define TX_DEFERRALS 0x08 204 #define RX_FRAMES_OK 0x07 205 #define TX_FRAMES_OK 0x06 206 #define RX_OVERRUNS 0x05 207 #define TX_COLLISIONS 0x04 208 #define TX_AFTER_1_COLLISION 0x03 209 #define TX_AFTER_X_COLLISIONS 0x02 210 #define TX_NO_SQE 0x01 211 #define TX_CD_LOST 0x00 212 213 /**************************************** 214 * 215 * Register definitions. 216 * 217 ****************************************/ 218 219 /* 220 * Command register. All windows. 221 * 222 * 16 bit register. 223 * 15-11: 5-bit code for command to be executed. 224 * 10-0: 11-bit arg if any. For commands with no args; 225 * this can be set to anything. 226 */ 227 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 228 * after issuing */ 229 #define WINDOW_SELECT (u_short) (0x1<<11) 230 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 231 * determine whether 232 * this is needed. If 233 * so; wait 800 uSec 234 * before using trans- 235 * ceiver. */ 236 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 237 * power-up */ 238 #define RX_ENABLE (u_short) (0x4<<11) 239 #define RX_RESET (u_short) (0x5<<11) 240 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 241 #define TX_ENABLE (u_short) (0x9<<11) 242 #define TX_DISABLE (u_short) (0xa<<11) 243 #define TX_RESET (u_short) (0xb<<11) 244 #define REQ_INTR (u_short) (0xc<<11) 245 /* 246 * The following C_* acknowledge the various interrupts. Some of them don't 247 * do anything. See the manual. 248 */ 249 #define ACK_INTR (u_short) (0x6800) 250 # define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 251 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 252 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 253 # define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 254 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 255 # define C_RX_EARLY (u_short) (ACK_INTR|0x20) 256 # define C_INT_RQD (u_short) (ACK_INTR|0x40) 257 # define C_UPD_STATS (u_short) (ACK_INTR|0x80) 258 #define SET_INTR_MASK (u_short) (0xe<<11) 259 #define SET_RD_0_MASK (u_short) (0xf<<11) 260 #define SET_RX_FILTER (u_short) (0x10<<11) 261 # define FIL_INDIVIDUAL (u_short) (0x1) 262 # define FIL_MULTICAST (u_short) (0x02) 263 # define FIL_BRDCST (u_short) (0x04) 264 # define FIL_PROMISC (u_short) (0x08) 265 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 266 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 267 #define SET_TX_START_THRESH (u_short) (0x13<<11) 268 #define STATS_ENABLE (u_short) (0x15<<11) 269 #define STATS_DISABLE (u_short) (0x16<<11) 270 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 271 272 /* 273 * Status register. All windows. 274 * 275 * 15-13: Window number(0-7). 276 * 12: Command_in_progress. 277 * 11: reserved. 278 * 10: reserved. 279 * 9: reserved. 280 * 8: reserved. 281 * 7: Update Statistics. 282 * 6: Interrupt Requested. 283 * 5: RX Early. 284 * 4: RX Complete. 285 * 3: TX Available. 286 * 2: TX Complete. 287 * 1: Adapter Failure. 288 * 0: Interrupt Latch. 289 */ 290 #define S_INTR_LATCH (u_short) (0x1) 291 #define S_CARD_FAILURE (u_short) (0x2) 292 #define S_TX_COMPLETE (u_short) (0x4) 293 #define S_TX_AVAIL (u_short) (0x8) 294 #define S_RX_COMPLETE (u_short) (0x10) 295 #define S_RX_EARLY (u_short) (0x20) 296 #define S_INT_RQD (u_short) (0x40) 297 #define S_UPD_STATS (u_short) (0x80) 298 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 299 300 #define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS) 301 302 /* Address Config. Register. 303 * Window 0/Port 06 304 */ 305 306 #define ACF_CONNECTOR_BITS 14 307 #define ACF_CONNECTOR_UTP 0 308 #define ACF_CONNECTOR_AUI 1 309 #define ACF_CONNECTOR_BNC 3 310 311 #define INTERNAL_CONNECTOR_BITS 20 312 #define INTERNAL_CONNECTOR_MASK 0x01700000 313 314 /* 315 * FIFO Registers. RX Status. 316 * 317 * 15: Incomplete or FIFO empty. 318 * 14: 1: Error in RX Packet 0: Incomplete or no error. 319 * 13-11: Type of error. 320 * 1000 = Overrun. 321 * 1011 = Run Packet Error. 322 * 1100 = Alignment Error. 323 * 1101 = CRC Error. 324 * 1001 = Oversize Packet Error (>1514 bytes) 325 * 0010 = Dribble Bits. 326 * (all other error codes, no errors.) 327 * 328 * 10-0: RX Bytes (0-1514) 329 */ 330 #define ERR_INCOMPLETE (u_short) (0x8000) 331 #define ERR_RX (u_short) (0x4000) 332 #define ERR_MASK (u_short) (0x7800) 333 #define ERR_OVERRUN (u_short) (0x4000) 334 #define ERR_RUNT (u_short) (0x5800) 335 #define ERR_ALIGNMENT (u_short) (0x6000) 336 #define ERR_CRC (u_short) (0x6800) 337 #define ERR_OVERSIZE (u_short) (0x4800) 338 #define ERR_DRIBBLE (u_short) (0x1000) 339 340 /* 341 * TX Status. 342 * 343 * Reports the transmit status of a completed transmission. Writing this 344 * register pops the transmit completion stack. 345 * 346 * Window 1/Port 0x0b. 347 * 348 * 7: Complete 349 * 6: Interrupt on successful transmission requested. 350 * 5: Jabber Error (TP Only, TX Reset required. ) 351 * 4: Underrun (TX Reset required. ) 352 * 3: Maximum Collisions. 353 * 2: TX Status Overflow. 354 * 1-0: Undefined. 355 * 356 */ 357 #define TXS_COMPLETE 0x80 358 #define TXS_INTR_REQ 0x40 359 #define TXS_JABBER 0x20 360 #define TXS_UNDERRUN 0x10 361 #define TXS_MAX_COLLISION 0x8 362 #define TXS_STATUS_OVERFLOW 0x4 363 364 #define RS_AUI (1<<5) 365 #define RS_BNC (1<<4) 366 #define RS_UTP (1<<3) 367 #define RS_T4 (1<<0) 368 #define RS_TX (1<<1) 369 #define RS_FX (1<<2) 370 #define RS_MII (1<<6) 371 372 373 /* 374 * FIFO Status (Window 4) 375 * 376 * Supports FIFO diagnostics 377 * 378 * Window 4/Port 0x04.1 379 * 380 * 15: 1=RX receiving (RO). Set when a packet is being received 381 * into the RX FIFO. 382 * 14: Reserved 383 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 384 * Requires RX Reset or Global Reset command to recover. 385 * It is generated when you read past the end of a packet - 386 * reading past what has been received so far will give bad 387 * data. 388 * 12: 1=RX status overrun (RO). Set when there are already 8 389 * packets in the RX FIFO. While this bit is set, no additional 390 * packets are received. Requires no action on the part of 391 * the host. The condition is cleared once a packet has been 392 * read out of the RX FIFO. 393 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 394 * may not be an overrun packet yet). While this bit is set, 395 * no additional packets will be received (some additional 396 * bytes can still be pending between the wire and the RX 397 * FIFO). Requires no action on the part of the host. The 398 * condition is cleared once a few bytes have been read out 399 * from the RX FIFO. 400 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 401 * Requires TX Reset or Global Reset command to recover. 402 * Disables Transmitter. 403 * 9-8: Unassigned. 404 * 7-0: Built in self test bits for the RX and TX FIFO's. 405 */ 406 #define FIFOS_RX_RECEIVING (u_short) 0x8000 407 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 408 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 409 #define FIFOS_RX_OVERRUN (u_short) 0x0800 410 #define FIFOS_TX_OVERRUN (u_short) 0x0400 411 412 /* 413 * Misc defines for various things. 414 */ 415 #define TAG_ADAPTER 0xd0 416 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 417 #define ENABLE_DRQ_IRQ 0x0001 418 #define MFG_ID 0x506d /* `TCM' */ 419 #define PROD_ID 0x5090 420 #define JABBER_GUARD_ENABLE 0x40 421 #define LINKBEAT_ENABLE 0x80 422 #define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 423 #define DISABLE_UTP 0x0 424 #define RX_BYTES_MASK (u_short) (0x07ff) 425 #define TX_INDICATE 1<<15 426 427 #define VX_IOSIZE 0x20 428 429 #define VX_CONNECTORS 8
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