Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/wb/if_wb.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/sockio.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/module.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/queue.h> 95 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_types.h> 102 103 #include <net/bpf.h> 104 105 #include <vm/vm.h> /* for vtophys */ 106 #include <vm/pmap.h> /* for vtophys */ 107 #include <machine/bus.h> 108 #include <machine/resource.h> 109 #include <sys/bus.h> 110 #include <sys/rman.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/mii_bitbang.h> 117 #include <dev/mii/miivar.h> 118 119 /* "device miibus" required. See GENERIC if you get errors here. */ 120 #include "miibus_if.h" 121 122 #define WB_USEIOSPACE 123 124 #include <dev/wb/if_wbreg.h> 125 126 MODULE_DEPEND(wb, pci, 1, 1, 1); 127 MODULE_DEPEND(wb, ether, 1, 1, 1); 128 MODULE_DEPEND(wb, miibus, 1, 1, 1); 129 130 /* 131 * Various supported device vendors/types and their names. 132 */ 133 static const struct wb_type wb_devs[] = { 134 { WB_VENDORID, WB_DEVICEID_840F, 135 "Winbond W89C840F 10/100BaseTX" }, 136 { CP_VENDORID, CP_DEVICEID_RL100, 137 "Compex RL100-ATX 10/100baseTX" }, 138 { 0, 0, NULL } 139 }; 140 141 static int wb_probe(device_t); 142 static int wb_attach(device_t); 143 static int wb_detach(device_t); 144 145 static int wb_bfree(struct mbuf *, void *addr, void *args); 146 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 147 struct mbuf *); 148 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 149 150 static void wb_rxeof(struct wb_softc *); 151 static void wb_rxeoc(struct wb_softc *); 152 static void wb_txeof(struct wb_softc *); 153 static void wb_txeoc(struct wb_softc *); 154 static void wb_intr(void *); 155 static void wb_tick(void *); 156 static void wb_start(struct ifnet *); 157 static void wb_start_locked(struct ifnet *); 158 static int wb_ioctl(struct ifnet *, u_long, caddr_t); 159 static void wb_init(void *); 160 static void wb_init_locked(struct wb_softc *); 161 static void wb_stop(struct wb_softc *); 162 static void wb_watchdog(struct wb_softc *); 163 static int wb_shutdown(device_t); 164 static int wb_ifmedia_upd(struct ifnet *); 165 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 167 static void wb_eeprom_putbyte(struct wb_softc *, int); 168 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 169 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 170 171 static void wb_setcfg(struct wb_softc *, u_int32_t); 172 static void wb_setmulti(struct wb_softc *); 173 static void wb_reset(struct wb_softc *); 174 static void wb_fixmedia(struct wb_softc *); 175 static int wb_list_rx_init(struct wb_softc *); 176 static int wb_list_tx_init(struct wb_softc *); 177 178 static int wb_miibus_readreg(device_t, int, int); 179 static int wb_miibus_writereg(device_t, int, int, int); 180 static void wb_miibus_statchg(device_t); 181 182 /* 183 * MII bit-bang glue 184 */ 185 static uint32_t wb_mii_bitbang_read(device_t); 186 static void wb_mii_bitbang_write(device_t, uint32_t); 187 188 static const struct mii_bitbang_ops wb_mii_bitbang_ops = { 189 wb_mii_bitbang_read, 190 wb_mii_bitbang_write, 191 { 192 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 193 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */ 194 WB_SIO_MII_CLK, /* MII_BIT_MDC */ 195 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 196 0, /* MII_BIT_DIR_PHY_HOST */ 197 } 198 }; 199 200 #ifdef WB_USEIOSPACE 201 #define WB_RES SYS_RES_IOPORT 202 #define WB_RID WB_PCI_LOIO 203 #else 204 #define WB_RES SYS_RES_MEMORY 205 #define WB_RID WB_PCI_LOMEM 206 #endif 207 208 static device_method_t wb_methods[] = { 209 /* Device interface */ 210 DEVMETHOD(device_probe, wb_probe), 211 DEVMETHOD(device_attach, wb_attach), 212 DEVMETHOD(device_detach, wb_detach), 213 DEVMETHOD(device_shutdown, wb_shutdown), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 217 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 218 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 219 220 DEVMETHOD_END 221 }; 222 223 static driver_t wb_driver = { 224 "wb", 225 wb_methods, 226 sizeof(struct wb_softc) 227 }; 228 229 static devclass_t wb_devclass; 230 231 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 232 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 233 234 #define WB_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | (x)) 237 238 #define WB_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~(x)) 241 242 #define SIO_SET(x) \ 243 CSR_WRITE_4(sc, WB_SIO, \ 244 CSR_READ_4(sc, WB_SIO) | (x)) 245 246 #define SIO_CLR(x) \ 247 CSR_WRITE_4(sc, WB_SIO, \ 248 CSR_READ_4(sc, WB_SIO) & ~(x)) 249 250 /* 251 * Send a read command and address to the EEPROM, check for ACK. 252 */ 253 static void 254 wb_eeprom_putbyte(sc, addr) 255 struct wb_softc *sc; 256 int addr; 257 { 258 register int d, i; 259 260 d = addr | WB_EECMD_READ; 261 262 /* 263 * Feed in each bit and stobe the clock. 264 */ 265 for (i = 0x400; i; i >>= 1) { 266 if (d & i) { 267 SIO_SET(WB_SIO_EE_DATAIN); 268 } else { 269 SIO_CLR(WB_SIO_EE_DATAIN); 270 } 271 DELAY(100); 272 SIO_SET(WB_SIO_EE_CLK); 273 DELAY(150); 274 SIO_CLR(WB_SIO_EE_CLK); 275 DELAY(100); 276 } 277 } 278 279 /* 280 * Read a word of data stored in the EEPROM at address 'addr.' 281 */ 282 static void 283 wb_eeprom_getword(sc, addr, dest) 284 struct wb_softc *sc; 285 int addr; 286 u_int16_t *dest; 287 { 288 register int i; 289 u_int16_t word = 0; 290 291 /* Enter EEPROM access mode. */ 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Send address of word we want to read. 296 */ 297 wb_eeprom_putbyte(sc, addr); 298 299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 300 301 /* 302 * Start reading bits from EEPROM. 303 */ 304 for (i = 0x8000; i; i >>= 1) { 305 SIO_SET(WB_SIO_EE_CLK); 306 DELAY(100); 307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 308 word |= i; 309 SIO_CLR(WB_SIO_EE_CLK); 310 DELAY(100); 311 } 312 313 /* Turn off EEPROM access mode. */ 314 CSR_WRITE_4(sc, WB_SIO, 0); 315 316 *dest = word; 317 } 318 319 /* 320 * Read a sequence of words from the EEPROM. 321 */ 322 static void 323 wb_read_eeprom(sc, dest, off, cnt, swap) 324 struct wb_softc *sc; 325 caddr_t dest; 326 int off; 327 int cnt; 328 int swap; 329 { 330 int i; 331 u_int16_t word = 0, *ptr; 332 333 for (i = 0; i < cnt; i++) { 334 wb_eeprom_getword(sc, off + i, &word); 335 ptr = (u_int16_t *)(dest + (i * 2)); 336 if (swap) 337 *ptr = ntohs(word); 338 else 339 *ptr = word; 340 } 341 } 342 343 /* 344 * Read the MII serial port for the MII bit-bang module. 345 */ 346 static uint32_t 347 wb_mii_bitbang_read(device_t dev) 348 { 349 struct wb_softc *sc; 350 uint32_t val; 351 352 sc = device_get_softc(dev); 353 354 val = CSR_READ_4(sc, WB_SIO); 355 CSR_BARRIER(sc, WB_SIO, 4, 356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 357 358 return (val); 359 } 360 361 /* 362 * Write the MII serial port for the MII bit-bang module. 363 */ 364 static void 365 wb_mii_bitbang_write(device_t dev, uint32_t val) 366 { 367 struct wb_softc *sc; 368 369 sc = device_get_softc(dev); 370 371 CSR_WRITE_4(sc, WB_SIO, val); 372 CSR_BARRIER(sc, WB_SIO, 4, 373 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 374 } 375 376 static int 377 wb_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380 { 381 382 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg)); 383 } 384 385 static int 386 wb_miibus_writereg(dev, phy, reg, data) 387 device_t dev; 388 int phy, reg, data; 389 { 390 391 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data); 392 393 return(0); 394 } 395 396 static void 397 wb_miibus_statchg(dev) 398 device_t dev; 399 { 400 struct wb_softc *sc; 401 struct mii_data *mii; 402 403 sc = device_get_softc(dev); 404 mii = device_get_softc(sc->wb_miibus); 405 wb_setcfg(sc, mii->mii_media_active); 406 } 407 408 /* 409 * Program the 64-bit multicast hash filter. 410 */ 411 static void 412 wb_setmulti(sc) 413 struct wb_softc *sc; 414 { 415 struct ifnet *ifp; 416 int h = 0; 417 u_int32_t hashes[2] = { 0, 0 }; 418 struct ifmultiaddr *ifma; 419 u_int32_t rxfilt; 420 int mcnt = 0; 421 422 ifp = sc->wb_ifp; 423 424 rxfilt = CSR_READ_4(sc, WB_NETCFG); 425 426 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 427 rxfilt |= WB_NETCFG_RX_MULTI; 428 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 429 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 430 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 431 return; 432 } 433 434 /* first, zot all the existing hash bits */ 435 CSR_WRITE_4(sc, WB_MAR0, 0); 436 CSR_WRITE_4(sc, WB_MAR1, 0); 437 438 /* now program new ones */ 439 if_maddr_rlock(ifp); 440 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 441 if (ifma->ifma_addr->sa_family != AF_LINK) 442 continue; 443 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 444 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 445 if (h < 32) 446 hashes[0] |= (1 << h); 447 else 448 hashes[1] |= (1 << (h - 32)); 449 mcnt++; 450 } 451 if_maddr_runlock(ifp); 452 453 if (mcnt) 454 rxfilt |= WB_NETCFG_RX_MULTI; 455 else 456 rxfilt &= ~WB_NETCFG_RX_MULTI; 457 458 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 459 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 460 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 461 } 462 463 /* 464 * The Winbond manual states that in order to fiddle with the 465 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 466 * first have to put the transmit and/or receive logic in the idle state. 467 */ 468 static void 469 wb_setcfg(sc, media) 470 struct wb_softc *sc; 471 u_int32_t media; 472 { 473 int i, restart = 0; 474 475 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 476 restart = 1; 477 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 478 479 for (i = 0; i < WB_TIMEOUT; i++) { 480 DELAY(10); 481 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 482 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 483 break; 484 } 485 486 if (i == WB_TIMEOUT) 487 device_printf(sc->wb_dev, 488 "failed to force tx and rx to idle state\n"); 489 } 490 491 if (IFM_SUBTYPE(media) == IFM_10_T) 492 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 493 else 494 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 495 496 if ((media & IFM_GMASK) == IFM_FDX) 497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 498 else 499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 500 501 if (restart) 502 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 503 } 504 505 static void 506 wb_reset(sc) 507 struct wb_softc *sc; 508 { 509 register int i; 510 struct mii_data *mii; 511 struct mii_softc *miisc; 512 513 CSR_WRITE_4(sc, WB_NETCFG, 0); 514 CSR_WRITE_4(sc, WB_BUSCTL, 0); 515 CSR_WRITE_4(sc, WB_TXADDR, 0); 516 CSR_WRITE_4(sc, WB_RXADDR, 0); 517 518 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 519 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 520 521 for (i = 0; i < WB_TIMEOUT; i++) { 522 DELAY(10); 523 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 524 break; 525 } 526 if (i == WB_TIMEOUT) 527 device_printf(sc->wb_dev, "reset never completed!\n"); 528 529 /* Wait a little while for the chip to get its brains in order. */ 530 DELAY(1000); 531 532 if (sc->wb_miibus == NULL) 533 return; 534 535 mii = device_get_softc(sc->wb_miibus); 536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 537 PHY_RESET(miisc); 538 } 539 540 static void 541 wb_fixmedia(sc) 542 struct wb_softc *sc; 543 { 544 struct mii_data *mii = NULL; 545 struct ifnet *ifp; 546 u_int32_t media; 547 548 mii = device_get_softc(sc->wb_miibus); 549 ifp = sc->wb_ifp; 550 551 mii_pollstat(mii); 552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 553 media = mii->mii_media_active & ~IFM_10_T; 554 media |= IFM_100_TX; 555 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 556 media = mii->mii_media_active & ~IFM_100_TX; 557 media |= IFM_10_T; 558 } else 559 return; 560 561 ifmedia_set(&mii->mii_media, media); 562 } 563 564 /* 565 * Probe for a Winbond chip. Check the PCI vendor and device 566 * IDs against our list and return a device name if we find a match. 567 */ 568 static int 569 wb_probe(dev) 570 device_t dev; 571 { 572 const struct wb_type *t; 573 574 t = wb_devs; 575 576 while(t->wb_name != NULL) { 577 if ((pci_get_vendor(dev) == t->wb_vid) && 578 (pci_get_device(dev) == t->wb_did)) { 579 device_set_desc(dev, t->wb_name); 580 return (BUS_PROBE_DEFAULT); 581 } 582 t++; 583 } 584 585 return(ENXIO); 586 } 587 588 /* 589 * Attach the interface. Allocate softc structures, do ifmedia 590 * setup and ethernet/BPF attach. 591 */ 592 static int 593 wb_attach(dev) 594 device_t dev; 595 { 596 u_char eaddr[ETHER_ADDR_LEN]; 597 struct wb_softc *sc; 598 struct ifnet *ifp; 599 int error = 0, rid; 600 601 sc = device_get_softc(dev); 602 sc->wb_dev = dev; 603 604 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 605 MTX_DEF); 606 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 607 608 /* 609 * Map control/status registers. 610 */ 611 pci_enable_busmaster(dev); 612 613 rid = WB_RID; 614 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 615 616 if (sc->wb_res == NULL) { 617 device_printf(dev, "couldn't map ports/memory\n"); 618 error = ENXIO; 619 goto fail; 620 } 621 622 /* Allocate interrupt */ 623 rid = 0; 624 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 625 RF_SHAREABLE | RF_ACTIVE); 626 627 if (sc->wb_irq == NULL) { 628 device_printf(dev, "couldn't map interrupt\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 633 /* Save the cache line size. */ 634 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 635 636 /* Reset the adapter. */ 637 wb_reset(sc); 638 639 /* 640 * Get station address from the EEPROM. 641 */ 642 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 643 644 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 645 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 646 647 if (sc->wb_ldata == NULL) { 648 device_printf(dev, "no memory for list buffers!\n"); 649 error = ENXIO; 650 goto fail; 651 } 652 653 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 654 655 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 656 if (ifp == NULL) { 657 device_printf(dev, "can not if_alloc()\n"); 658 error = ENOSPC; 659 goto fail; 660 } 661 ifp->if_softc = sc; 662 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 663 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 664 ifp->if_ioctl = wb_ioctl; 665 ifp->if_start = wb_start; 666 ifp->if_init = wb_init; 667 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 668 669 /* 670 * Do MII setup. 671 */ 672 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 673 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 674 if (error != 0) { 675 device_printf(dev, "attaching PHYs failed\n"); 676 goto fail; 677 } 678 679 /* 680 * Call MI attach routine. 681 */ 682 ether_ifattach(ifp, eaddr); 683 684 /* Hook interrupt last to avoid having to lock softc */ 685 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 686 NULL, wb_intr, sc, &sc->wb_intrhand); 687 688 if (error) { 689 device_printf(dev, "couldn't set up irq\n"); 690 ether_ifdetach(ifp); 691 goto fail; 692 } 693 694 fail: 695 if (error) 696 wb_detach(dev); 697 698 return(error); 699 } 700 701 /* 702 * Shutdown hardware and free up resources. This can be called any 703 * time after the mutex has been initialized. It is called in both 704 * the error case in attach and the normal detach case so it needs 705 * to be careful about only freeing resources that have actually been 706 * allocated. 707 */ 708 static int 709 wb_detach(dev) 710 device_t dev; 711 { 712 struct wb_softc *sc; 713 struct ifnet *ifp; 714 715 sc = device_get_softc(dev); 716 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 717 ifp = sc->wb_ifp; 718 719 /* 720 * Delete any miibus and phy devices attached to this interface. 721 * This should only be done if attach succeeded. 722 */ 723 if (device_is_attached(dev)) { 724 ether_ifdetach(ifp); 725 WB_LOCK(sc); 726 wb_stop(sc); 727 WB_UNLOCK(sc); 728 callout_drain(&sc->wb_stat_callout); 729 } 730 if (sc->wb_miibus) 731 device_delete_child(dev, sc->wb_miibus); 732 bus_generic_detach(dev); 733 734 if (sc->wb_intrhand) 735 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 736 if (sc->wb_irq) 737 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 738 if (sc->wb_res) 739 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 740 741 if (ifp) 742 if_free(ifp); 743 744 if (sc->wb_ldata) { 745 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 746 M_DEVBUF); 747 } 748 749 mtx_destroy(&sc->wb_mtx); 750 751 return(0); 752 } 753 754 /* 755 * Initialize the transmit descriptors. 756 */ 757 static int 758 wb_list_tx_init(sc) 759 struct wb_softc *sc; 760 { 761 struct wb_chain_data *cd; 762 struct wb_list_data *ld; 763 int i; 764 765 cd = &sc->wb_cdata; 766 ld = sc->wb_ldata; 767 768 for (i = 0; i < WB_TX_LIST_CNT; i++) { 769 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 770 if (i == (WB_TX_LIST_CNT - 1)) { 771 cd->wb_tx_chain[i].wb_nextdesc = 772 &cd->wb_tx_chain[0]; 773 } else { 774 cd->wb_tx_chain[i].wb_nextdesc = 775 &cd->wb_tx_chain[i + 1]; 776 } 777 } 778 779 cd->wb_tx_free = &cd->wb_tx_chain[0]; 780 cd->wb_tx_tail = cd->wb_tx_head = NULL; 781 782 return(0); 783 } 784 785 786 /* 787 * Initialize the RX descriptors and allocate mbufs for them. Note that 788 * we arrange the descriptors in a closed ring, so that the last descriptor 789 * points back to the first. 790 */ 791 static int 792 wb_list_rx_init(sc) 793 struct wb_softc *sc; 794 { 795 struct wb_chain_data *cd; 796 struct wb_list_data *ld; 797 int i; 798 799 cd = &sc->wb_cdata; 800 ld = sc->wb_ldata; 801 802 for (i = 0; i < WB_RX_LIST_CNT; i++) { 803 cd->wb_rx_chain[i].wb_ptr = 804 (struct wb_desc *)&ld->wb_rx_list[i]; 805 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 806 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 807 return(ENOBUFS); 808 if (i == (WB_RX_LIST_CNT - 1)) { 809 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 810 ld->wb_rx_list[i].wb_next = 811 vtophys(&ld->wb_rx_list[0]); 812 } else { 813 cd->wb_rx_chain[i].wb_nextdesc = 814 &cd->wb_rx_chain[i + 1]; 815 ld->wb_rx_list[i].wb_next = 816 vtophys(&ld->wb_rx_list[i + 1]); 817 } 818 } 819 820 cd->wb_rx_head = &cd->wb_rx_chain[0]; 821 822 return(0); 823 } 824 825 static int 826 wb_bfree(struct mbuf *m, void *buf, void *args) 827 { 828 829 return (EXT_FREE_OK); 830 } 831 832 /* 833 * Initialize an RX descriptor and attach an MBUF cluster. 834 */ 835 static int 836 wb_newbuf(sc, c, m) 837 struct wb_softc *sc; 838 struct wb_chain_onefrag *c; 839 struct mbuf *m; 840 { 841 struct mbuf *m_new = NULL; 842 843 if (m == NULL) { 844 MGETHDR(m_new, M_NOWAIT, MT_DATA); 845 if (m_new == NULL) 846 return(ENOBUFS); 847 m_new->m_data = c->wb_buf; 848 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 849 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 850 NULL, 0, EXT_NET_DRV); 851 } else { 852 m_new = m; 853 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 854 m_new->m_data = m_new->m_ext.ext_buf; 855 } 856 857 m_adj(m_new, sizeof(u_int64_t)); 858 859 c->wb_mbuf = m_new; 860 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 861 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 862 c->wb_ptr->wb_status = WB_RXSTAT; 863 864 return(0); 865 } 866 867 /* 868 * A frame has been uploaded: pass the resulting mbuf chain up to 869 * the higher level protocols. 870 */ 871 static void 872 wb_rxeof(sc) 873 struct wb_softc *sc; 874 { 875 struct mbuf *m = NULL; 876 struct ifnet *ifp; 877 struct wb_chain_onefrag *cur_rx; 878 int total_len = 0; 879 u_int32_t rxstat; 880 881 WB_LOCK_ASSERT(sc); 882 883 ifp = sc->wb_ifp; 884 885 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 886 WB_RXSTAT_OWN)) { 887 struct mbuf *m0 = NULL; 888 889 cur_rx = sc->wb_cdata.wb_rx_head; 890 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 891 892 m = cur_rx->wb_mbuf; 893 894 if ((rxstat & WB_RXSTAT_MIIERR) || 895 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 896 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 897 !(rxstat & WB_RXSTAT_LASTFRAG) || 898 !(rxstat & WB_RXSTAT_RXCMP)) { 899 ifp->if_ierrors++; 900 wb_newbuf(sc, cur_rx, m); 901 device_printf(sc->wb_dev, 902 "receiver babbling: possible chip bug," 903 " forcing reset\n"); 904 wb_fixmedia(sc); 905 wb_reset(sc); 906 wb_init_locked(sc); 907 return; 908 } 909 910 if (rxstat & WB_RXSTAT_RXERR) { 911 ifp->if_ierrors++; 912 wb_newbuf(sc, cur_rx, m); 913 break; 914 } 915 916 /* No errors; receive the packet. */ 917 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 918 919 /* 920 * XXX The Winbond chip includes the CRC with every 921 * received frame, and there's no way to turn this 922 * behavior off (at least, I can't find anything in 923 * the manual that explains how to do it) so we have 924 * to trim off the CRC manually. 925 */ 926 total_len -= ETHER_CRC_LEN; 927 928 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 929 NULL); 930 wb_newbuf(sc, cur_rx, m); 931 if (m0 == NULL) { 932 ifp->if_ierrors++; 933 break; 934 } 935 m = m0; 936 937 ifp->if_ipackets++; 938 WB_UNLOCK(sc); 939 (*ifp->if_input)(ifp, m); 940 WB_LOCK(sc); 941 } 942 } 943 944 static void 945 wb_rxeoc(sc) 946 struct wb_softc *sc; 947 { 948 wb_rxeof(sc); 949 950 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 951 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 952 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 953 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 954 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 955 } 956 957 /* 958 * A frame was downloaded to the chip. It's safe for us to clean up 959 * the list buffers. 960 */ 961 static void 962 wb_txeof(sc) 963 struct wb_softc *sc; 964 { 965 struct wb_chain *cur_tx; 966 struct ifnet *ifp; 967 968 ifp = sc->wb_ifp; 969 970 /* Clear the timeout timer. */ 971 sc->wb_timer = 0; 972 973 if (sc->wb_cdata.wb_tx_head == NULL) 974 return; 975 976 /* 977 * Go through our tx list and free mbufs for those 978 * frames that have been transmitted. 979 */ 980 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 981 u_int32_t txstat; 982 983 cur_tx = sc->wb_cdata.wb_tx_head; 984 txstat = WB_TXSTATUS(cur_tx); 985 986 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 987 break; 988 989 if (txstat & WB_TXSTAT_TXERR) { 990 ifp->if_oerrors++; 991 if (txstat & WB_TXSTAT_ABORT) 992 ifp->if_collisions++; 993 if (txstat & WB_TXSTAT_LATECOLL) 994 ifp->if_collisions++; 995 } 996 997 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 998 999 ifp->if_opackets++; 1000 m_freem(cur_tx->wb_mbuf); 1001 cur_tx->wb_mbuf = NULL; 1002 1003 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1004 sc->wb_cdata.wb_tx_head = NULL; 1005 sc->wb_cdata.wb_tx_tail = NULL; 1006 break; 1007 } 1008 1009 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1010 } 1011 } 1012 1013 /* 1014 * TX 'end of channel' interrupt handler. 1015 */ 1016 static void 1017 wb_txeoc(sc) 1018 struct wb_softc *sc; 1019 { 1020 struct ifnet *ifp; 1021 1022 ifp = sc->wb_ifp; 1023 1024 sc->wb_timer = 0; 1025 1026 if (sc->wb_cdata.wb_tx_head == NULL) { 1027 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1028 sc->wb_cdata.wb_tx_tail = NULL; 1029 } else { 1030 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1031 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1032 sc->wb_timer = 5; 1033 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1034 } 1035 } 1036 } 1037 1038 static void 1039 wb_intr(arg) 1040 void *arg; 1041 { 1042 struct wb_softc *sc; 1043 struct ifnet *ifp; 1044 u_int32_t status; 1045 1046 sc = arg; 1047 WB_LOCK(sc); 1048 ifp = sc->wb_ifp; 1049 1050 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1051 WB_UNLOCK(sc); 1052 return; 1053 } 1054 1055 /* Disable interrupts. */ 1056 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1057 1058 for (;;) { 1059 1060 status = CSR_READ_4(sc, WB_ISR); 1061 if (status) 1062 CSR_WRITE_4(sc, WB_ISR, status); 1063 1064 if ((status & WB_INTRS) == 0) 1065 break; 1066 1067 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1068 ifp->if_ierrors++; 1069 wb_reset(sc); 1070 if (status & WB_ISR_RX_ERR) 1071 wb_fixmedia(sc); 1072 wb_init_locked(sc); 1073 continue; 1074 } 1075 1076 if (status & WB_ISR_RX_OK) 1077 wb_rxeof(sc); 1078 1079 if (status & WB_ISR_RX_IDLE) 1080 wb_rxeoc(sc); 1081 1082 if (status & WB_ISR_TX_OK) 1083 wb_txeof(sc); 1084 1085 if (status & WB_ISR_TX_NOBUF) 1086 wb_txeoc(sc); 1087 1088 if (status & WB_ISR_TX_IDLE) { 1089 wb_txeof(sc); 1090 if (sc->wb_cdata.wb_tx_head != NULL) { 1091 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1092 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1093 } 1094 } 1095 1096 if (status & WB_ISR_TX_UNDERRUN) { 1097 ifp->if_oerrors++; 1098 wb_txeof(sc); 1099 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1100 /* Jack up TX threshold */ 1101 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1102 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1103 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1104 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1105 } 1106 1107 if (status & WB_ISR_BUS_ERR) { 1108 wb_reset(sc); 1109 wb_init_locked(sc); 1110 } 1111 1112 } 1113 1114 /* Re-enable interrupts. */ 1115 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1116 1117 if (ifp->if_snd.ifq_head != NULL) { 1118 wb_start_locked(ifp); 1119 } 1120 1121 WB_UNLOCK(sc); 1122 } 1123 1124 static void 1125 wb_tick(xsc) 1126 void *xsc; 1127 { 1128 struct wb_softc *sc; 1129 struct mii_data *mii; 1130 1131 sc = xsc; 1132 WB_LOCK_ASSERT(sc); 1133 mii = device_get_softc(sc->wb_miibus); 1134 1135 mii_tick(mii); 1136 1137 if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1138 wb_watchdog(sc); 1139 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1140 } 1141 1142 /* 1143 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1144 * pointers to the fragment pointers. 1145 */ 1146 static int 1147 wb_encap(sc, c, m_head) 1148 struct wb_softc *sc; 1149 struct wb_chain *c; 1150 struct mbuf *m_head; 1151 { 1152 int frag = 0; 1153 struct wb_desc *f = NULL; 1154 int total_len; 1155 struct mbuf *m; 1156 1157 /* 1158 * Start packing the mbufs in this chain into 1159 * the fragment pointers. Stop when we run out 1160 * of fragments or hit the end of the mbuf chain. 1161 */ 1162 m = m_head; 1163 total_len = 0; 1164 1165 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1166 if (m->m_len != 0) { 1167 if (frag == WB_MAXFRAGS) 1168 break; 1169 total_len += m->m_len; 1170 f = &c->wb_ptr->wb_frag[frag]; 1171 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1172 if (frag == 0) { 1173 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1174 f->wb_status = 0; 1175 } else 1176 f->wb_status = WB_TXSTAT_OWN; 1177 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1178 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1179 frag++; 1180 } 1181 } 1182 1183 /* 1184 * Handle special case: we used up all 16 fragments, 1185 * but we have more mbufs left in the chain. Copy the 1186 * data into an mbuf cluster. Note that we don't 1187 * bother clearing the values in the other fragment 1188 * pointers/counters; it wouldn't gain us anything, 1189 * and would waste cycles. 1190 */ 1191 if (m != NULL) { 1192 struct mbuf *m_new = NULL; 1193 1194 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1195 if (m_new == NULL) 1196 return(1); 1197 if (m_head->m_pkthdr.len > MHLEN) { 1198 MCLGET(m_new, M_NOWAIT); 1199 if (!(m_new->m_flags & M_EXT)) { 1200 m_freem(m_new); 1201 return(1); 1202 } 1203 } 1204 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1205 mtod(m_new, caddr_t)); 1206 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1207 m_freem(m_head); 1208 m_head = m_new; 1209 f = &c->wb_ptr->wb_frag[0]; 1210 f->wb_status = 0; 1211 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1212 f->wb_ctl = total_len = m_new->m_len; 1213 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1214 frag = 1; 1215 } 1216 1217 if (total_len < WB_MIN_FRAMELEN) { 1218 f = &c->wb_ptr->wb_frag[frag]; 1219 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1220 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1221 f->wb_ctl |= WB_TXCTL_TLINK; 1222 f->wb_status = WB_TXSTAT_OWN; 1223 frag++; 1224 } 1225 1226 c->wb_mbuf = m_head; 1227 c->wb_lastdesc = frag - 1; 1228 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1229 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1230 1231 return(0); 1232 } 1233 1234 /* 1235 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1236 * to the mbuf data regions directly in the transmit lists. We also save a 1237 * copy of the pointers since the transmit list fragment pointers are 1238 * physical addresses. 1239 */ 1240 1241 static void 1242 wb_start(ifp) 1243 struct ifnet *ifp; 1244 { 1245 struct wb_softc *sc; 1246 1247 sc = ifp->if_softc; 1248 WB_LOCK(sc); 1249 wb_start_locked(ifp); 1250 WB_UNLOCK(sc); 1251 } 1252 1253 static void 1254 wb_start_locked(ifp) 1255 struct ifnet *ifp; 1256 { 1257 struct wb_softc *sc; 1258 struct mbuf *m_head = NULL; 1259 struct wb_chain *cur_tx = NULL, *start_tx; 1260 1261 sc = ifp->if_softc; 1262 WB_LOCK_ASSERT(sc); 1263 1264 /* 1265 * Check for an available queue slot. If there are none, 1266 * punt. 1267 */ 1268 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1269 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1270 return; 1271 } 1272 1273 start_tx = sc->wb_cdata.wb_tx_free; 1274 1275 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1276 IF_DEQUEUE(&ifp->if_snd, m_head); 1277 if (m_head == NULL) 1278 break; 1279 1280 /* Pick a descriptor off the free list. */ 1281 cur_tx = sc->wb_cdata.wb_tx_free; 1282 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1283 1284 /* Pack the data into the descriptor. */ 1285 wb_encap(sc, cur_tx, m_head); 1286 1287 if (cur_tx != start_tx) 1288 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1289 1290 /* 1291 * If there's a BPF listener, bounce a copy of this frame 1292 * to him. 1293 */ 1294 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1295 } 1296 1297 /* 1298 * If there are no packets queued, bail. 1299 */ 1300 if (cur_tx == NULL) 1301 return; 1302 1303 /* 1304 * Place the request for the upload interrupt 1305 * in the last descriptor in the chain. This way, if 1306 * we're chaining several packets at once, we'll only 1307 * get an interrupt once for the whole chain rather than 1308 * once for each packet. 1309 */ 1310 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1311 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1312 sc->wb_cdata.wb_tx_tail = cur_tx; 1313 1314 if (sc->wb_cdata.wb_tx_head == NULL) { 1315 sc->wb_cdata.wb_tx_head = start_tx; 1316 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1317 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1318 } else { 1319 /* 1320 * We need to distinguish between the case where 1321 * the own bit is clear because the chip cleared it 1322 * and where the own bit is clear because we haven't 1323 * set it yet. The magic value WB_UNSET is just some 1324 * ramdomly chosen number which doesn't have the own 1325 * bit set. When we actually transmit the frame, the 1326 * status word will have _only_ the own bit set, so 1327 * the txeoc handler will be able to tell if it needs 1328 * to initiate another transmission to flush out pending 1329 * frames. 1330 */ 1331 WB_TXOWN(start_tx) = WB_UNSENT; 1332 } 1333 1334 /* 1335 * Set a timeout in case the chip goes out to lunch. 1336 */ 1337 sc->wb_timer = 5; 1338 } 1339 1340 static void 1341 wb_init(xsc) 1342 void *xsc; 1343 { 1344 struct wb_softc *sc = xsc; 1345 1346 WB_LOCK(sc); 1347 wb_init_locked(sc); 1348 WB_UNLOCK(sc); 1349 } 1350 1351 static void 1352 wb_init_locked(sc) 1353 struct wb_softc *sc; 1354 { 1355 struct ifnet *ifp = sc->wb_ifp; 1356 int i; 1357 struct mii_data *mii; 1358 1359 WB_LOCK_ASSERT(sc); 1360 mii = device_get_softc(sc->wb_miibus); 1361 1362 /* 1363 * Cancel pending I/O and free all RX/TX buffers. 1364 */ 1365 wb_stop(sc); 1366 wb_reset(sc); 1367 1368 sc->wb_txthresh = WB_TXTHRESH_INIT; 1369 1370 /* 1371 * Set cache alignment and burst length. 1372 */ 1373 #ifdef foo 1374 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1375 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1376 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1377 #endif 1378 1379 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1380 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1381 switch(sc->wb_cachesize) { 1382 case 32: 1383 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1384 break; 1385 case 16: 1386 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1387 break; 1388 case 8: 1389 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1390 break; 1391 case 0: 1392 default: 1393 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1394 break; 1395 } 1396 1397 /* This doesn't tend to work too well at 100Mbps. */ 1398 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1399 1400 /* Init our MAC address */ 1401 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1402 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 1403 } 1404 1405 /* Init circular RX list. */ 1406 if (wb_list_rx_init(sc) == ENOBUFS) { 1407 device_printf(sc->wb_dev, 1408 "initialization failed: no memory for rx buffers\n"); 1409 wb_stop(sc); 1410 return; 1411 } 1412 1413 /* Init TX descriptors. */ 1414 wb_list_tx_init(sc); 1415 1416 /* If we want promiscuous mode, set the allframes bit. */ 1417 if (ifp->if_flags & IFF_PROMISC) { 1418 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1419 } else { 1420 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1421 } 1422 1423 /* 1424 * Set capture broadcast bit to capture broadcast frames. 1425 */ 1426 if (ifp->if_flags & IFF_BROADCAST) { 1427 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1428 } else { 1429 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1430 } 1431 1432 /* 1433 * Program the multicast filter, if necessary. 1434 */ 1435 wb_setmulti(sc); 1436 1437 /* 1438 * Load the address of the RX list. 1439 */ 1440 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1441 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1442 1443 /* 1444 * Enable interrupts. 1445 */ 1446 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1447 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1448 1449 /* Enable receiver and transmitter. */ 1450 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1451 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1452 1453 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1454 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1455 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1456 1457 mii_mediachg(mii); 1458 1459 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1460 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1461 1462 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1463 } 1464 1465 /* 1466 * Set media options. 1467 */ 1468 static int 1469 wb_ifmedia_upd(ifp) 1470 struct ifnet *ifp; 1471 { 1472 struct wb_softc *sc; 1473 1474 sc = ifp->if_softc; 1475 1476 WB_LOCK(sc); 1477 if (ifp->if_flags & IFF_UP) 1478 wb_init_locked(sc); 1479 WB_UNLOCK(sc); 1480 1481 return(0); 1482 } 1483 1484 /* 1485 * Report current media status. 1486 */ 1487 static void 1488 wb_ifmedia_sts(ifp, ifmr) 1489 struct ifnet *ifp; 1490 struct ifmediareq *ifmr; 1491 { 1492 struct wb_softc *sc; 1493 struct mii_data *mii; 1494 1495 sc = ifp->if_softc; 1496 1497 WB_LOCK(sc); 1498 mii = device_get_softc(sc->wb_miibus); 1499 1500 mii_pollstat(mii); 1501 ifmr->ifm_active = mii->mii_media_active; 1502 ifmr->ifm_status = mii->mii_media_status; 1503 WB_UNLOCK(sc); 1504 } 1505 1506 static int 1507 wb_ioctl(ifp, command, data) 1508 struct ifnet *ifp; 1509 u_long command; 1510 caddr_t data; 1511 { 1512 struct wb_softc *sc = ifp->if_softc; 1513 struct mii_data *mii; 1514 struct ifreq *ifr = (struct ifreq *) data; 1515 int error = 0; 1516 1517 switch(command) { 1518 case SIOCSIFFLAGS: 1519 WB_LOCK(sc); 1520 if (ifp->if_flags & IFF_UP) { 1521 wb_init_locked(sc); 1522 } else { 1523 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1524 wb_stop(sc); 1525 } 1526 WB_UNLOCK(sc); 1527 error = 0; 1528 break; 1529 case SIOCADDMULTI: 1530 case SIOCDELMULTI: 1531 WB_LOCK(sc); 1532 wb_setmulti(sc); 1533 WB_UNLOCK(sc); 1534 error = 0; 1535 break; 1536 case SIOCGIFMEDIA: 1537 case SIOCSIFMEDIA: 1538 mii = device_get_softc(sc->wb_miibus); 1539 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1540 break; 1541 default: 1542 error = ether_ioctl(ifp, command, data); 1543 break; 1544 } 1545 1546 return(error); 1547 } 1548 1549 static void 1550 wb_watchdog(sc) 1551 struct wb_softc *sc; 1552 { 1553 struct ifnet *ifp; 1554 1555 WB_LOCK_ASSERT(sc); 1556 ifp = sc->wb_ifp; 1557 ifp->if_oerrors++; 1558 if_printf(ifp, "watchdog timeout\n"); 1559 #ifdef foo 1560 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1561 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1562 #endif 1563 wb_stop(sc); 1564 wb_reset(sc); 1565 wb_init_locked(sc); 1566 1567 if (ifp->if_snd.ifq_head != NULL) 1568 wb_start_locked(ifp); 1569 } 1570 1571 /* 1572 * Stop the adapter and free any mbufs allocated to the 1573 * RX and TX lists. 1574 */ 1575 static void 1576 wb_stop(sc) 1577 struct wb_softc *sc; 1578 { 1579 register int i; 1580 struct ifnet *ifp; 1581 1582 WB_LOCK_ASSERT(sc); 1583 ifp = sc->wb_ifp; 1584 sc->wb_timer = 0; 1585 1586 callout_stop(&sc->wb_stat_callout); 1587 1588 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1589 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1590 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1591 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1592 1593 /* 1594 * Free data in the RX lists. 1595 */ 1596 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1597 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1598 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1599 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1600 } 1601 } 1602 bzero((char *)&sc->wb_ldata->wb_rx_list, 1603 sizeof(sc->wb_ldata->wb_rx_list)); 1604 1605 /* 1606 * Free the TX list buffers. 1607 */ 1608 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1609 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1610 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1611 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1612 } 1613 } 1614 1615 bzero((char *)&sc->wb_ldata->wb_tx_list, 1616 sizeof(sc->wb_ldata->wb_tx_list)); 1617 1618 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1619 } 1620 1621 /* 1622 * Stop all chip I/O so that the kernel's probe routines don't 1623 * get confused by errant DMAs when rebooting. 1624 */ 1625 static int 1626 wb_shutdown(dev) 1627 device_t dev; 1628 { 1629 struct wb_softc *sc; 1630 1631 sc = device_get_softc(dev); 1632 1633 WB_LOCK(sc); 1634 wb_stop(sc); 1635 WB_UNLOCK(sc); 1636 1637 return (0); 1638 }
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