FreeBSD/Linux Kernel Cross Reference
sys/dev/wb/if_wb.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Winbond fast ethernet PCI NIC driver
38 *
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
89 #include <sys/mbuf.h>
90 #include <sys/malloc.h>
91 #include <sys/module.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
95
96 #include <net/if.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102
103 #include <net/bpf.h>
104
105 #include <vm/vm.h> /* for vtophys */
106 #include <vm/pmap.h> /* for vtophys */
107 #include <machine/bus.h>
108 #include <machine/resource.h>
109 #include <sys/bus.h>
110 #include <sys/rman.h>
111
112 #include <dev/pci/pcireg.h>
113 #include <dev/pci/pcivar.h>
114
115 #include <dev/mii/mii.h>
116 #include <dev/mii/mii_bitbang.h>
117 #include <dev/mii/miivar.h>
118
119 /* "device miibus" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
121
122 #define WB_USEIOSPACE
123
124 #include <dev/wb/if_wbreg.h>
125
126 MODULE_DEPEND(wb, pci, 1, 1, 1);
127 MODULE_DEPEND(wb, ether, 1, 1, 1);
128 MODULE_DEPEND(wb, miibus, 1, 1, 1);
129
130 /*
131 * Various supported device vendors/types and their names.
132 */
133 static const struct wb_type wb_devs[] = {
134 { WB_VENDORID, WB_DEVICEID_840F,
135 "Winbond W89C840F 10/100BaseTX" },
136 { CP_VENDORID, CP_DEVICEID_RL100,
137 "Compex RL100-ATX 10/100baseTX" },
138 { 0, 0, NULL }
139 };
140
141 static int wb_probe(device_t);
142 static int wb_attach(device_t);
143 static int wb_detach(device_t);
144
145 static void wb_bfree(void *addr, void *args);
146 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
147 struct mbuf *);
148 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
149
150 static void wb_rxeof(struct wb_softc *);
151 static void wb_rxeoc(struct wb_softc *);
152 static void wb_txeof(struct wb_softc *);
153 static void wb_txeoc(struct wb_softc *);
154 static void wb_intr(void *);
155 static void wb_tick(void *);
156 static void wb_start(struct ifnet *);
157 static void wb_start_locked(struct ifnet *);
158 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
159 static void wb_init(void *);
160 static void wb_init_locked(struct wb_softc *);
161 static void wb_stop(struct wb_softc *);
162 static void wb_watchdog(struct wb_softc *);
163 static int wb_shutdown(device_t);
164 static int wb_ifmedia_upd(struct ifnet *);
165 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
166
167 static void wb_eeprom_putbyte(struct wb_softc *, int);
168 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
169 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
170
171 static void wb_setcfg(struct wb_softc *, u_int32_t);
172 static void wb_setmulti(struct wb_softc *);
173 static void wb_reset(struct wb_softc *);
174 static void wb_fixmedia(struct wb_softc *);
175 static int wb_list_rx_init(struct wb_softc *);
176 static int wb_list_tx_init(struct wb_softc *);
177
178 static int wb_miibus_readreg(device_t, int, int);
179 static int wb_miibus_writereg(device_t, int, int, int);
180 static void wb_miibus_statchg(device_t);
181
182 /*
183 * MII bit-bang glue
184 */
185 static uint32_t wb_mii_bitbang_read(device_t);
186 static void wb_mii_bitbang_write(device_t, uint32_t);
187
188 static const struct mii_bitbang_ops wb_mii_bitbang_ops = {
189 wb_mii_bitbang_read,
190 wb_mii_bitbang_write,
191 {
192 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */
193 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */
194 WB_SIO_MII_CLK, /* MII_BIT_MDC */
195 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
196 0, /* MII_BIT_DIR_PHY_HOST */
197 }
198 };
199
200 #ifdef WB_USEIOSPACE
201 #define WB_RES SYS_RES_IOPORT
202 #define WB_RID WB_PCI_LOIO
203 #else
204 #define WB_RES SYS_RES_MEMORY
205 #define WB_RID WB_PCI_LOMEM
206 #endif
207
208 static device_method_t wb_methods[] = {
209 /* Device interface */
210 DEVMETHOD(device_probe, wb_probe),
211 DEVMETHOD(device_attach, wb_attach),
212 DEVMETHOD(device_detach, wb_detach),
213 DEVMETHOD(device_shutdown, wb_shutdown),
214
215 /* MII interface */
216 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
217 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
218 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
219
220 DEVMETHOD_END
221 };
222
223 static driver_t wb_driver = {
224 "wb",
225 wb_methods,
226 sizeof(struct wb_softc)
227 };
228
229 static devclass_t wb_devclass;
230
231 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
232 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
233
234 #define WB_SETBIT(sc, reg, x) \
235 CSR_WRITE_4(sc, reg, \
236 CSR_READ_4(sc, reg) | (x))
237
238 #define WB_CLRBIT(sc, reg, x) \
239 CSR_WRITE_4(sc, reg, \
240 CSR_READ_4(sc, reg) & ~(x))
241
242 #define SIO_SET(x) \
243 CSR_WRITE_4(sc, WB_SIO, \
244 CSR_READ_4(sc, WB_SIO) | (x))
245
246 #define SIO_CLR(x) \
247 CSR_WRITE_4(sc, WB_SIO, \
248 CSR_READ_4(sc, WB_SIO) & ~(x))
249
250 /*
251 * Send a read command and address to the EEPROM, check for ACK.
252 */
253 static void
254 wb_eeprom_putbyte(sc, addr)
255 struct wb_softc *sc;
256 int addr;
257 {
258 register int d, i;
259
260 d = addr | WB_EECMD_READ;
261
262 /*
263 * Feed in each bit and stobe the clock.
264 */
265 for (i = 0x400; i; i >>= 1) {
266 if (d & i) {
267 SIO_SET(WB_SIO_EE_DATAIN);
268 } else {
269 SIO_CLR(WB_SIO_EE_DATAIN);
270 }
271 DELAY(100);
272 SIO_SET(WB_SIO_EE_CLK);
273 DELAY(150);
274 SIO_CLR(WB_SIO_EE_CLK);
275 DELAY(100);
276 }
277 }
278
279 /*
280 * Read a word of data stored in the EEPROM at address 'addr.'
281 */
282 static void
283 wb_eeprom_getword(sc, addr, dest)
284 struct wb_softc *sc;
285 int addr;
286 u_int16_t *dest;
287 {
288 register int i;
289 u_int16_t word = 0;
290
291 /* Enter EEPROM access mode. */
292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
293
294 /*
295 * Send address of word we want to read.
296 */
297 wb_eeprom_putbyte(sc, addr);
298
299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
300
301 /*
302 * Start reading bits from EEPROM.
303 */
304 for (i = 0x8000; i; i >>= 1) {
305 SIO_SET(WB_SIO_EE_CLK);
306 DELAY(100);
307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
308 word |= i;
309 SIO_CLR(WB_SIO_EE_CLK);
310 DELAY(100);
311 }
312
313 /* Turn off EEPROM access mode. */
314 CSR_WRITE_4(sc, WB_SIO, 0);
315
316 *dest = word;
317 }
318
319 /*
320 * Read a sequence of words from the EEPROM.
321 */
322 static void
323 wb_read_eeprom(sc, dest, off, cnt, swap)
324 struct wb_softc *sc;
325 caddr_t dest;
326 int off;
327 int cnt;
328 int swap;
329 {
330 int i;
331 u_int16_t word = 0, *ptr;
332
333 for (i = 0; i < cnt; i++) {
334 wb_eeprom_getword(sc, off + i, &word);
335 ptr = (u_int16_t *)(dest + (i * 2));
336 if (swap)
337 *ptr = ntohs(word);
338 else
339 *ptr = word;
340 }
341 }
342
343 /*
344 * Read the MII serial port for the MII bit-bang module.
345 */
346 static uint32_t
347 wb_mii_bitbang_read(device_t dev)
348 {
349 struct wb_softc *sc;
350 uint32_t val;
351
352 sc = device_get_softc(dev);
353
354 val = CSR_READ_4(sc, WB_SIO);
355 CSR_BARRIER(sc, WB_SIO, 4,
356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
357
358 return (val);
359 }
360
361 /*
362 * Write the MII serial port for the MII bit-bang module.
363 */
364 static void
365 wb_mii_bitbang_write(device_t dev, uint32_t val)
366 {
367 struct wb_softc *sc;
368
369 sc = device_get_softc(dev);
370
371 CSR_WRITE_4(sc, WB_SIO, val);
372 CSR_BARRIER(sc, WB_SIO, 4,
373 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
374 }
375
376 static int
377 wb_miibus_readreg(dev, phy, reg)
378 device_t dev;
379 int phy, reg;
380 {
381
382 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg));
383 }
384
385 static int
386 wb_miibus_writereg(dev, phy, reg, data)
387 device_t dev;
388 int phy, reg, data;
389 {
390
391 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data);
392
393 return(0);
394 }
395
396 static void
397 wb_miibus_statchg(dev)
398 device_t dev;
399 {
400 struct wb_softc *sc;
401 struct mii_data *mii;
402
403 sc = device_get_softc(dev);
404 mii = device_get_softc(sc->wb_miibus);
405 wb_setcfg(sc, mii->mii_media_active);
406 }
407
408 /*
409 * Program the 64-bit multicast hash filter.
410 */
411 static void
412 wb_setmulti(sc)
413 struct wb_softc *sc;
414 {
415 struct ifnet *ifp;
416 int h = 0;
417 u_int32_t hashes[2] = { 0, 0 };
418 struct ifmultiaddr *ifma;
419 u_int32_t rxfilt;
420 int mcnt = 0;
421
422 ifp = sc->wb_ifp;
423
424 rxfilt = CSR_READ_4(sc, WB_NETCFG);
425
426 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
427 rxfilt |= WB_NETCFG_RX_MULTI;
428 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
429 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
430 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
431 return;
432 }
433
434 /* first, zot all the existing hash bits */
435 CSR_WRITE_4(sc, WB_MAR0, 0);
436 CSR_WRITE_4(sc, WB_MAR1, 0);
437
438 /* now program new ones */
439 if_maddr_rlock(ifp);
440 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
441 if (ifma->ifma_addr->sa_family != AF_LINK)
442 continue;
443 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
444 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
445 if (h < 32)
446 hashes[0] |= (1 << h);
447 else
448 hashes[1] |= (1 << (h - 32));
449 mcnt++;
450 }
451 if_maddr_runlock(ifp);
452
453 if (mcnt)
454 rxfilt |= WB_NETCFG_RX_MULTI;
455 else
456 rxfilt &= ~WB_NETCFG_RX_MULTI;
457
458 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
459 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
460 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
461 }
462
463 /*
464 * The Winbond manual states that in order to fiddle with the
465 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
466 * first have to put the transmit and/or receive logic in the idle state.
467 */
468 static void
469 wb_setcfg(sc, media)
470 struct wb_softc *sc;
471 u_int32_t media;
472 {
473 int i, restart = 0;
474
475 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
476 restart = 1;
477 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
478
479 for (i = 0; i < WB_TIMEOUT; i++) {
480 DELAY(10);
481 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
482 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
483 break;
484 }
485
486 if (i == WB_TIMEOUT)
487 device_printf(sc->wb_dev,
488 "failed to force tx and rx to idle state\n");
489 }
490
491 if (IFM_SUBTYPE(media) == IFM_10_T)
492 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
493 else
494 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
495
496 if ((media & IFM_GMASK) == IFM_FDX)
497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
498 else
499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
500
501 if (restart)
502 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
503 }
504
505 static void
506 wb_reset(sc)
507 struct wb_softc *sc;
508 {
509 register int i;
510 struct mii_data *mii;
511 struct mii_softc *miisc;
512
513 CSR_WRITE_4(sc, WB_NETCFG, 0);
514 CSR_WRITE_4(sc, WB_BUSCTL, 0);
515 CSR_WRITE_4(sc, WB_TXADDR, 0);
516 CSR_WRITE_4(sc, WB_RXADDR, 0);
517
518 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
519 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
520
521 for (i = 0; i < WB_TIMEOUT; i++) {
522 DELAY(10);
523 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
524 break;
525 }
526 if (i == WB_TIMEOUT)
527 device_printf(sc->wb_dev, "reset never completed!\n");
528
529 /* Wait a little while for the chip to get its brains in order. */
530 DELAY(1000);
531
532 if (sc->wb_miibus == NULL)
533 return;
534
535 mii = device_get_softc(sc->wb_miibus);
536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
537 mii_phy_reset(miisc);
538 }
539
540 static void
541 wb_fixmedia(sc)
542 struct wb_softc *sc;
543 {
544 struct mii_data *mii = NULL;
545 struct ifnet *ifp;
546 u_int32_t media;
547
548 mii = device_get_softc(sc->wb_miibus);
549 ifp = sc->wb_ifp;
550
551 mii_pollstat(mii);
552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
553 media = mii->mii_media_active & ~IFM_10_T;
554 media |= IFM_100_TX;
555 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
556 media = mii->mii_media_active & ~IFM_100_TX;
557 media |= IFM_10_T;
558 } else
559 return;
560
561 ifmedia_set(&mii->mii_media, media);
562 }
563
564 /*
565 * Probe for a Winbond chip. Check the PCI vendor and device
566 * IDs against our list and return a device name if we find a match.
567 */
568 static int
569 wb_probe(dev)
570 device_t dev;
571 {
572 const struct wb_type *t;
573
574 t = wb_devs;
575
576 while(t->wb_name != NULL) {
577 if ((pci_get_vendor(dev) == t->wb_vid) &&
578 (pci_get_device(dev) == t->wb_did)) {
579 device_set_desc(dev, t->wb_name);
580 return (BUS_PROBE_DEFAULT);
581 }
582 t++;
583 }
584
585 return(ENXIO);
586 }
587
588 /*
589 * Attach the interface. Allocate softc structures, do ifmedia
590 * setup and ethernet/BPF attach.
591 */
592 static int
593 wb_attach(dev)
594 device_t dev;
595 {
596 u_char eaddr[ETHER_ADDR_LEN];
597 struct wb_softc *sc;
598 struct ifnet *ifp;
599 int error = 0, rid;
600
601 sc = device_get_softc(dev);
602 sc->wb_dev = dev;
603
604 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
605 MTX_DEF);
606 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
607
608 /*
609 * Map control/status registers.
610 */
611 pci_enable_busmaster(dev);
612
613 rid = WB_RID;
614 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
615
616 if (sc->wb_res == NULL) {
617 device_printf(dev, "couldn't map ports/memory\n");
618 error = ENXIO;
619 goto fail;
620 }
621
622 sc->wb_btag = rman_get_bustag(sc->wb_res);
623 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
624
625 /* Allocate interrupt */
626 rid = 0;
627 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
628 RF_SHAREABLE | RF_ACTIVE);
629
630 if (sc->wb_irq == NULL) {
631 device_printf(dev, "couldn't map interrupt\n");
632 error = ENXIO;
633 goto fail;
634 }
635
636 /* Save the cache line size. */
637 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
638
639 /* Reset the adapter. */
640 wb_reset(sc);
641
642 /*
643 * Get station address from the EEPROM.
644 */
645 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
646
647 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
648 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
649
650 if (sc->wb_ldata == NULL) {
651 device_printf(dev, "no memory for list buffers!\n");
652 error = ENXIO;
653 goto fail;
654 }
655
656 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
657
658 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
659 if (ifp == NULL) {
660 device_printf(dev, "can not if_alloc()\n");
661 error = ENOSPC;
662 goto fail;
663 }
664 ifp->if_softc = sc;
665 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
666 ifp->if_mtu = ETHERMTU;
667 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
668 ifp->if_ioctl = wb_ioctl;
669 ifp->if_start = wb_start;
670 ifp->if_init = wb_init;
671 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
672
673 /*
674 * Do MII setup.
675 */
676 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd,
677 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
678 if (error != 0) {
679 device_printf(dev, "attaching PHYs failed\n");
680 goto fail;
681 }
682
683 /*
684 * Call MI attach routine.
685 */
686 ether_ifattach(ifp, eaddr);
687
688 /* Hook interrupt last to avoid having to lock softc */
689 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
690 NULL, wb_intr, sc, &sc->wb_intrhand);
691
692 if (error) {
693 device_printf(dev, "couldn't set up irq\n");
694 ether_ifdetach(ifp);
695 goto fail;
696 }
697
698 fail:
699 if (error)
700 wb_detach(dev);
701
702 return(error);
703 }
704
705 /*
706 * Shutdown hardware and free up resources. This can be called any
707 * time after the mutex has been initialized. It is called in both
708 * the error case in attach and the normal detach case so it needs
709 * to be careful about only freeing resources that have actually been
710 * allocated.
711 */
712 static int
713 wb_detach(dev)
714 device_t dev;
715 {
716 struct wb_softc *sc;
717 struct ifnet *ifp;
718
719 sc = device_get_softc(dev);
720 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
721 ifp = sc->wb_ifp;
722
723 /*
724 * Delete any miibus and phy devices attached to this interface.
725 * This should only be done if attach succeeded.
726 */
727 if (device_is_attached(dev)) {
728 ether_ifdetach(ifp);
729 WB_LOCK(sc);
730 wb_stop(sc);
731 WB_UNLOCK(sc);
732 callout_drain(&sc->wb_stat_callout);
733 }
734 if (sc->wb_miibus)
735 device_delete_child(dev, sc->wb_miibus);
736 bus_generic_detach(dev);
737
738 if (sc->wb_intrhand)
739 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
740 if (sc->wb_irq)
741 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
742 if (sc->wb_res)
743 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
744
745 if (ifp)
746 if_free(ifp);
747
748 if (sc->wb_ldata) {
749 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
750 M_DEVBUF);
751 }
752
753 mtx_destroy(&sc->wb_mtx);
754
755 return(0);
756 }
757
758 /*
759 * Initialize the transmit descriptors.
760 */
761 static int
762 wb_list_tx_init(sc)
763 struct wb_softc *sc;
764 {
765 struct wb_chain_data *cd;
766 struct wb_list_data *ld;
767 int i;
768
769 cd = &sc->wb_cdata;
770 ld = sc->wb_ldata;
771
772 for (i = 0; i < WB_TX_LIST_CNT; i++) {
773 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
774 if (i == (WB_TX_LIST_CNT - 1)) {
775 cd->wb_tx_chain[i].wb_nextdesc =
776 &cd->wb_tx_chain[0];
777 } else {
778 cd->wb_tx_chain[i].wb_nextdesc =
779 &cd->wb_tx_chain[i + 1];
780 }
781 }
782
783 cd->wb_tx_free = &cd->wb_tx_chain[0];
784 cd->wb_tx_tail = cd->wb_tx_head = NULL;
785
786 return(0);
787 }
788
789
790 /*
791 * Initialize the RX descriptors and allocate mbufs for them. Note that
792 * we arrange the descriptors in a closed ring, so that the last descriptor
793 * points back to the first.
794 */
795 static int
796 wb_list_rx_init(sc)
797 struct wb_softc *sc;
798 {
799 struct wb_chain_data *cd;
800 struct wb_list_data *ld;
801 int i;
802
803 cd = &sc->wb_cdata;
804 ld = sc->wb_ldata;
805
806 for (i = 0; i < WB_RX_LIST_CNT; i++) {
807 cd->wb_rx_chain[i].wb_ptr =
808 (struct wb_desc *)&ld->wb_rx_list[i];
809 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
810 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
811 return(ENOBUFS);
812 if (i == (WB_RX_LIST_CNT - 1)) {
813 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
814 ld->wb_rx_list[i].wb_next =
815 vtophys(&ld->wb_rx_list[0]);
816 } else {
817 cd->wb_rx_chain[i].wb_nextdesc =
818 &cd->wb_rx_chain[i + 1];
819 ld->wb_rx_list[i].wb_next =
820 vtophys(&ld->wb_rx_list[i + 1]);
821 }
822 }
823
824 cd->wb_rx_head = &cd->wb_rx_chain[0];
825
826 return(0);
827 }
828
829 static void
830 wb_bfree(buf, args)
831 void *buf;
832 void *args;
833 {
834
835 }
836
837 /*
838 * Initialize an RX descriptor and attach an MBUF cluster.
839 */
840 static int
841 wb_newbuf(sc, c, m)
842 struct wb_softc *sc;
843 struct wb_chain_onefrag *c;
844 struct mbuf *m;
845 {
846 struct mbuf *m_new = NULL;
847
848 if (m == NULL) {
849 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
850 if (m_new == NULL)
851 return(ENOBUFS);
852 m_new->m_data = c->wb_buf;
853 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
854 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf,
855 NULL, 0, EXT_NET_DRV);
856 } else {
857 m_new = m;
858 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
859 m_new->m_data = m_new->m_ext.ext_buf;
860 }
861
862 m_adj(m_new, sizeof(u_int64_t));
863
864 c->wb_mbuf = m_new;
865 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
866 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
867 c->wb_ptr->wb_status = WB_RXSTAT;
868
869 return(0);
870 }
871
872 /*
873 * A frame has been uploaded: pass the resulting mbuf chain up to
874 * the higher level protocols.
875 */
876 static void
877 wb_rxeof(sc)
878 struct wb_softc *sc;
879 {
880 struct mbuf *m = NULL;
881 struct ifnet *ifp;
882 struct wb_chain_onefrag *cur_rx;
883 int total_len = 0;
884 u_int32_t rxstat;
885
886 WB_LOCK_ASSERT(sc);
887
888 ifp = sc->wb_ifp;
889
890 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
891 WB_RXSTAT_OWN)) {
892 struct mbuf *m0 = NULL;
893
894 cur_rx = sc->wb_cdata.wb_rx_head;
895 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
896
897 m = cur_rx->wb_mbuf;
898
899 if ((rxstat & WB_RXSTAT_MIIERR) ||
900 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
901 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
902 !(rxstat & WB_RXSTAT_LASTFRAG) ||
903 !(rxstat & WB_RXSTAT_RXCMP)) {
904 ifp->if_ierrors++;
905 wb_newbuf(sc, cur_rx, m);
906 device_printf(sc->wb_dev,
907 "receiver babbling: possible chip bug,"
908 " forcing reset\n");
909 wb_fixmedia(sc);
910 wb_reset(sc);
911 wb_init_locked(sc);
912 return;
913 }
914
915 if (rxstat & WB_RXSTAT_RXERR) {
916 ifp->if_ierrors++;
917 wb_newbuf(sc, cur_rx, m);
918 break;
919 }
920
921 /* No errors; receive the packet. */
922 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
923
924 /*
925 * XXX The Winbond chip includes the CRC with every
926 * received frame, and there's no way to turn this
927 * behavior off (at least, I can't find anything in
928 * the manual that explains how to do it) so we have
929 * to trim off the CRC manually.
930 */
931 total_len -= ETHER_CRC_LEN;
932
933 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
934 NULL);
935 wb_newbuf(sc, cur_rx, m);
936 if (m0 == NULL) {
937 ifp->if_ierrors++;
938 break;
939 }
940 m = m0;
941
942 ifp->if_ipackets++;
943 WB_UNLOCK(sc);
944 (*ifp->if_input)(ifp, m);
945 WB_LOCK(sc);
946 }
947 }
948
949 static void
950 wb_rxeoc(sc)
951 struct wb_softc *sc;
952 {
953 wb_rxeof(sc);
954
955 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
956 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
957 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
958 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
959 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
960 }
961
962 /*
963 * A frame was downloaded to the chip. It's safe for us to clean up
964 * the list buffers.
965 */
966 static void
967 wb_txeof(sc)
968 struct wb_softc *sc;
969 {
970 struct wb_chain *cur_tx;
971 struct ifnet *ifp;
972
973 ifp = sc->wb_ifp;
974
975 /* Clear the timeout timer. */
976 sc->wb_timer = 0;
977
978 if (sc->wb_cdata.wb_tx_head == NULL)
979 return;
980
981 /*
982 * Go through our tx list and free mbufs for those
983 * frames that have been transmitted.
984 */
985 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
986 u_int32_t txstat;
987
988 cur_tx = sc->wb_cdata.wb_tx_head;
989 txstat = WB_TXSTATUS(cur_tx);
990
991 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
992 break;
993
994 if (txstat & WB_TXSTAT_TXERR) {
995 ifp->if_oerrors++;
996 if (txstat & WB_TXSTAT_ABORT)
997 ifp->if_collisions++;
998 if (txstat & WB_TXSTAT_LATECOLL)
999 ifp->if_collisions++;
1000 }
1001
1002 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1003
1004 ifp->if_opackets++;
1005 m_freem(cur_tx->wb_mbuf);
1006 cur_tx->wb_mbuf = NULL;
1007
1008 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1009 sc->wb_cdata.wb_tx_head = NULL;
1010 sc->wb_cdata.wb_tx_tail = NULL;
1011 break;
1012 }
1013
1014 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1015 }
1016 }
1017
1018 /*
1019 * TX 'end of channel' interrupt handler.
1020 */
1021 static void
1022 wb_txeoc(sc)
1023 struct wb_softc *sc;
1024 {
1025 struct ifnet *ifp;
1026
1027 ifp = sc->wb_ifp;
1028
1029 sc->wb_timer = 0;
1030
1031 if (sc->wb_cdata.wb_tx_head == NULL) {
1032 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1033 sc->wb_cdata.wb_tx_tail = NULL;
1034 } else {
1035 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1036 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1037 sc->wb_timer = 5;
1038 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1039 }
1040 }
1041 }
1042
1043 static void
1044 wb_intr(arg)
1045 void *arg;
1046 {
1047 struct wb_softc *sc;
1048 struct ifnet *ifp;
1049 u_int32_t status;
1050
1051 sc = arg;
1052 WB_LOCK(sc);
1053 ifp = sc->wb_ifp;
1054
1055 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1056 WB_UNLOCK(sc);
1057 return;
1058 }
1059
1060 /* Disable interrupts. */
1061 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1062
1063 for (;;) {
1064
1065 status = CSR_READ_4(sc, WB_ISR);
1066 if (status)
1067 CSR_WRITE_4(sc, WB_ISR, status);
1068
1069 if ((status & WB_INTRS) == 0)
1070 break;
1071
1072 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1073 ifp->if_ierrors++;
1074 wb_reset(sc);
1075 if (status & WB_ISR_RX_ERR)
1076 wb_fixmedia(sc);
1077 wb_init_locked(sc);
1078 continue;
1079 }
1080
1081 if (status & WB_ISR_RX_OK)
1082 wb_rxeof(sc);
1083
1084 if (status & WB_ISR_RX_IDLE)
1085 wb_rxeoc(sc);
1086
1087 if (status & WB_ISR_TX_OK)
1088 wb_txeof(sc);
1089
1090 if (status & WB_ISR_TX_NOBUF)
1091 wb_txeoc(sc);
1092
1093 if (status & WB_ISR_TX_IDLE) {
1094 wb_txeof(sc);
1095 if (sc->wb_cdata.wb_tx_head != NULL) {
1096 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1097 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1098 }
1099 }
1100
1101 if (status & WB_ISR_TX_UNDERRUN) {
1102 ifp->if_oerrors++;
1103 wb_txeof(sc);
1104 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1105 /* Jack up TX threshold */
1106 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1107 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1108 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1109 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1110 }
1111
1112 if (status & WB_ISR_BUS_ERR) {
1113 wb_reset(sc);
1114 wb_init_locked(sc);
1115 }
1116
1117 }
1118
1119 /* Re-enable interrupts. */
1120 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1121
1122 if (ifp->if_snd.ifq_head != NULL) {
1123 wb_start_locked(ifp);
1124 }
1125
1126 WB_UNLOCK(sc);
1127 }
1128
1129 static void
1130 wb_tick(xsc)
1131 void *xsc;
1132 {
1133 struct wb_softc *sc;
1134 struct mii_data *mii;
1135
1136 sc = xsc;
1137 WB_LOCK_ASSERT(sc);
1138 mii = device_get_softc(sc->wb_miibus);
1139
1140 mii_tick(mii);
1141
1142 if (sc->wb_timer > 0 && --sc->wb_timer == 0)
1143 wb_watchdog(sc);
1144 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1145 }
1146
1147 /*
1148 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1149 * pointers to the fragment pointers.
1150 */
1151 static int
1152 wb_encap(sc, c, m_head)
1153 struct wb_softc *sc;
1154 struct wb_chain *c;
1155 struct mbuf *m_head;
1156 {
1157 int frag = 0;
1158 struct wb_desc *f = NULL;
1159 int total_len;
1160 struct mbuf *m;
1161
1162 /*
1163 * Start packing the mbufs in this chain into
1164 * the fragment pointers. Stop when we run out
1165 * of fragments or hit the end of the mbuf chain.
1166 */
1167 m = m_head;
1168 total_len = 0;
1169
1170 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1171 if (m->m_len != 0) {
1172 if (frag == WB_MAXFRAGS)
1173 break;
1174 total_len += m->m_len;
1175 f = &c->wb_ptr->wb_frag[frag];
1176 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1177 if (frag == 0) {
1178 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1179 f->wb_status = 0;
1180 } else
1181 f->wb_status = WB_TXSTAT_OWN;
1182 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1183 f->wb_data = vtophys(mtod(m, vm_offset_t));
1184 frag++;
1185 }
1186 }
1187
1188 /*
1189 * Handle special case: we used up all 16 fragments,
1190 * but we have more mbufs left in the chain. Copy the
1191 * data into an mbuf cluster. Note that we don't
1192 * bother clearing the values in the other fragment
1193 * pointers/counters; it wouldn't gain us anything,
1194 * and would waste cycles.
1195 */
1196 if (m != NULL) {
1197 struct mbuf *m_new = NULL;
1198
1199 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1200 if (m_new == NULL)
1201 return(1);
1202 if (m_head->m_pkthdr.len > MHLEN) {
1203 MCLGET(m_new, M_DONTWAIT);
1204 if (!(m_new->m_flags & M_EXT)) {
1205 m_freem(m_new);
1206 return(1);
1207 }
1208 }
1209 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1210 mtod(m_new, caddr_t));
1211 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1212 m_freem(m_head);
1213 m_head = m_new;
1214 f = &c->wb_ptr->wb_frag[0];
1215 f->wb_status = 0;
1216 f->wb_data = vtophys(mtod(m_new, caddr_t));
1217 f->wb_ctl = total_len = m_new->m_len;
1218 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1219 frag = 1;
1220 }
1221
1222 if (total_len < WB_MIN_FRAMELEN) {
1223 f = &c->wb_ptr->wb_frag[frag];
1224 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1225 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1226 f->wb_ctl |= WB_TXCTL_TLINK;
1227 f->wb_status = WB_TXSTAT_OWN;
1228 frag++;
1229 }
1230
1231 c->wb_mbuf = m_head;
1232 c->wb_lastdesc = frag - 1;
1233 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1234 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1235
1236 return(0);
1237 }
1238
1239 /*
1240 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1241 * to the mbuf data regions directly in the transmit lists. We also save a
1242 * copy of the pointers since the transmit list fragment pointers are
1243 * physical addresses.
1244 */
1245
1246 static void
1247 wb_start(ifp)
1248 struct ifnet *ifp;
1249 {
1250 struct wb_softc *sc;
1251
1252 sc = ifp->if_softc;
1253 WB_LOCK(sc);
1254 wb_start_locked(ifp);
1255 WB_UNLOCK(sc);
1256 }
1257
1258 static void
1259 wb_start_locked(ifp)
1260 struct ifnet *ifp;
1261 {
1262 struct wb_softc *sc;
1263 struct mbuf *m_head = NULL;
1264 struct wb_chain *cur_tx = NULL, *start_tx;
1265
1266 sc = ifp->if_softc;
1267 WB_LOCK_ASSERT(sc);
1268
1269 /*
1270 * Check for an available queue slot. If there are none,
1271 * punt.
1272 */
1273 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1274 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1275 return;
1276 }
1277
1278 start_tx = sc->wb_cdata.wb_tx_free;
1279
1280 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1281 IF_DEQUEUE(&ifp->if_snd, m_head);
1282 if (m_head == NULL)
1283 break;
1284
1285 /* Pick a descriptor off the free list. */
1286 cur_tx = sc->wb_cdata.wb_tx_free;
1287 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1288
1289 /* Pack the data into the descriptor. */
1290 wb_encap(sc, cur_tx, m_head);
1291
1292 if (cur_tx != start_tx)
1293 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1294
1295 /*
1296 * If there's a BPF listener, bounce a copy of this frame
1297 * to him.
1298 */
1299 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1300 }
1301
1302 /*
1303 * If there are no packets queued, bail.
1304 */
1305 if (cur_tx == NULL)
1306 return;
1307
1308 /*
1309 * Place the request for the upload interrupt
1310 * in the last descriptor in the chain. This way, if
1311 * we're chaining several packets at once, we'll only
1312 * get an interrupt once for the whole chain rather than
1313 * once for each packet.
1314 */
1315 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1316 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1317 sc->wb_cdata.wb_tx_tail = cur_tx;
1318
1319 if (sc->wb_cdata.wb_tx_head == NULL) {
1320 sc->wb_cdata.wb_tx_head = start_tx;
1321 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1322 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1323 } else {
1324 /*
1325 * We need to distinguish between the case where
1326 * the own bit is clear because the chip cleared it
1327 * and where the own bit is clear because we haven't
1328 * set it yet. The magic value WB_UNSET is just some
1329 * ramdomly chosen number which doesn't have the own
1330 * bit set. When we actually transmit the frame, the
1331 * status word will have _only_ the own bit set, so
1332 * the txeoc handler will be able to tell if it needs
1333 * to initiate another transmission to flush out pending
1334 * frames.
1335 */
1336 WB_TXOWN(start_tx) = WB_UNSENT;
1337 }
1338
1339 /*
1340 * Set a timeout in case the chip goes out to lunch.
1341 */
1342 sc->wb_timer = 5;
1343 }
1344
1345 static void
1346 wb_init(xsc)
1347 void *xsc;
1348 {
1349 struct wb_softc *sc = xsc;
1350
1351 WB_LOCK(sc);
1352 wb_init_locked(sc);
1353 WB_UNLOCK(sc);
1354 }
1355
1356 static void
1357 wb_init_locked(sc)
1358 struct wb_softc *sc;
1359 {
1360 struct ifnet *ifp = sc->wb_ifp;
1361 int i;
1362 struct mii_data *mii;
1363
1364 WB_LOCK_ASSERT(sc);
1365 mii = device_get_softc(sc->wb_miibus);
1366
1367 /*
1368 * Cancel pending I/O and free all RX/TX buffers.
1369 */
1370 wb_stop(sc);
1371 wb_reset(sc);
1372
1373 sc->wb_txthresh = WB_TXTHRESH_INIT;
1374
1375 /*
1376 * Set cache alignment and burst length.
1377 */
1378 #ifdef foo
1379 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1380 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1381 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1382 #endif
1383
1384 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1385 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1386 switch(sc->wb_cachesize) {
1387 case 32:
1388 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1389 break;
1390 case 16:
1391 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1392 break;
1393 case 8:
1394 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1395 break;
1396 case 0:
1397 default:
1398 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1399 break;
1400 }
1401
1402 /* This doesn't tend to work too well at 100Mbps. */
1403 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1404
1405 /* Init our MAC address */
1406 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1407 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
1408 }
1409
1410 /* Init circular RX list. */
1411 if (wb_list_rx_init(sc) == ENOBUFS) {
1412 device_printf(sc->wb_dev,
1413 "initialization failed: no memory for rx buffers\n");
1414 wb_stop(sc);
1415 return;
1416 }
1417
1418 /* Init TX descriptors. */
1419 wb_list_tx_init(sc);
1420
1421 /* If we want promiscuous mode, set the allframes bit. */
1422 if (ifp->if_flags & IFF_PROMISC) {
1423 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1424 } else {
1425 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1426 }
1427
1428 /*
1429 * Set capture broadcast bit to capture broadcast frames.
1430 */
1431 if (ifp->if_flags & IFF_BROADCAST) {
1432 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1433 } else {
1434 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1435 }
1436
1437 /*
1438 * Program the multicast filter, if necessary.
1439 */
1440 wb_setmulti(sc);
1441
1442 /*
1443 * Load the address of the RX list.
1444 */
1445 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1446 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1447
1448 /*
1449 * Enable interrupts.
1450 */
1451 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1452 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1453
1454 /* Enable receiver and transmitter. */
1455 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1456 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1457
1458 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1459 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1460 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1461
1462 mii_mediachg(mii);
1463
1464 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1465 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1466
1467 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1468 }
1469
1470 /*
1471 * Set media options.
1472 */
1473 static int
1474 wb_ifmedia_upd(ifp)
1475 struct ifnet *ifp;
1476 {
1477 struct wb_softc *sc;
1478
1479 sc = ifp->if_softc;
1480
1481 WB_LOCK(sc);
1482 if (ifp->if_flags & IFF_UP)
1483 wb_init_locked(sc);
1484 WB_UNLOCK(sc);
1485
1486 return(0);
1487 }
1488
1489 /*
1490 * Report current media status.
1491 */
1492 static void
1493 wb_ifmedia_sts(ifp, ifmr)
1494 struct ifnet *ifp;
1495 struct ifmediareq *ifmr;
1496 {
1497 struct wb_softc *sc;
1498 struct mii_data *mii;
1499
1500 sc = ifp->if_softc;
1501
1502 WB_LOCK(sc);
1503 mii = device_get_softc(sc->wb_miibus);
1504
1505 mii_pollstat(mii);
1506 ifmr->ifm_active = mii->mii_media_active;
1507 ifmr->ifm_status = mii->mii_media_status;
1508 WB_UNLOCK(sc);
1509 }
1510
1511 static int
1512 wb_ioctl(ifp, command, data)
1513 struct ifnet *ifp;
1514 u_long command;
1515 caddr_t data;
1516 {
1517 struct wb_softc *sc = ifp->if_softc;
1518 struct mii_data *mii;
1519 struct ifreq *ifr = (struct ifreq *) data;
1520 int error = 0;
1521
1522 switch(command) {
1523 case SIOCSIFFLAGS:
1524 WB_LOCK(sc);
1525 if (ifp->if_flags & IFF_UP) {
1526 wb_init_locked(sc);
1527 } else {
1528 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1529 wb_stop(sc);
1530 }
1531 WB_UNLOCK(sc);
1532 error = 0;
1533 break;
1534 case SIOCADDMULTI:
1535 case SIOCDELMULTI:
1536 WB_LOCK(sc);
1537 wb_setmulti(sc);
1538 WB_UNLOCK(sc);
1539 error = 0;
1540 break;
1541 case SIOCGIFMEDIA:
1542 case SIOCSIFMEDIA:
1543 mii = device_get_softc(sc->wb_miibus);
1544 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1545 break;
1546 default:
1547 error = ether_ioctl(ifp, command, data);
1548 break;
1549 }
1550
1551 return(error);
1552 }
1553
1554 static void
1555 wb_watchdog(sc)
1556 struct wb_softc *sc;
1557 {
1558 struct ifnet *ifp;
1559
1560 WB_LOCK_ASSERT(sc);
1561 ifp = sc->wb_ifp;
1562 ifp->if_oerrors++;
1563 if_printf(ifp, "watchdog timeout\n");
1564 #ifdef foo
1565 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1566 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1567 #endif
1568 wb_stop(sc);
1569 wb_reset(sc);
1570 wb_init_locked(sc);
1571
1572 if (ifp->if_snd.ifq_head != NULL)
1573 wb_start_locked(ifp);
1574 }
1575
1576 /*
1577 * Stop the adapter and free any mbufs allocated to the
1578 * RX and TX lists.
1579 */
1580 static void
1581 wb_stop(sc)
1582 struct wb_softc *sc;
1583 {
1584 register int i;
1585 struct ifnet *ifp;
1586
1587 WB_LOCK_ASSERT(sc);
1588 ifp = sc->wb_ifp;
1589 sc->wb_timer = 0;
1590
1591 callout_stop(&sc->wb_stat_callout);
1592
1593 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1594 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1595 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1596 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1597
1598 /*
1599 * Free data in the RX lists.
1600 */
1601 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1602 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1603 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1604 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1605 }
1606 }
1607 bzero((char *)&sc->wb_ldata->wb_rx_list,
1608 sizeof(sc->wb_ldata->wb_rx_list));
1609
1610 /*
1611 * Free the TX list buffers.
1612 */
1613 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1614 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1615 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1616 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1617 }
1618 }
1619
1620 bzero((char *)&sc->wb_ldata->wb_tx_list,
1621 sizeof(sc->wb_ldata->wb_tx_list));
1622
1623 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1624 }
1625
1626 /*
1627 * Stop all chip I/O so that the kernel's probe routines don't
1628 * get confused by errant DMAs when rebooting.
1629 */
1630 static int
1631 wb_shutdown(dev)
1632 device_t dev;
1633 {
1634 struct wb_softc *sc;
1635
1636 sc = device_get_softc(dev);
1637
1638 WB_LOCK(sc);
1639 wb_stop(sc);
1640 WB_UNLOCK(sc);
1641
1642 return (0);
1643 }
Cache object: 08bf85e12722a68c002a797e6cb1ab50
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