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FreeBSD/Linux Kernel Cross Reference
sys/dev/wpi/if_wpireg.h
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1 /* $FreeBSD: releng/9.0/sys/dev/wpi/if_wpireg.h 190458 2009-03-27 03:17:25Z jmallett $ */ 2 3 /*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define WPI_TX_RING_COUNT 256 21 #define WPI_CMD_RING_COUNT 256 22 #define WPI_RX_RING_COUNT 64 23 24 /* 25 * Rings must be aligned on a 16K boundary. 26 */ 27 #define WPI_RING_DMA_ALIGN 0x4000 28 29 /* maximum scatter/gather */ 30 #define WPI_MAX_SCATTER 4 31 32 /* maximum Rx buffer size */ 33 #define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 34 35 /* 36 * Control and status registers. 37 */ 38 #define WPI_HWCONFIG 0x000 39 #define WPI_INTR 0x008 40 #define WPI_MASK 0x00c 41 #define WPI_INTR_STATUS 0x010 42 #define WPI_GPIO_STATUS 0x018 43 #define WPI_RESET 0x020 44 #define WPI_GPIO_CTL 0x024 45 #define WPI_EEPROM_CTL 0x02c 46 #define WPI_EEPROM_STATUS 0x030 47 #define WPI_UCODE_SET 0x058 48 #define WPI_UCODE_CLR 0x05c 49 #define WPI_TEMPERATURE 0x060 50 #define WPI_CHICKEN 0x100 51 #define WPI_PLL_CTL 0x20c 52 #define WPI_WRITE_MEM_ADDR 0x444 53 #define WPI_READ_MEM_ADDR 0x448 54 #define WPI_WRITE_MEM_DATA 0x44c 55 #define WPI_READ_MEM_DATA 0x450 56 #define WPI_TX_WIDX 0x460 57 #define WPI_TX_CTL(qid) (0x940 + (qid) * 8) 58 #define WPI_TX_BASE(qid) (0x944 + (qid) * 8) 59 #define WPI_TX_DESC(qid) (0x980 + (qid) * 80) 60 #define WPI_RX_CONFIG 0xc00 61 #define WPI_RX_BASE 0xc04 62 #define WPI_RX_WIDX 0xc20 63 #define WPI_RX_RIDX_PTR 0xc24 64 #define WPI_RX_CTL 0xcc0 65 #define WPI_RX_STATUS 0xcc4 66 #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) 67 #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) 68 #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) 69 #define WPI_TX_BASE_PTR 0xe80 70 #define WPI_MSG_CONFIG 0xe88 71 #define WPI_TX_STATUS 0xe90 72 73 74 /* 75 * NIC internal memory offsets. 76 */ 77 #define WPI_MEM_MODE 0x2e00 78 #define WPI_MEM_RA 0x2e04 79 #define WPI_MEM_TXCFG 0x2e10 80 #define WPI_MEM_MAGIC4 0x2e14 81 #define WPI_MEM_MAGIC5 0x2e20 82 #define WPI_MEM_BYPASS1 0x2e2c 83 #define WPI_MEM_BYPASS2 0x2e30 84 #define WPI_MEM_CLOCK1 0x3004 85 #define WPI_MEM_CLOCK2 0x3008 86 #define WPI_MEM_POWER 0x300c 87 #define WPI_MEM_PCIDEV 0x3010 88 #define WPI_MEM_HW_RADIO_OFF 0x3014 89 #define WPI_MEM_UCODE_CTL 0x3400 90 #define WPI_MEM_UCODE_SRC 0x3404 91 #define WPI_MEM_UCODE_DST 0x3408 92 #define WPI_MEM_UCODE_SIZE 0x340c 93 #define WPI_MEM_UCODE_BASE 0x3800 94 95 #define WPI_MEM_TEXT_BASE 0x3490 96 #define WPI_MEM_TEXT_SIZE 0x3494 97 #define WPI_MEM_DATA_BASE 0x3498 98 #define WPI_MEM_DATA_SIZE 0x349c 99 100 101 /* possible flags for register WPI_HWCONFIG */ 102 #define WPI_HW_ALM_MB (1 << 8) 103 #define WPI_HW_ALM_MM (1 << 9) 104 #define WPI_HW_SKU_MRC (1 << 10) 105 #define WPI_HW_REV_D (1 << 11) 106 #define WPI_HW_TYPE_B (1 << 12) 107 108 /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */ 109 #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) 110 111 /* possible values for WPI_MEM_UCODE_DST */ 112 #define WPI_FW_TEXT 0x00000000 113 114 /* possible flags for WPI_GPIO_STATUS */ 115 #define WPI_POWERED (1 << 9) 116 117 /* possible flags for register WPI_RESET */ 118 #define WPI_NEVO_RESET (1 << 0) 119 #define WPI_SW_RESET (1 << 7) 120 #define WPI_MASTER_DISABLED (1 << 8) 121 #define WPI_STOP_MASTER (1 << 9) 122 123 /* possible flags for register WPI_GPIO_CTL */ 124 #define WPI_GPIO_CLOCK (1 << 0) 125 #define WPI_GPIO_INIT (1 << 2) 126 #define WPI_GPIO_MAC (1 << 3) 127 #define WPI_GPIO_SLEEP (1 << 4) 128 #define WPI_GPIO_PWR_STATUS 0x07000000 129 #define WPI_GPIO_PWR_SLEEP (4 << 24) 130 131 /* possible flags for register WPI_CHICKEN */ 132 #define WPI_CHICKEN_RXNOLOS (1 << 23) 133 134 /* possible flags for register WPI_PLL_CTL */ 135 #define WPI_PLL_INIT (1 << 24) 136 137 /* possible flags for register WPI_UCODE_CLR */ 138 #define WPI_RADIO_OFF (1 << 1) 139 #define WPI_DISABLE_CMD (1 << 2) 140 141 /* possible flags for WPI_RX_STATUS */ 142 #define WPI_RX_IDLE (1 << 24) 143 144 /* possible flags for register WPI_UC_CTL */ 145 #define WPI_UC_ENABLE (1 << 30) 146 #define WPI_UC_RUN (1 << 31) 147 148 /* possible flags for register WPI_INTR_CSR */ 149 #define WPI_ALIVE_INTR (1 << 0) 150 #define WPI_WAKEUP_INTR (1 << 1) 151 #define WPI_SW_ERROR (1 << 25) 152 #define WPI_TX_INTR (1 << 27) 153 #define WPI_HW_ERROR (1 << 29) 154 #define WPI_RX_INTR (1 << 31) 155 156 #define WPI_INTR_MASK \ 157 (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ 158 WPI_ALIVE_INTR | WPI_WAKEUP_INTR) 159 160 /* possible flags for register WPI_TX_STATUS */ 161 #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) 162 163 /* possible flags for register WPI_EEPROM_CTL */ 164 #define WPI_EEPROM_READY (1 << 0) 165 166 /* possible flags for register WPI_EEPROM_STATUS */ 167 #define WPI_EEPROM_VERSION 0x00000007 168 #define WPI_EEPROM_LOCKED 0x00000180 169 170 171 struct wpi_shared { 172 uint32_t txbase[8]; 173 uint32_t next; 174 uint32_t reserved[2]; 175 } __packed; 176 177 #define WPI_MAX_SEG_LEN 65520 178 struct wpi_tx_desc { 179 uint32_t flags; 180 #define WPI_PAD32(x) (roundup2(x, 4) - (x)) 181 182 struct { 183 uint32_t addr; 184 uint32_t len; 185 } __attribute__((__packed__)) segs[WPI_MAX_SCATTER]; 186 uint8_t reserved[28]; 187 } __packed; 188 189 struct wpi_tx_stat { 190 uint8_t nrts; 191 uint8_t ntries; 192 uint8_t nkill; 193 uint8_t rate; 194 uint32_t duration; 195 uint32_t status; 196 } __packed; 197 198 struct wpi_rx_desc { 199 uint32_t len; 200 uint8_t type; 201 #define WPI_UC_READY 1 202 #define WPI_RX_DONE 27 203 #define WPI_TX_DONE 28 204 #define WPI_START_SCAN 130 205 #define WPI_SCAN_RESULTS 131 206 #define WPI_STOP_SCAN 132 207 #define WPI_STATE_CHANGED 161 208 #define WPI_MISSED_BEACON 162 209 210 uint8_t flags; 211 uint8_t idx; 212 uint8_t qid; 213 } __packed; 214 215 struct wpi_rx_stat { 216 uint8_t len; 217 #define WPI_STAT_MAXLEN 20 218 219 uint8_t id; 220 uint8_t rssi; /* received signal strength */ 221 #define WPI_RSSI_OFFSET 95 222 223 uint8_t agc; /* access gain control */ 224 uint16_t signal; 225 uint16_t noise; 226 } __packed; 227 228 struct wpi_rx_head { 229 uint16_t chan; 230 uint16_t flags; 231 uint8_t reserved; 232 uint8_t rate; 233 uint16_t len; 234 } __packed; 235 236 struct wpi_rx_tail { 237 uint32_t flags; 238 #define WPI_RX_NO_CRC_ERR (1 << 0) 239 #define WPI_RX_NO_OVFL_ERR (1 << 1) 240 /* shortcut for the above */ 241 #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 242 uint64_t tstamp; 243 uint32_t tbeacon; 244 } __packed; 245 246 struct wpi_tx_cmd { 247 uint8_t code; 248 #define WPI_CMD_CONFIGURE 16 249 #define WPI_CMD_ASSOCIATE 17 250 #define WPI_CMD_SET_WME 19 251 #define WPI_CMD_TSF 20 252 #define WPI_CMD_ADD_NODE 24 253 #define WPI_CMD_TX_DATA 28 254 #define WPI_CMD_MRR_SETUP 71 255 #define WPI_CMD_SET_LED 72 256 #define WPI_CMD_SET_POWER_MODE 119 257 #define WPI_CMD_SCAN 128 258 #define WPI_CMD_SET_BEACON 145 259 #define WPI_CMD_TXPOWER 151 260 #define WPI_CMD_BLUETOOTH 155 261 262 uint8_t flags; 263 uint8_t idx; 264 uint8_t qid; 265 uint8_t data[360]; 266 } __packed; 267 268 /* structure for WPI_CMD_CONFIGURE */ 269 struct wpi_config { 270 uint8_t myaddr[IEEE80211_ADDR_LEN]; 271 uint16_t reserved1; 272 uint8_t bssid[IEEE80211_ADDR_LEN]; 273 uint16_t reserved2; 274 uint8_t wlap_bssid_addr[6]; 275 uint16_t reserved3; 276 uint8_t mode; 277 #define WPI_MODE_HOSTAP 1 278 #define WPI_MODE_STA 3 279 #define WPI_MODE_IBSS 4 280 #define WPI_MODE_MONITOR 6 281 282 uint8_t air_propogation; 283 uint16_t reserved4; 284 uint8_t ofdm_mask; 285 uint8_t cck_mask; 286 uint16_t associd; 287 uint32_t flags; 288 #define WPI_CONFIG_24GHZ (1 << 0) 289 #define WPI_CONFIG_CCK (1 << 1) 290 #define WPI_CONFIG_AUTO (1 << 2) 291 #define WPI_CONFIG_SHSLOT (1 << 4) 292 #define WPI_CONFIG_SHPREAMBLE (1 << 5) 293 #define WPI_CONFIG_NODIVERSITY (1 << 7) 294 #define WPI_CONFIG_ANTENNA_A (1 << 8) 295 #define WPI_CONFIG_ANTENNA_B (1 << 9) 296 #define WPI_CONFIG_TSF (1 << 15) 297 298 uint32_t filter; 299 #define WPI_FILTER_PROMISC (1 << 0) 300 #define WPI_FILTER_CTL (1 << 1) 301 #define WPI_FILTER_MULTICAST (1 << 2) 302 #define WPI_FILTER_NODECRYPT (1 << 3) 303 #define WPI_FILTER_BSS (1 << 5) 304 #define WPI_FILTER_BEACON (1 << 6) 305 306 uint8_t chan; 307 uint16_t reserved6; 308 } __packed; 309 310 /* structure for command WPI_CMD_ASSOCIATE */ 311 struct wpi_assoc { 312 uint32_t flags; 313 uint32_t filter; 314 uint8_t ofdm_mask; 315 uint8_t cck_mask; 316 uint16_t reserved; 317 } __packed; 318 319 /* structure for command WPI_CMD_SET_WME */ 320 struct wpi_wme_setup { 321 uint32_t flags; 322 struct { 323 uint16_t cwmin; 324 uint16_t cwmax; 325 uint8_t aifsn; 326 uint8_t reserved; 327 uint16_t txop; 328 } __packed ac[WME_NUM_AC]; 329 } __packed; 330 331 /* structure for command WPI_CMD_TSF */ 332 struct wpi_cmd_tsf { 333 uint64_t tstamp; 334 uint16_t bintval; 335 uint16_t atim; 336 uint32_t binitval; 337 uint16_t lintval; 338 uint16_t reserved; 339 } __packed; 340 341 /* structure for WPI_CMD_ADD_NODE */ 342 struct wpi_node_info { 343 uint8_t control; 344 #define WPI_NODE_UPDATE (1 << 0) 345 346 uint8_t reserved1[3]; 347 uint8_t bssid[IEEE80211_ADDR_LEN]; 348 uint16_t reserved2; 349 uint8_t id; 350 #define WPI_ID_BSS 0 351 #define WPI_ID_BROADCAST 24 352 353 uint8_t flags; 354 uint16_t reserved3; 355 uint16_t key_flags; 356 uint8_t tkip; 357 uint8_t reserved4; 358 uint16_t ttak[5]; 359 uint16_t reserved5; 360 uint8_t key[IEEE80211_KEYBUF_SIZE]; 361 uint32_t action; 362 #define WPI_ACTION_SET_RATE 4 363 uint32_t mask; 364 uint16_t tid; 365 uint8_t rate; 366 uint8_t antenna; 367 #define WPI_ANTENNA_A (1<<6) 368 #define WPI_ANTENNA_B (1<<7) 369 #define WPI_ANTENNA_BOTH (WPI_ANTENNA_A|WPI_ANTENNA_B) 370 uint8_t add_imm; 371 uint8_t del_imm; 372 uint16_t add_imm_start; 373 } __packed; 374 375 /* structure for command WPI_CMD_TX_DATA */ 376 struct wpi_cmd_data { 377 uint16_t len; 378 uint16_t lnext; 379 uint32_t flags; 380 #define WPI_TX_NEED_RTS (1 << 1) 381 #define WPI_TX_NEED_CTS (1 << 2) 382 #define WPI_TX_NEED_ACK (1 << 3) 383 #define WPI_TX_FULL_TXOP (1 << 7) 384 #define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 385 #define WPI_TX_AUTO_SEQ (1 << 13) 386 #define WPI_TX_INSERT_TSTAMP (1 << 16) 387 388 uint8_t rate; 389 uint8_t id; 390 uint8_t tid; 391 uint8_t security; 392 uint8_t key[IEEE80211_KEYBUF_SIZE]; 393 uint8_t tkip[IEEE80211_WEP_MICLEN]; 394 uint32_t fnext; 395 uint32_t lifetime; 396 #define WPI_LIFETIME_INFINITE 0xffffffff 397 uint8_t ofdm_mask; 398 uint8_t cck_mask; 399 uint8_t rts_ntries; 400 uint8_t data_ntries; 401 uint16_t timeout; 402 uint16_t txop; 403 struct ieee80211_frame wh; 404 } __packed; 405 406 /* structure for command WPI_CMD_SET_BEACON */ 407 struct wpi_cmd_beacon { 408 uint16_t len; 409 uint16_t reserved1; 410 uint32_t flags; /* same as wpi_cmd_data */ 411 uint8_t rate; 412 uint8_t id; 413 uint8_t reserved2[30]; 414 uint32_t lifetime; 415 uint8_t ofdm_mask; 416 uint8_t cck_mask; 417 uint16_t reserved3[3]; 418 uint16_t tim; 419 uint8_t timsz; 420 uint8_t reserved4; 421 struct ieee80211_frame wh; 422 } __packed; 423 424 /* structure for notification WPI_MISSED_BEACON */ 425 struct wpi_missed_beacon { 426 uint32_t consecutive; 427 uint32_t total; 428 uint32_t expected; 429 uint32_t received; 430 } __packed; 431 432 433 /* structure for WPI_CMD_MRR_SETUP */ 434 struct wpi_mrr_setup { 435 uint8_t which; 436 #define WPI_MRR_CTL 0 437 #define WPI_MRR_DATA 1 438 439 uint8_t reserved[3]; 440 441 struct { 442 uint8_t signal; 443 uint8_t flags; 444 uint8_t ntries; 445 uint8_t next; 446 #define WPI_OFDM6 0 447 #define WPI_OFDM54 7 448 #define WPI_CCK1 8 449 #define WPI_CCK2 9 450 #define WPI_CCK11 11 451 452 } __attribute__((__packed__)) rates[WPI_CCK11 + 1]; 453 } __packed; 454 455 /* structure for WPI_CMD_SET_LED */ 456 struct wpi_cmd_led { 457 uint32_t unit; /* multiplier (in usecs) */ 458 uint8_t which; 459 #define WPI_LED_ACTIVITY 1 460 #define WPI_LED_LINK 2 461 462 uint8_t off; 463 uint8_t on; 464 uint8_t reserved; 465 } __packed; 466 467 /* structure for WPI_CMD_SET_POWER_MODE */ 468 struct wpi_power { 469 uint32_t flags; 470 #define WPI_POWER_CAM 0 /* constantly awake mode */ 471 uint32_t rx_timeout; 472 uint32_t tx_timeout; 473 uint32_t sleep[5]; 474 } __packed; 475 476 /* structure for command WPI_CMD_SCAN */ 477 struct wpi_scan_hdr { 478 uint16_t len; 479 uint8_t reserved1; 480 uint8_t nchan; 481 uint16_t quiet; 482 uint16_t threshold; 483 uint16_t promotion; 484 uint16_t reserved2; 485 uint32_t maxtimeout; 486 uint32_t suspend; 487 uint32_t flags; 488 uint32_t filter; 489 490 struct { 491 uint16_t len; 492 uint16_t lnext; 493 uint32_t flags; 494 uint8_t rate; 495 uint8_t id; 496 uint8_t tid; 497 uint8_t security; 498 uint8_t key[IEEE80211_KEYBUF_SIZE]; 499 uint8_t tkip[IEEE80211_WEP_MICLEN]; 500 uint32_t fnext; 501 uint32_t lifetime; 502 uint8_t ofdm_mask; 503 uint8_t cck_mask; 504 uint8_t rts_ntries; 505 uint8_t data_ntries; 506 uint16_t timeout; 507 uint16_t txop; 508 } tx __attribute__((__packed__)); 509 510 #define WPI_SCAN_MAX_ESSIDS 4 511 struct { 512 uint8_t id; 513 uint8_t esslen; 514 uint8_t essid[32]; 515 }scan_essids[WPI_SCAN_MAX_ESSIDS]; 516 /* followed by probe request body */ 517 /* followed by nchan x wpi_scan_chan */ 518 } __packed; 519 520 struct wpi_scan_chan { 521 uint8_t flags; 522 uint8_t chan; 523 #define WPI_CHAN_ACTIVE (1 << 0) 524 #define WPI_CHAN_DIRECT (1 << 1) 525 uint8_t gain_radio; 526 uint8_t gain_dsp; 527 uint16_t active; /* msecs */ 528 uint16_t passive; /* msecs */ 529 } __packed; 530 531 /* structure for WPI_CMD_BLUETOOTH */ 532 struct wpi_bluetooth { 533 uint8_t flags; 534 uint8_t lead; 535 uint8_t kill; 536 uint8_t reserved; 537 uint32_t ack; 538 uint32_t cts; 539 } __packed; 540 541 /* structure for command WPI_CMD_TXPOWER */ 542 struct wpi_cmd_txpower { 543 544 uint8_t band; 545 #define WPI_RATE_5GHZ 0 546 #define WPI_RATE_2GHZ 1 547 uint8_t reserved; 548 uint16_t channel; 549 550 #define WPI_RATE_MAPPING_COUNT 12 551 struct { 552 uint8_t rate; 553 uint8_t gain_radio; 554 uint8_t gain_dsp; 555 uint8_t reserved; 556 } __packed rates [WPI_RATE_MAPPING_COUNT]; 557 558 } __packed; 559 560 561 562 #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024 ) 563 #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024 ) 564 #define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024 ) 565 #define WPI_FW_INIT_DATA_MAXSZ (32 * 1024 ) 566 #define WPI_FW_BOOT_TEXT_MAXSZ 1024 567 568 #define WPI_FW_UPDATED (1 << 31 ) 569 570 /* firmware image header */ 571 struct wpi_firmware_hdr { 572 573 #define WPI_FW_MINVERSION 2144 574 575 uint32_t version; 576 uint32_t rtextsz; 577 uint32_t rdatasz; 578 uint32_t itextsz; 579 uint32_t idatasz; 580 uint32_t btextsz; 581 } __packed; 582 583 /* structure for WPI_UC_READY notification */ 584 struct wpi_ucode_info { 585 uint32_t version; 586 uint8_t revision[8]; 587 uint8_t type; 588 uint8_t subtype; 589 uint16_t reserved; 590 uint32_t logptr; 591 uint32_t errorptr; 592 uint32_t timestamp; 593 uint32_t valid; 594 } __packed; 595 596 /* structure for WPI_START_SCAN notification */ 597 struct wpi_start_scan { 598 uint64_t tstamp; 599 uint32_t tbeacon; 600 uint8_t chan; 601 uint8_t band; 602 uint16_t reserved; 603 uint32_t status; 604 } __packed; 605 606 /* structure for WPI_STOP_SCAN notification */ 607 struct wpi_stop_scan { 608 uint8_t nchan; 609 uint8_t status; 610 uint8_t reserved; 611 uint8_t chan; 612 uint64_t tsf; 613 } __packed; 614 615 #define WPI_EEPROM_MAC 0x015 616 #define WPI_EEPROM_REVISION 0x035 617 #define WPI_EEPROM_CAPABILITIES 0x045 618 #define WPI_EEPROM_TYPE 0x04a 619 #define WPI_EEPROM_DOMAIN 0x060 620 #define WPI_EEPROM_BAND1 0x063 621 #define WPI_EEPROM_BAND2 0x072 622 #define WPI_EEPROM_BAND3 0x080 623 #define WPI_EEPROM_BAND4 0x08d 624 #define WPI_EEPROM_BAND5 0x099 625 #define WPI_EEPROM_POWER_GRP 0x100 626 627 struct wpi_eeprom_chan { 628 uint8_t flags; 629 #define WPI_EEPROM_CHAN_VALID (1<<0) 630 #define WPI_EEPROM_CHAN_IBSS (1<<1) 631 #define WPI_EEPROM_CHAN_ACTIVE (1<<3) 632 #define WPI_EEPROM_CHAN_RADAR (1<<4) 633 634 int8_t maxpwr; 635 } __packed; 636 637 struct wpi_eeprom_sample { 638 uint8_t index; 639 int8_t power; 640 uint16_t volt; 641 }; 642 643 #define WPI_POWER_GROUPS_COUNT 5 644 645 struct wpi_eeprom_group { 646 struct wpi_eeprom_sample samples[5]; 647 int32_t coef[5]; 648 int32_t corr[5]; 649 int8_t maxpwr; 650 uint8_t chan; 651 int16_t temp; 652 } __packed; 653 654 #define WPI_CHAN_BANDS_COUNT 5 655 #define WPI_MAX_CHAN_PER_BAND 14 656 657 static const struct wpi_chan_band { 658 uint32_t addr; /* offset in EEPROM */ 659 uint8_t nchan; 660 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 661 } wpi_bands[5] = { 662 { WPI_EEPROM_BAND1, 14, 663 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }}, 664 { WPI_EEPROM_BAND2, 13, 665 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 }}, 666 { WPI_EEPROM_BAND3, 12, 667 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 }}, 668 { WPI_EEPROM_BAND4, 11, 669 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 }}, 670 { WPI_EEPROM_BAND5, 6, 671 { 145, 149, 153, 157, 161, 165 }} 672 }; 673 674 #define WPI_MAX_PWR_INDEX 77 675 676 /* 677 * RF Tx gain values from highest to lowest power (values obtained from 678 * the reference driver.) 679 */ 680 static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 681 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 682 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 683 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 684 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 685 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 686 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 687 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 688 0x03 689 }; 690 691 static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 692 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 693 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 694 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 695 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 696 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 697 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 698 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 699 0x03 700 }; 701 702 /* 703 * DSP pre-DAC gain values from highest to lowest power (values obtained 704 * from the reference driver.) 705 */ 706 static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 707 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 708 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 709 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 710 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 711 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 712 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 713 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 714 0x5f 715 }; 716 717 static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 718 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 719 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 720 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 721 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 722 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 723 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 724 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 725 0x78 726 }; 727 728 729 #define WPI_READ(sc, reg) \ 730 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 731 732 #define WPI_WRITE(sc, reg, val) \ 733 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 734 735 #define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 736 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 737 (datap), (count))
Cache object: 5f4775e5ecee7a2de31cf76d1f51ebec
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