FreeBSD/Linux Kernel Cross Reference
sys/dev/xl/if_xl.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/9.0/sys/dev/xl/if_xl.c 227277 2011-11-06 21:09:10Z marius $");
35
36 /*
37 * 3Com 3c90x Etherlink XL PCI NIC driver
38 *
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
41 * the following:
42 *
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
72 *
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
76 */
77 /*
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
86 *
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
91 *
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
99 */
100
101 #ifdef HAVE_KERNEL_OPTION_HEADERS
102 #include "opt_device_polling.h"
103 #endif
104
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/taskqueue.h>
114
115 #include <net/if.h>
116 #include <net/if_arp.h>
117 #include <net/ethernet.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_types.h>
121
122 #include <net/bpf.h>
123
124 #include <machine/bus.h>
125 #include <machine/resource.h>
126 #include <sys/bus.h>
127 #include <sys/rman.h>
128
129 #include <dev/mii/mii.h>
130 #include <dev/mii/mii_bitbang.h>
131 #include <dev/mii/miivar.h>
132
133 #include <dev/pci/pcireg.h>
134 #include <dev/pci/pcivar.h>
135
136 MODULE_DEPEND(xl, pci, 1, 1, 1);
137 MODULE_DEPEND(xl, ether, 1, 1, 1);
138 MODULE_DEPEND(xl, miibus, 1, 1, 1);
139
140 /* "device miibus" required. See GENERIC if you get errors here. */
141 #include "miibus_if.h"
142
143 #include <dev/xl/if_xlreg.h>
144
145 /*
146 * TX Checksumming is disabled by default for two reasons:
147 * - TX Checksumming will occasionally produce corrupt packets
148 * - TX Checksumming seems to reduce performance
149 *
150 * Only 905B/C cards were reported to have this problem, it is possible
151 * that later chips _may_ be immune.
152 */
153 #define XL905B_TXCSUM_BROKEN 1
154
155 #ifdef XL905B_TXCSUM_BROKEN
156 #define XL905B_CSUM_FEATURES 0
157 #else
158 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159 #endif
160
161 /*
162 * Various supported device vendors/types and their names.
163 */
164 static const struct xl_type const xl_devs[] = {
165 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
166 "3Com 3c900-TPO Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
168 "3Com 3c900-COMBO Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
170 "3Com 3c905-TX Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
172 "3Com 3c905-T4 Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
174 "3Com 3c900B-TPO Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
176 "3Com 3c900B-COMBO Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
178 "3Com 3c900B-TPC Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
180 "3Com 3c900B-FL Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
182 "3Com 3c905B-TX Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
184 "3Com 3c905B-T4 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
186 "3Com 3c905B-FX/SC Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
188 "3Com 3c905B-COMBO Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
190 "3Com 3c905C-TX Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
192 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
194 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
196 "3Com 3c980 Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
198 "3Com 3c980C Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
200 "3Com 3cSOHO100-TX OfficeConnect" },
201 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
202 "3Com 3c450-TX HomeConnect" },
203 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
204 "3Com 3c555 Fast Etherlink XL" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
206 "3Com 3c556 Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
208 "3Com 3c556B Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
210 "3Com 3c575TX Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
212 "3Com 3c575B Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
214 "3Com 3c575C Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
216 "3Com 3c656 Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
218 "3Com 3c656B Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
220 "3Com 3c656C Fast Etherlink XL" },
221 { 0, 0, NULL }
222 };
223
224 static int xl_probe(device_t);
225 static int xl_attach(device_t);
226 static int xl_detach(device_t);
227
228 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
229 static void xl_tick(void *);
230 static void xl_stats_update(struct xl_softc *);
231 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
232 static int xl_rxeof(struct xl_softc *);
233 static void xl_rxeof_task(void *, int);
234 static int xl_rx_resync(struct xl_softc *);
235 static void xl_txeof(struct xl_softc *);
236 static void xl_txeof_90xB(struct xl_softc *);
237 static void xl_txeoc(struct xl_softc *);
238 static void xl_intr(void *);
239 static void xl_start(struct ifnet *);
240 static void xl_start_locked(struct ifnet *);
241 static void xl_start_90xB_locked(struct ifnet *);
242 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
243 static void xl_init(void *);
244 static void xl_init_locked(struct xl_softc *);
245 static void xl_stop(struct xl_softc *);
246 static int xl_watchdog(struct xl_softc *);
247 static int xl_shutdown(device_t);
248 static int xl_suspend(device_t);
249 static int xl_resume(device_t);
250 static void xl_setwol(struct xl_softc *);
251
252 #ifdef DEVICE_POLLING
253 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
254 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
255 #endif
256
257 static int xl_ifmedia_upd(struct ifnet *);
258 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
259
260 static int xl_eeprom_wait(struct xl_softc *);
261 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
262
263 static void xl_rxfilter(struct xl_softc *);
264 static void xl_rxfilter_90x(struct xl_softc *);
265 static void xl_rxfilter_90xB(struct xl_softc *);
266 static void xl_setcfg(struct xl_softc *);
267 static void xl_setmode(struct xl_softc *, int);
268 static void xl_reset(struct xl_softc *);
269 static int xl_list_rx_init(struct xl_softc *);
270 static int xl_list_tx_init(struct xl_softc *);
271 static int xl_list_tx_init_90xB(struct xl_softc *);
272 static void xl_wait(struct xl_softc *);
273 static void xl_mediacheck(struct xl_softc *);
274 static void xl_choose_media(struct xl_softc *sc, int *media);
275 static void xl_choose_xcvr(struct xl_softc *, int);
276 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
277 #ifdef notdef
278 static void xl_testpacket(struct xl_softc *);
279 #endif
280
281 static int xl_miibus_readreg(device_t, int, int);
282 static int xl_miibus_writereg(device_t, int, int, int);
283 static void xl_miibus_statchg(device_t);
284 static void xl_miibus_mediainit(device_t);
285
286 /*
287 * MII bit-bang glue
288 */
289 static uint32_t xl_mii_bitbang_read(device_t);
290 static void xl_mii_bitbang_write(device_t, uint32_t);
291
292 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
293 xl_mii_bitbang_read,
294 xl_mii_bitbang_write,
295 {
296 XL_MII_DATA, /* MII_BIT_MDO */
297 XL_MII_DATA, /* MII_BIT_MDI */
298 XL_MII_CLK, /* MII_BIT_MDC */
299 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
300 0, /* MII_BIT_DIR_PHY_HOST */
301 }
302 };
303
304 static device_method_t xl_methods[] = {
305 /* Device interface */
306 DEVMETHOD(device_probe, xl_probe),
307 DEVMETHOD(device_attach, xl_attach),
308 DEVMETHOD(device_detach, xl_detach),
309 DEVMETHOD(device_shutdown, xl_shutdown),
310 DEVMETHOD(device_suspend, xl_suspend),
311 DEVMETHOD(device_resume, xl_resume),
312
313 /* bus interface */
314 DEVMETHOD(bus_print_child, bus_generic_print_child),
315 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
316
317 /* MII interface */
318 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
319 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
320 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
321 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
322
323 { 0, 0 }
324 };
325
326 static driver_t xl_driver = {
327 "xl",
328 xl_methods,
329 sizeof(struct xl_softc)
330 };
331
332 static devclass_t xl_devclass;
333
334 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
335 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
336
337 static void
338 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
339 {
340 u_int32_t *paddr;
341
342 paddr = arg;
343 *paddr = segs->ds_addr;
344 }
345
346 /*
347 * Murphy's law says that it's possible the chip can wedge and
348 * the 'command in progress' bit may never clear. Hence, we wait
349 * only a finite amount of time to avoid getting caught in an
350 * infinite loop. Normally this delay routine would be a macro,
351 * but it isn't called during normal operation so we can afford
352 * to make it a function. Suppress warning when card gone.
353 */
354 static void
355 xl_wait(struct xl_softc *sc)
356 {
357 register int i;
358
359 for (i = 0; i < XL_TIMEOUT; i++) {
360 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
361 break;
362 }
363
364 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
365 device_printf(sc->xl_dev, "command never completed!\n");
366 }
367
368 /*
369 * MII access routines are provided for adapters with external
370 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
371 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
372 * Note: if you don't perform the MDIO operations just right,
373 * it's possible to end up with code that works correctly with
374 * some chips/CPUs/processor speeds/bus speeds/etc but not
375 * with others.
376 */
377
378 /*
379 * Read the MII serial port for the MII bit-bang module.
380 */
381 static uint32_t
382 xl_mii_bitbang_read(device_t dev)
383 {
384 struct xl_softc *sc;
385 uint32_t val;
386
387 sc = device_get_softc(dev);
388
389 /* We're already in window 4. */
390 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
391 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
392 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
393
394 return (val);
395 }
396
397 /*
398 * Write the MII serial port for the MII bit-bang module.
399 */
400 static void
401 xl_mii_bitbang_write(device_t dev, uint32_t val)
402 {
403 struct xl_softc *sc;
404
405 sc = device_get_softc(dev);
406
407 /* We're already in window 4. */
408 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
409 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
410 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
411 }
412
413 static int
414 xl_miibus_readreg(device_t dev, int phy, int reg)
415 {
416 struct xl_softc *sc;
417
418 sc = device_get_softc(dev);
419
420 /* Select the window 4. */
421 XL_SEL_WIN(4);
422
423 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
424 }
425
426 static int
427 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
428 {
429 struct xl_softc *sc;
430
431 sc = device_get_softc(dev);
432
433 /* Select the window 4. */
434 XL_SEL_WIN(4);
435
436 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
437
438 return (0);
439 }
440
441 static void
442 xl_miibus_statchg(device_t dev)
443 {
444 struct xl_softc *sc;
445 struct mii_data *mii;
446 uint8_t macctl;
447
448 sc = device_get_softc(dev);
449 mii = device_get_softc(sc->xl_miibus);
450
451 xl_setcfg(sc);
452
453 /* Set ASIC's duplex mode to match the PHY. */
454 XL_SEL_WIN(3);
455 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
456 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
457 macctl |= XL_MACCTRL_DUPLEX;
458 if (sc->xl_type == XL_TYPE_905B) {
459 if ((IFM_OPTIONS(mii->mii_media_active) &
460 IFM_ETH_RXPAUSE) != 0)
461 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
462 else
463 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
464 }
465 } else {
466 macctl &= ~XL_MACCTRL_DUPLEX;
467 if (sc->xl_type == XL_TYPE_905B)
468 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
469 }
470 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
471 }
472
473 /*
474 * Special support for the 3c905B-COMBO. This card has 10/100 support
475 * plus BNC and AUI ports. This means we will have both an miibus attached
476 * plus some non-MII media settings. In order to allow this, we have to
477 * add the extra media to the miibus's ifmedia struct, but we can't do
478 * that during xl_attach() because the miibus hasn't been attached yet.
479 * So instead, we wait until the miibus probe/attach is done, at which
480 * point we will get a callback telling is that it's safe to add our
481 * extra media.
482 */
483 static void
484 xl_miibus_mediainit(device_t dev)
485 {
486 struct xl_softc *sc;
487 struct mii_data *mii;
488 struct ifmedia *ifm;
489
490 sc = device_get_softc(dev);
491 mii = device_get_softc(sc->xl_miibus);
492 ifm = &mii->mii_media;
493
494 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
495 /*
496 * Check for a 10baseFL board in disguise.
497 */
498 if (sc->xl_type == XL_TYPE_905B &&
499 sc->xl_media == XL_MEDIAOPT_10FL) {
500 if (bootverbose)
501 device_printf(sc->xl_dev, "found 10baseFL\n");
502 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
503 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
504 NULL);
505 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
506 ifmedia_add(ifm,
507 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
508 } else {
509 if (bootverbose)
510 device_printf(sc->xl_dev, "found AUI\n");
511 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
512 }
513 }
514
515 if (sc->xl_media & XL_MEDIAOPT_BNC) {
516 if (bootverbose)
517 device_printf(sc->xl_dev, "found BNC\n");
518 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
519 }
520 }
521
522 /*
523 * The EEPROM is slow: give it time to come ready after issuing
524 * it a command.
525 */
526 static int
527 xl_eeprom_wait(struct xl_softc *sc)
528 {
529 int i;
530
531 for (i = 0; i < 100; i++) {
532 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
533 DELAY(162);
534 else
535 break;
536 }
537
538 if (i == 100) {
539 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
540 return (1);
541 }
542
543 return (0);
544 }
545
546 /*
547 * Read a sequence of words from the EEPROM. Note that ethernet address
548 * data is stored in the EEPROM in network byte order.
549 */
550 static int
551 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
552 {
553 int err = 0, i;
554 u_int16_t word = 0, *ptr;
555
556 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
557 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
558 /*
559 * XXX: WARNING! DANGER!
560 * It's easy to accidentally overwrite the rom content!
561 * Note: the 3c575 uses 8bit EEPROM offsets.
562 */
563 XL_SEL_WIN(0);
564
565 if (xl_eeprom_wait(sc))
566 return (1);
567
568 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
569 off += 0x30;
570
571 for (i = 0; i < cnt; i++) {
572 if (sc->xl_flags & XL_FLAG_8BITROM)
573 CSR_WRITE_2(sc, XL_W0_EE_CMD,
574 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
575 else
576 CSR_WRITE_2(sc, XL_W0_EE_CMD,
577 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
578 err = xl_eeprom_wait(sc);
579 if (err)
580 break;
581 word = CSR_READ_2(sc, XL_W0_EE_DATA);
582 ptr = (u_int16_t *)(dest + (i * 2));
583 if (swap)
584 *ptr = ntohs(word);
585 else
586 *ptr = word;
587 }
588
589 return (err ? 1 : 0);
590 }
591
592 static void
593 xl_rxfilter(struct xl_softc *sc)
594 {
595
596 if (sc->xl_type == XL_TYPE_905B)
597 xl_rxfilter_90xB(sc);
598 else
599 xl_rxfilter_90x(sc);
600 }
601
602 /*
603 * NICs older than the 3c905B have only one multicast option, which
604 * is to enable reception of all multicast frames.
605 */
606 static void
607 xl_rxfilter_90x(struct xl_softc *sc)
608 {
609 struct ifnet *ifp;
610 struct ifmultiaddr *ifma;
611 u_int8_t rxfilt;
612
613 XL_LOCK_ASSERT(sc);
614
615 ifp = sc->xl_ifp;
616
617 XL_SEL_WIN(5);
618 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
619 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
620 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
621
622 /* Set the individual bit to receive frames for this host only. */
623 rxfilt |= XL_RXFILTER_INDIVIDUAL;
624 /* Set capture broadcast bit to capture broadcast frames. */
625 if (ifp->if_flags & IFF_BROADCAST)
626 rxfilt |= XL_RXFILTER_BROADCAST;
627
628 /* If we want promiscuous mode, set the allframes bit. */
629 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
630 if (ifp->if_flags & IFF_PROMISC)
631 rxfilt |= XL_RXFILTER_ALLFRAMES;
632 if (ifp->if_flags & IFF_ALLMULTI)
633 rxfilt |= XL_RXFILTER_ALLMULTI;
634 } else {
635 if_maddr_rlock(ifp);
636 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
637 if (ifma->ifma_addr->sa_family != AF_LINK)
638 continue;
639 rxfilt |= XL_RXFILTER_ALLMULTI;
640 break;
641 }
642 if_maddr_runlock(ifp);
643 }
644
645 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
646 XL_SEL_WIN(7);
647 }
648
649 /*
650 * 3c905B adapters have a hash filter that we can program.
651 */
652 static void
653 xl_rxfilter_90xB(struct xl_softc *sc)
654 {
655 struct ifnet *ifp;
656 struct ifmultiaddr *ifma;
657 int i, mcnt;
658 u_int16_t h;
659 u_int8_t rxfilt;
660
661 XL_LOCK_ASSERT(sc);
662
663 ifp = sc->xl_ifp;
664
665 XL_SEL_WIN(5);
666 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
667 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
668 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
669 XL_RXFILTER_MULTIHASH);
670
671 /* Set the individual bit to receive frames for this host only. */
672 rxfilt |= XL_RXFILTER_INDIVIDUAL;
673 /* Set capture broadcast bit to capture broadcast frames. */
674 if (ifp->if_flags & IFF_BROADCAST)
675 rxfilt |= XL_RXFILTER_BROADCAST;
676
677 /* If we want promiscuous mode, set the allframes bit. */
678 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
679 if (ifp->if_flags & IFF_PROMISC)
680 rxfilt |= XL_RXFILTER_ALLFRAMES;
681 if (ifp->if_flags & IFF_ALLMULTI)
682 rxfilt |= XL_RXFILTER_ALLMULTI;
683 } else {
684 /* First, zot all the existing hash bits. */
685 for (i = 0; i < XL_HASHFILT_SIZE; i++)
686 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
687
688 /* Now program new ones. */
689 mcnt = 0;
690 if_maddr_rlock(ifp);
691 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
692 if (ifma->ifma_addr->sa_family != AF_LINK)
693 continue;
694 /*
695 * Note: the 3c905B currently only supports a 64-bit
696 * hash table, which means we really only need 6 bits,
697 * but the manual indicates that future chip revisions
698 * will have a 256-bit hash table, hence the routine
699 * is set up to calculate 8 bits of position info in
700 * case we need it some day.
701 * Note II, The Sequel: _CURRENT_ versions of the
702 * 3c905B have a 256 bit hash table. This means we have
703 * to use all 8 bits regardless. On older cards, the
704 * upper 2 bits will be ignored. Grrrr....
705 */
706 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
707 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
708 CSR_WRITE_2(sc, XL_COMMAND,
709 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
710 mcnt++;
711 }
712 if_maddr_runlock(ifp);
713 if (mcnt > 0)
714 rxfilt |= XL_RXFILTER_MULTIHASH;
715 }
716
717 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
718 XL_SEL_WIN(7);
719 }
720
721 static void
722 xl_setcfg(struct xl_softc *sc)
723 {
724 u_int32_t icfg;
725
726 /*XL_LOCK_ASSERT(sc);*/
727
728 XL_SEL_WIN(3);
729 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
730 icfg &= ~XL_ICFG_CONNECTOR_MASK;
731 if (sc->xl_media & XL_MEDIAOPT_MII ||
732 sc->xl_media & XL_MEDIAOPT_BT4)
733 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
734 if (sc->xl_media & XL_MEDIAOPT_BTX)
735 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
736
737 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
739 }
740
741 static void
742 xl_setmode(struct xl_softc *sc, int media)
743 {
744 u_int32_t icfg;
745 u_int16_t mediastat;
746 char *pmsg = "", *dmsg = "";
747
748 XL_LOCK_ASSERT(sc);
749
750 XL_SEL_WIN(4);
751 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
752 XL_SEL_WIN(3);
753 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
754
755 if (sc->xl_media & XL_MEDIAOPT_BT) {
756 if (IFM_SUBTYPE(media) == IFM_10_T) {
757 pmsg = "10baseT transceiver";
758 sc->xl_xcvr = XL_XCVR_10BT;
759 icfg &= ~XL_ICFG_CONNECTOR_MASK;
760 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
761 mediastat |= XL_MEDIASTAT_LINKBEAT |
762 XL_MEDIASTAT_JABGUARD;
763 mediastat &= ~XL_MEDIASTAT_SQEENB;
764 }
765 }
766
767 if (sc->xl_media & XL_MEDIAOPT_BFX) {
768 if (IFM_SUBTYPE(media) == IFM_100_FX) {
769 pmsg = "100baseFX port";
770 sc->xl_xcvr = XL_XCVR_100BFX;
771 icfg &= ~XL_ICFG_CONNECTOR_MASK;
772 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
773 mediastat |= XL_MEDIASTAT_LINKBEAT;
774 mediastat &= ~XL_MEDIASTAT_SQEENB;
775 }
776 }
777
778 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
779 if (IFM_SUBTYPE(media) == IFM_10_5) {
780 pmsg = "AUI port";
781 sc->xl_xcvr = XL_XCVR_AUI;
782 icfg &= ~XL_ICFG_CONNECTOR_MASK;
783 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
784 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
785 XL_MEDIASTAT_JABGUARD);
786 mediastat |= ~XL_MEDIASTAT_SQEENB;
787 }
788 if (IFM_SUBTYPE(media) == IFM_10_FL) {
789 pmsg = "10baseFL transceiver";
790 sc->xl_xcvr = XL_XCVR_AUI;
791 icfg &= ~XL_ICFG_CONNECTOR_MASK;
792 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
793 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
794 XL_MEDIASTAT_JABGUARD);
795 mediastat |= ~XL_MEDIASTAT_SQEENB;
796 }
797 }
798
799 if (sc->xl_media & XL_MEDIAOPT_BNC) {
800 if (IFM_SUBTYPE(media) == IFM_10_2) {
801 pmsg = "AUI port";
802 sc->xl_xcvr = XL_XCVR_COAX;
803 icfg &= ~XL_ICFG_CONNECTOR_MASK;
804 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
805 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
806 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
807 }
808 }
809
810 if ((media & IFM_GMASK) == IFM_FDX ||
811 IFM_SUBTYPE(media) == IFM_100_FX) {
812 dmsg = "full";
813 XL_SEL_WIN(3);
814 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
815 } else {
816 dmsg = "half";
817 XL_SEL_WIN(3);
818 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
819 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
820 }
821
822 if (IFM_SUBTYPE(media) == IFM_10_2)
823 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
824 else
825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
826
827 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
828 XL_SEL_WIN(4);
829 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
830
831 DELAY(800);
832 XL_SEL_WIN(7);
833
834 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
835 }
836
837 static void
838 xl_reset(struct xl_softc *sc)
839 {
840 register int i;
841
842 XL_LOCK_ASSERT(sc);
843
844 XL_SEL_WIN(0);
845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
846 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
847 XL_RESETOPT_DISADVFD:0));
848
849 /*
850 * If we're using memory mapped register mode, pause briefly
851 * after issuing the reset command before trying to access any
852 * other registers. With my 3c575C CardBus card, failing to do
853 * this results in the system locking up while trying to poll
854 * the command busy bit in the status register.
855 */
856 if (sc->xl_flags & XL_FLAG_USE_MMIO)
857 DELAY(100000);
858
859 for (i = 0; i < XL_TIMEOUT; i++) {
860 DELAY(10);
861 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
862 break;
863 }
864
865 if (i == XL_TIMEOUT)
866 device_printf(sc->xl_dev, "reset didn't complete\n");
867
868 /* Reset TX and RX. */
869 /* Note: the RX reset takes an absurd amount of time
870 * on newer versions of the Tornado chips such as those
871 * on the 3c905CX and newer 3c908C cards. We wait an
872 * extra amount of time so that xl_wait() doesn't complain
873 * and annoy the users.
874 */
875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
876 DELAY(100000);
877 xl_wait(sc);
878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
879 xl_wait(sc);
880
881 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
882 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
883 XL_SEL_WIN(2);
884 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
885 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
886 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
887 XL_RESETOPT_INVERT_LED : 0) |
888 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
889 XL_RESETOPT_INVERT_MII : 0));
890 }
891
892 /* Wait a little while for the chip to get its brains in order. */
893 DELAY(100000);
894 }
895
896 /*
897 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
898 * IDs against our list and return a device name if we find a match.
899 */
900 static int
901 xl_probe(device_t dev)
902 {
903 const struct xl_type *t;
904
905 t = xl_devs;
906
907 while (t->xl_name != NULL) {
908 if ((pci_get_vendor(dev) == t->xl_vid) &&
909 (pci_get_device(dev) == t->xl_did)) {
910 device_set_desc(dev, t->xl_name);
911 return (BUS_PROBE_DEFAULT);
912 }
913 t++;
914 }
915
916 return (ENXIO);
917 }
918
919 /*
920 * This routine is a kludge to work around possible hardware faults
921 * or manufacturing defects that can cause the media options register
922 * (or reset options register, as it's called for the first generation
923 * 3c90x adapters) to return an incorrect result. I have encountered
924 * one Dell Latitude laptop docking station with an integrated 3c905-TX
925 * which doesn't have any of the 'mediaopt' bits set. This screws up
926 * the attach routine pretty badly because it doesn't know what media
927 * to look for. If we find ourselves in this predicament, this routine
928 * will try to guess the media options values and warn the user of a
929 * possible manufacturing defect with his adapter/system/whatever.
930 */
931 static void
932 xl_mediacheck(struct xl_softc *sc)
933 {
934
935 /*
936 * If some of the media options bits are set, assume they are
937 * correct. If not, try to figure it out down below.
938 * XXX I should check for 10baseFL, but I don't have an adapter
939 * to test with.
940 */
941 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
942 /*
943 * Check the XCVR value. If it's not in the normal range
944 * of values, we need to fake it up here.
945 */
946 if (sc->xl_xcvr <= XL_XCVR_AUTO)
947 return;
948 else {
949 device_printf(sc->xl_dev,
950 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
951 device_printf(sc->xl_dev,
952 "choosing new default based on card type\n");
953 }
954 } else {
955 if (sc->xl_type == XL_TYPE_905B &&
956 sc->xl_media & XL_MEDIAOPT_10FL)
957 return;
958 device_printf(sc->xl_dev,
959 "WARNING: no media options bits set in the media options register!!\n");
960 device_printf(sc->xl_dev,
961 "this could be a manufacturing defect in your adapter or system\n");
962 device_printf(sc->xl_dev,
963 "attempting to guess media type; you should probably consult your vendor\n");
964 }
965
966 xl_choose_xcvr(sc, 1);
967 }
968
969 static void
970 xl_choose_xcvr(struct xl_softc *sc, int verbose)
971 {
972 u_int16_t devid;
973
974 /*
975 * Read the device ID from the EEPROM.
976 * This is what's loaded into the PCI device ID register, so it has
977 * to be correct otherwise we wouldn't have gotten this far.
978 */
979 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
980
981 switch (devid) {
982 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
983 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
984 sc->xl_media = XL_MEDIAOPT_BT;
985 sc->xl_xcvr = XL_XCVR_10BT;
986 if (verbose)
987 device_printf(sc->xl_dev,
988 "guessing 10BaseT transceiver\n");
989 break;
990 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
991 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
992 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
993 sc->xl_xcvr = XL_XCVR_10BT;
994 if (verbose)
995 device_printf(sc->xl_dev,
996 "guessing COMBO (AUI/BNC/TP)\n");
997 break;
998 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
999 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1000 sc->xl_xcvr = XL_XCVR_10BT;
1001 if (verbose)
1002 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1003 break;
1004 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1005 sc->xl_media = XL_MEDIAOPT_10FL;
1006 sc->xl_xcvr = XL_XCVR_AUI;
1007 if (verbose)
1008 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1009 break;
1010 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1011 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1012 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1013 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1014 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1015 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1016 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1017 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1018 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1019 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1020 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1021 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1022 sc->xl_media = XL_MEDIAOPT_MII;
1023 sc->xl_xcvr = XL_XCVR_MII;
1024 if (verbose)
1025 device_printf(sc->xl_dev, "guessing MII\n");
1026 break;
1027 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1028 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1029 sc->xl_media = XL_MEDIAOPT_BT4;
1030 sc->xl_xcvr = XL_XCVR_MII;
1031 if (verbose)
1032 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1033 break;
1034 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1035 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1036 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1037 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1038 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1039 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1040 sc->xl_media = XL_MEDIAOPT_BTX;
1041 sc->xl_xcvr = XL_XCVR_AUTO;
1042 if (verbose)
1043 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1044 break;
1045 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1046 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1047 sc->xl_xcvr = XL_XCVR_AUTO;
1048 if (verbose)
1049 device_printf(sc->xl_dev,
1050 "guessing 10/100 plus BNC/AUI\n");
1051 break;
1052 default:
1053 device_printf(sc->xl_dev,
1054 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1055 sc->xl_media = XL_MEDIAOPT_BT;
1056 break;
1057 }
1058 }
1059
1060 /*
1061 * Attach the interface. Allocate softc structures, do ifmedia
1062 * setup and ethernet/BPF attach.
1063 */
1064 static int
1065 xl_attach(device_t dev)
1066 {
1067 u_char eaddr[ETHER_ADDR_LEN];
1068 u_int16_t sinfo2, xcvr[2];
1069 struct xl_softc *sc;
1070 struct ifnet *ifp;
1071 int media, pmcap;
1072 int error = 0, phy, rid, res, unit;
1073 uint16_t did;
1074
1075 sc = device_get_softc(dev);
1076 sc->xl_dev = dev;
1077
1078 unit = device_get_unit(dev);
1079
1080 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1081 MTX_DEF);
1082 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1083
1084 did = pci_get_device(dev);
1085
1086 sc->xl_flags = 0;
1087 if (did == TC_DEVICEID_HURRICANE_555)
1088 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1089 if (did == TC_DEVICEID_HURRICANE_556 ||
1090 did == TC_DEVICEID_HURRICANE_556B)
1091 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1092 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1093 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1094 if (did == TC_DEVICEID_HURRICANE_555 ||
1095 did == TC_DEVICEID_HURRICANE_556)
1096 sc->xl_flags |= XL_FLAG_8BITROM;
1097 if (did == TC_DEVICEID_HURRICANE_556B)
1098 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1099
1100 if (did == TC_DEVICEID_HURRICANE_575B ||
1101 did == TC_DEVICEID_HURRICANE_575C ||
1102 did == TC_DEVICEID_HURRICANE_656B ||
1103 did == TC_DEVICEID_TORNADO_656C)
1104 sc->xl_flags |= XL_FLAG_FUNCREG;
1105 if (did == TC_DEVICEID_HURRICANE_575A ||
1106 did == TC_DEVICEID_HURRICANE_575B ||
1107 did == TC_DEVICEID_HURRICANE_575C ||
1108 did == TC_DEVICEID_HURRICANE_656B ||
1109 did == TC_DEVICEID_TORNADO_656C)
1110 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1111 XL_FLAG_8BITROM;
1112 if (did == TC_DEVICEID_HURRICANE_656)
1113 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1114 if (did == TC_DEVICEID_HURRICANE_575B)
1115 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1116 if (did == TC_DEVICEID_HURRICANE_575C)
1117 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1118 if (did == TC_DEVICEID_TORNADO_656C)
1119 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1120 if (did == TC_DEVICEID_HURRICANE_656 ||
1121 did == TC_DEVICEID_HURRICANE_656B)
1122 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1123 XL_FLAG_INVERT_LED_PWR;
1124 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1125 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1126 sc->xl_flags |= XL_FLAG_PHYOK;
1127
1128 switch (did) {
1129 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1130 case TC_DEVICEID_HURRICANE_575A:
1131 case TC_DEVICEID_HURRICANE_575B:
1132 case TC_DEVICEID_HURRICANE_575C:
1133 sc->xl_flags |= XL_FLAG_NO_MMIO;
1134 break;
1135 default:
1136 break;
1137 }
1138
1139 /*
1140 * Map control/status registers.
1141 */
1142 pci_enable_busmaster(dev);
1143
1144 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1145 rid = XL_PCI_LOMEM;
1146 res = SYS_RES_MEMORY;
1147
1148 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1149 }
1150
1151 if (sc->xl_res != NULL) {
1152 sc->xl_flags |= XL_FLAG_USE_MMIO;
1153 if (bootverbose)
1154 device_printf(dev, "using memory mapped I/O\n");
1155 } else {
1156 rid = XL_PCI_LOIO;
1157 res = SYS_RES_IOPORT;
1158 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1159 if (sc->xl_res == NULL) {
1160 device_printf(dev, "couldn't map ports/memory\n");
1161 error = ENXIO;
1162 goto fail;
1163 }
1164 if (bootverbose)
1165 device_printf(dev, "using port I/O\n");
1166 }
1167
1168 sc->xl_btag = rman_get_bustag(sc->xl_res);
1169 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1170
1171 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1172 rid = XL_PCI_FUNCMEM;
1173 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1174 RF_ACTIVE);
1175
1176 if (sc->xl_fres == NULL) {
1177 device_printf(dev, "couldn't map funcreg memory\n");
1178 error = ENXIO;
1179 goto fail;
1180 }
1181
1182 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1183 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1184 }
1185
1186 /* Allocate interrupt */
1187 rid = 0;
1188 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1189 RF_SHAREABLE | RF_ACTIVE);
1190 if (sc->xl_irq == NULL) {
1191 device_printf(dev, "couldn't map interrupt\n");
1192 error = ENXIO;
1193 goto fail;
1194 }
1195
1196 /* Initialize interface name. */
1197 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1198 if (ifp == NULL) {
1199 device_printf(dev, "can not if_alloc()\n");
1200 error = ENOSPC;
1201 goto fail;
1202 }
1203 ifp->if_softc = sc;
1204 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1205
1206 /* Reset the adapter. */
1207 XL_LOCK(sc);
1208 xl_reset(sc);
1209 XL_UNLOCK(sc);
1210
1211 /*
1212 * Get station address from the EEPROM.
1213 */
1214 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1215 device_printf(dev, "failed to read station address\n");
1216 error = ENXIO;
1217 goto fail;
1218 }
1219
1220 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1221 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1222
1223 /*
1224 * Now allocate a tag for the DMA descriptor lists and a chunk
1225 * of DMA-able memory based on the tag. Also obtain the DMA
1226 * addresses of the RX and TX ring, which we'll need later.
1227 * All of our lists are allocated as a contiguous block
1228 * of memory.
1229 */
1230 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1231 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1232 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1233 &sc->xl_ldata.xl_rx_tag);
1234 if (error) {
1235 device_printf(dev, "failed to allocate rx dma tag\n");
1236 goto fail;
1237 }
1238
1239 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1240 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1241 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1242 if (error) {
1243 device_printf(dev, "no memory for rx list buffers!\n");
1244 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1245 sc->xl_ldata.xl_rx_tag = NULL;
1246 goto fail;
1247 }
1248
1249 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1250 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1251 XL_RX_LIST_SZ, xl_dma_map_addr,
1252 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1253 if (error) {
1254 device_printf(dev, "cannot get dma address of the rx ring!\n");
1255 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1256 sc->xl_ldata.xl_rx_dmamap);
1257 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1258 sc->xl_ldata.xl_rx_tag = NULL;
1259 goto fail;
1260 }
1261
1262 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1263 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1264 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1265 &sc->xl_ldata.xl_tx_tag);
1266 if (error) {
1267 device_printf(dev, "failed to allocate tx dma tag\n");
1268 goto fail;
1269 }
1270
1271 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1272 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1273 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1274 if (error) {
1275 device_printf(dev, "no memory for list buffers!\n");
1276 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1277 sc->xl_ldata.xl_tx_tag = NULL;
1278 goto fail;
1279 }
1280
1281 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1282 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1283 XL_TX_LIST_SZ, xl_dma_map_addr,
1284 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1285 if (error) {
1286 device_printf(dev, "cannot get dma address of the tx ring!\n");
1287 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1288 sc->xl_ldata.xl_tx_dmamap);
1289 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1290 sc->xl_ldata.xl_tx_tag = NULL;
1291 goto fail;
1292 }
1293
1294 /*
1295 * Allocate a DMA tag for the mapping of mbufs.
1296 */
1297 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1298 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1299 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1300 NULL, &sc->xl_mtag);
1301 if (error) {
1302 device_printf(dev, "failed to allocate mbuf dma tag\n");
1303 goto fail;
1304 }
1305
1306 /* We need a spare DMA map for the RX ring. */
1307 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1308 if (error)
1309 goto fail;
1310
1311 /*
1312 * Figure out the card type. 3c905B adapters have the
1313 * 'supportsNoTxLength' bit set in the capabilities
1314 * word in the EEPROM.
1315 * Note: my 3c575C CardBus card lies. It returns a value
1316 * of 0x1578 for its capabilities word, which is somewhat
1317 * nonsensical. Another way to distinguish a 3c90x chip
1318 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1319 * bit. This will only be set for 3c90x boomerage chips.
1320 */
1321 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1322 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1323 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1324 sc->xl_type = XL_TYPE_905B;
1325 else
1326 sc->xl_type = XL_TYPE_90X;
1327
1328 /* Check availability of WOL. */
1329 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1330 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1331 sc->xl_pmcap = pmcap;
1332 sc->xl_flags |= XL_FLAG_WOL;
1333 sinfo2 = 0;
1334 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1335 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1336 device_printf(dev,
1337 "No auxiliary remote wakeup connector!\n");
1338 }
1339
1340 /* Set the TX start threshold for best performance. */
1341 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1342
1343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1344 ifp->if_ioctl = xl_ioctl;
1345 ifp->if_capabilities = IFCAP_VLAN_MTU;
1346 if (sc->xl_type == XL_TYPE_905B) {
1347 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1348 #ifdef XL905B_TXCSUM_BROKEN
1349 ifp->if_capabilities |= IFCAP_RXCSUM;
1350 #else
1351 ifp->if_capabilities |= IFCAP_HWCSUM;
1352 #endif
1353 }
1354 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1355 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1356 ifp->if_capenable = ifp->if_capabilities;
1357 #ifdef DEVICE_POLLING
1358 ifp->if_capabilities |= IFCAP_POLLING;
1359 #endif
1360 ifp->if_start = xl_start;
1361 ifp->if_init = xl_init;
1362 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1363 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1364 IFQ_SET_READY(&ifp->if_snd);
1365
1366 /*
1367 * Now we have to see what sort of media we have.
1368 * This includes probing for an MII interace and a
1369 * possible PHY.
1370 */
1371 XL_SEL_WIN(3);
1372 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1373 if (bootverbose)
1374 device_printf(dev, "media options word: %x\n", sc->xl_media);
1375
1376 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1377 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1378 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1379 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1380
1381 xl_mediacheck(sc);
1382
1383 if (sc->xl_media & XL_MEDIAOPT_MII ||
1384 sc->xl_media & XL_MEDIAOPT_BTX ||
1385 sc->xl_media & XL_MEDIAOPT_BT4) {
1386 if (bootverbose)
1387 device_printf(dev, "found MII/AUTO\n");
1388 xl_setcfg(sc);
1389 /*
1390 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1391 * This is to guard against problems with certain 3Com ASIC
1392 * revisions that incorrectly map the internal transceiver
1393 * control registers at all MII addresses.
1394 */
1395 phy = MII_PHY_ANY;
1396 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1397 phy = 24;
1398 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1399 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1400 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1401 if (error != 0) {
1402 device_printf(dev, "attaching PHYs failed\n");
1403 goto fail;
1404 }
1405 goto done;
1406 }
1407
1408 /*
1409 * Sanity check. If the user has selected "auto" and this isn't
1410 * a 10/100 card of some kind, we need to force the transceiver
1411 * type to something sane.
1412 */
1413 if (sc->xl_xcvr == XL_XCVR_AUTO)
1414 xl_choose_xcvr(sc, bootverbose);
1415
1416 /*
1417 * Do ifmedia setup.
1418 */
1419 if (sc->xl_media & XL_MEDIAOPT_BT) {
1420 if (bootverbose)
1421 device_printf(dev, "found 10baseT\n");
1422 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1423 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1424 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1425 ifmedia_add(&sc->ifmedia,
1426 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1427 }
1428
1429 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1430 /*
1431 * Check for a 10baseFL board in disguise.
1432 */
1433 if (sc->xl_type == XL_TYPE_905B &&
1434 sc->xl_media == XL_MEDIAOPT_10FL) {
1435 if (bootverbose)
1436 device_printf(dev, "found 10baseFL\n");
1437 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1438 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1439 0, NULL);
1440 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1441 ifmedia_add(&sc->ifmedia,
1442 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1443 } else {
1444 if (bootverbose)
1445 device_printf(dev, "found AUI\n");
1446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1447 }
1448 }
1449
1450 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1451 if (bootverbose)
1452 device_printf(dev, "found BNC\n");
1453 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1454 }
1455
1456 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1457 if (bootverbose)
1458 device_printf(dev, "found 100baseFX\n");
1459 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1460 }
1461
1462 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1463 xl_choose_media(sc, &media);
1464
1465 if (sc->xl_miibus == NULL)
1466 ifmedia_set(&sc->ifmedia, media);
1467
1468 done:
1469 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1470 XL_SEL_WIN(0);
1471 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1472 }
1473
1474 /*
1475 * Call MI attach routine.
1476 */
1477 ether_ifattach(ifp, eaddr);
1478
1479 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1480 NULL, xl_intr, sc, &sc->xl_intrhand);
1481 if (error) {
1482 device_printf(dev, "couldn't set up irq\n");
1483 ether_ifdetach(ifp);
1484 goto fail;
1485 }
1486
1487 fail:
1488 if (error)
1489 xl_detach(dev);
1490
1491 return (error);
1492 }
1493
1494 /*
1495 * Choose a default media.
1496 * XXX This is a leaf function only called by xl_attach() and
1497 * acquires/releases the non-recursible driver mutex to
1498 * satisfy lock assertions.
1499 */
1500 static void
1501 xl_choose_media(struct xl_softc *sc, int *media)
1502 {
1503
1504 XL_LOCK(sc);
1505
1506 switch (sc->xl_xcvr) {
1507 case XL_XCVR_10BT:
1508 *media = IFM_ETHER|IFM_10_T;
1509 xl_setmode(sc, *media);
1510 break;
1511 case XL_XCVR_AUI:
1512 if (sc->xl_type == XL_TYPE_905B &&
1513 sc->xl_media == XL_MEDIAOPT_10FL) {
1514 *media = IFM_ETHER|IFM_10_FL;
1515 xl_setmode(sc, *media);
1516 } else {
1517 *media = IFM_ETHER|IFM_10_5;
1518 xl_setmode(sc, *media);
1519 }
1520 break;
1521 case XL_XCVR_COAX:
1522 *media = IFM_ETHER|IFM_10_2;
1523 xl_setmode(sc, *media);
1524 break;
1525 case XL_XCVR_AUTO:
1526 case XL_XCVR_100BTX:
1527 case XL_XCVR_MII:
1528 /* Chosen by miibus */
1529 break;
1530 case XL_XCVR_100BFX:
1531 *media = IFM_ETHER|IFM_100_FX;
1532 break;
1533 default:
1534 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1535 sc->xl_xcvr);
1536 /*
1537 * This will probably be wrong, but it prevents
1538 * the ifmedia code from panicking.
1539 */
1540 *media = IFM_ETHER|IFM_10_T;
1541 break;
1542 }
1543
1544 XL_UNLOCK(sc);
1545 }
1546
1547 /*
1548 * Shutdown hardware and free up resources. This can be called any
1549 * time after the mutex has been initialized. It is called in both
1550 * the error case in attach and the normal detach case so it needs
1551 * to be careful about only freeing resources that have actually been
1552 * allocated.
1553 */
1554 static int
1555 xl_detach(device_t dev)
1556 {
1557 struct xl_softc *sc;
1558 struct ifnet *ifp;
1559 int rid, res;
1560
1561 sc = device_get_softc(dev);
1562 ifp = sc->xl_ifp;
1563
1564 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1565
1566 #ifdef DEVICE_POLLING
1567 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1568 ether_poll_deregister(ifp);
1569 #endif
1570
1571 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1572 rid = XL_PCI_LOMEM;
1573 res = SYS_RES_MEMORY;
1574 } else {
1575 rid = XL_PCI_LOIO;
1576 res = SYS_RES_IOPORT;
1577 }
1578
1579 /* These should only be active if attach succeeded */
1580 if (device_is_attached(dev)) {
1581 XL_LOCK(sc);
1582 xl_stop(sc);
1583 XL_UNLOCK(sc);
1584 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1585 callout_drain(&sc->xl_tick_callout);
1586 ether_ifdetach(ifp);
1587 }
1588 if (sc->xl_miibus)
1589 device_delete_child(dev, sc->xl_miibus);
1590 bus_generic_detach(dev);
1591 ifmedia_removeall(&sc->ifmedia);
1592
1593 if (sc->xl_intrhand)
1594 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1595 if (sc->xl_irq)
1596 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1597 if (sc->xl_fres != NULL)
1598 bus_release_resource(dev, SYS_RES_MEMORY,
1599 XL_PCI_FUNCMEM, sc->xl_fres);
1600 if (sc->xl_res)
1601 bus_release_resource(dev, res, rid, sc->xl_res);
1602
1603 if (ifp)
1604 if_free(ifp);
1605
1606 if (sc->xl_mtag) {
1607 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1608 bus_dma_tag_destroy(sc->xl_mtag);
1609 }
1610 if (sc->xl_ldata.xl_rx_tag) {
1611 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1612 sc->xl_ldata.xl_rx_dmamap);
1613 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1614 sc->xl_ldata.xl_rx_dmamap);
1615 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1616 }
1617 if (sc->xl_ldata.xl_tx_tag) {
1618 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1619 sc->xl_ldata.xl_tx_dmamap);
1620 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1621 sc->xl_ldata.xl_tx_dmamap);
1622 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1623 }
1624
1625 mtx_destroy(&sc->xl_mtx);
1626
1627 return (0);
1628 }
1629
1630 /*
1631 * Initialize the transmit descriptors.
1632 */
1633 static int
1634 xl_list_tx_init(struct xl_softc *sc)
1635 {
1636 struct xl_chain_data *cd;
1637 struct xl_list_data *ld;
1638 int error, i;
1639
1640 XL_LOCK_ASSERT(sc);
1641
1642 cd = &sc->xl_cdata;
1643 ld = &sc->xl_ldata;
1644 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1645 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1646 error = bus_dmamap_create(sc->xl_mtag, 0,
1647 &cd->xl_tx_chain[i].xl_map);
1648 if (error)
1649 return (error);
1650 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1651 i * sizeof(struct xl_list);
1652 if (i == (XL_TX_LIST_CNT - 1))
1653 cd->xl_tx_chain[i].xl_next = NULL;
1654 else
1655 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1656 }
1657
1658 cd->xl_tx_free = &cd->xl_tx_chain[0];
1659 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1660
1661 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1662 return (0);
1663 }
1664
1665 /*
1666 * Initialize the transmit descriptors.
1667 */
1668 static int
1669 xl_list_tx_init_90xB(struct xl_softc *sc)
1670 {
1671 struct xl_chain_data *cd;
1672 struct xl_list_data *ld;
1673 int error, i;
1674
1675 XL_LOCK_ASSERT(sc);
1676
1677 cd = &sc->xl_cdata;
1678 ld = &sc->xl_ldata;
1679 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1680 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1681 error = bus_dmamap_create(sc->xl_mtag, 0,
1682 &cd->xl_tx_chain[i].xl_map);
1683 if (error)
1684 return (error);
1685 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1686 i * sizeof(struct xl_list);
1687 if (i == (XL_TX_LIST_CNT - 1))
1688 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1689 else
1690 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1691 if (i == 0)
1692 cd->xl_tx_chain[i].xl_prev =
1693 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1694 else
1695 cd->xl_tx_chain[i].xl_prev =
1696 &cd->xl_tx_chain[i - 1];
1697 }
1698
1699 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1700 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1701
1702 cd->xl_tx_prod = 1;
1703 cd->xl_tx_cons = 1;
1704 cd->xl_tx_cnt = 0;
1705
1706 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1707 return (0);
1708 }
1709
1710 /*
1711 * Initialize the RX descriptors and allocate mbufs for them. Note that
1712 * we arrange the descriptors in a closed ring, so that the last descriptor
1713 * points back to the first.
1714 */
1715 static int
1716 xl_list_rx_init(struct xl_softc *sc)
1717 {
1718 struct xl_chain_data *cd;
1719 struct xl_list_data *ld;
1720 int error, i, next;
1721 u_int32_t nextptr;
1722
1723 XL_LOCK_ASSERT(sc);
1724
1725 cd = &sc->xl_cdata;
1726 ld = &sc->xl_ldata;
1727
1728 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1729 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1730 error = bus_dmamap_create(sc->xl_mtag, 0,
1731 &cd->xl_rx_chain[i].xl_map);
1732 if (error)
1733 return (error);
1734 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1735 if (error)
1736 return (error);
1737 if (i == (XL_RX_LIST_CNT - 1))
1738 next = 0;
1739 else
1740 next = i + 1;
1741 nextptr = ld->xl_rx_dmaaddr +
1742 next * sizeof(struct xl_list_onefrag);
1743 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1744 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1745 }
1746
1747 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1748 cd->xl_rx_head = &cd->xl_rx_chain[0];
1749
1750 return (0);
1751 }
1752
1753 /*
1754 * Initialize an RX descriptor and attach an MBUF cluster.
1755 * If we fail to do so, we need to leave the old mbuf and
1756 * the old DMA map untouched so that it can be reused.
1757 */
1758 static int
1759 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1760 {
1761 struct mbuf *m_new = NULL;
1762 bus_dmamap_t map;
1763 bus_dma_segment_t segs[1];
1764 int error, nseg;
1765
1766 XL_LOCK_ASSERT(sc);
1767
1768 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1769 if (m_new == NULL)
1770 return (ENOBUFS);
1771
1772 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1773
1774 /* Force longword alignment for packet payload. */
1775 m_adj(m_new, ETHER_ALIGN);
1776
1777 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1778 segs, &nseg, BUS_DMA_NOWAIT);
1779 if (error) {
1780 m_freem(m_new);
1781 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1782 error);
1783 return (error);
1784 }
1785 KASSERT(nseg == 1,
1786 ("%s: too many DMA segments (%d)", __func__, nseg));
1787
1788 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1789 map = c->xl_map;
1790 c->xl_map = sc->xl_tmpmap;
1791 sc->xl_tmpmap = map;
1792 c->xl_mbuf = m_new;
1793 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1794 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1795 c->xl_ptr->xl_status = 0;
1796 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1797 return (0);
1798 }
1799
1800 static int
1801 xl_rx_resync(struct xl_softc *sc)
1802 {
1803 struct xl_chain_onefrag *pos;
1804 int i;
1805
1806 XL_LOCK_ASSERT(sc);
1807
1808 pos = sc->xl_cdata.xl_rx_head;
1809
1810 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1811 if (pos->xl_ptr->xl_status)
1812 break;
1813 pos = pos->xl_next;
1814 }
1815
1816 if (i == XL_RX_LIST_CNT)
1817 return (0);
1818
1819 sc->xl_cdata.xl_rx_head = pos;
1820
1821 return (EAGAIN);
1822 }
1823
1824 /*
1825 * A frame has been uploaded: pass the resulting mbuf chain up to
1826 * the higher level protocols.
1827 */
1828 static int
1829 xl_rxeof(struct xl_softc *sc)
1830 {
1831 struct mbuf *m;
1832 struct ifnet *ifp = sc->xl_ifp;
1833 struct xl_chain_onefrag *cur_rx;
1834 int total_len;
1835 int rx_npkts = 0;
1836 u_int32_t rxstat;
1837
1838 XL_LOCK_ASSERT(sc);
1839 again:
1840 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1841 BUS_DMASYNC_POSTREAD);
1842 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1843 #ifdef DEVICE_POLLING
1844 if (ifp->if_capenable & IFCAP_POLLING) {
1845 if (sc->rxcycles <= 0)
1846 break;
1847 sc->rxcycles--;
1848 }
1849 #endif
1850 cur_rx = sc->xl_cdata.xl_rx_head;
1851 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1852 total_len = rxstat & XL_RXSTAT_LENMASK;
1853 rx_npkts++;
1854
1855 /*
1856 * Since we have told the chip to allow large frames,
1857 * we need to trap giant frame errors in software. We allow
1858 * a little more than the normal frame size to account for
1859 * frames with VLAN tags.
1860 */
1861 if (total_len > XL_MAX_FRAMELEN)
1862 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1863
1864 /*
1865 * If an error occurs, update stats, clear the
1866 * status word and leave the mbuf cluster in place:
1867 * it should simply get re-used next time this descriptor
1868 * comes up in the ring.
1869 */
1870 if (rxstat & XL_RXSTAT_UP_ERROR) {
1871 ifp->if_ierrors++;
1872 cur_rx->xl_ptr->xl_status = 0;
1873 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1874 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1875 continue;
1876 }
1877
1878 /*
1879 * If the error bit was not set, the upload complete
1880 * bit should be set which means we have a valid packet.
1881 * If not, something truly strange has happened.
1882 */
1883 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1884 device_printf(sc->xl_dev,
1885 "bad receive status -- packet dropped\n");
1886 ifp->if_ierrors++;
1887 cur_rx->xl_ptr->xl_status = 0;
1888 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1889 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1890 continue;
1891 }
1892
1893 /* No errors; receive the packet. */
1894 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1895 BUS_DMASYNC_POSTREAD);
1896 m = cur_rx->xl_mbuf;
1897
1898 /*
1899 * Try to conjure up a new mbuf cluster. If that
1900 * fails, it means we have an out of memory condition and
1901 * should leave the buffer in place and continue. This will
1902 * result in a lost packet, but there's little else we
1903 * can do in this situation.
1904 */
1905 if (xl_newbuf(sc, cur_rx)) {
1906 ifp->if_ierrors++;
1907 cur_rx->xl_ptr->xl_status = 0;
1908 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1909 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1910 continue;
1911 }
1912 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1913 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1914
1915 ifp->if_ipackets++;
1916 m->m_pkthdr.rcvif = ifp;
1917 m->m_pkthdr.len = m->m_len = total_len;
1918
1919 if (ifp->if_capenable & IFCAP_RXCSUM) {
1920 /* Do IP checksum checking. */
1921 if (rxstat & XL_RXSTAT_IPCKOK)
1922 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1923 if (!(rxstat & XL_RXSTAT_IPCKERR))
1924 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1925 if ((rxstat & XL_RXSTAT_TCPCOK &&
1926 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1927 (rxstat & XL_RXSTAT_UDPCKOK &&
1928 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1929 m->m_pkthdr.csum_flags |=
1930 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1931 m->m_pkthdr.csum_data = 0xffff;
1932 }
1933 }
1934
1935 XL_UNLOCK(sc);
1936 (*ifp->if_input)(ifp, m);
1937 XL_LOCK(sc);
1938
1939 /*
1940 * If we are running from the taskqueue, the interface
1941 * might have been stopped while we were passing the last
1942 * packet up the network stack.
1943 */
1944 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1945 return (rx_npkts);
1946 }
1947
1948 /*
1949 * Handle the 'end of channel' condition. When the upload
1950 * engine hits the end of the RX ring, it will stall. This
1951 * is our cue to flush the RX ring, reload the uplist pointer
1952 * register and unstall the engine.
1953 * XXX This is actually a little goofy. With the ThunderLAN
1954 * chip, you get an interrupt when the receiver hits the end
1955 * of the receive ring, which tells you exactly when you
1956 * you need to reload the ring pointer. Here we have to
1957 * fake it. I'm mad at myself for not being clever enough
1958 * to avoid the use of a goto here.
1959 */
1960 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1961 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1963 xl_wait(sc);
1964 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1965 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1967 goto again;
1968 }
1969 return (rx_npkts);
1970 }
1971
1972 /*
1973 * Taskqueue wrapper for xl_rxeof().
1974 */
1975 static void
1976 xl_rxeof_task(void *arg, int pending)
1977 {
1978 struct xl_softc *sc = (struct xl_softc *)arg;
1979
1980 XL_LOCK(sc);
1981 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1982 xl_rxeof(sc);
1983 XL_UNLOCK(sc);
1984 }
1985
1986 /*
1987 * A frame was downloaded to the chip. It's safe for us to clean up
1988 * the list buffers.
1989 */
1990 static void
1991 xl_txeof(struct xl_softc *sc)
1992 {
1993 struct xl_chain *cur_tx;
1994 struct ifnet *ifp = sc->xl_ifp;
1995
1996 XL_LOCK_ASSERT(sc);
1997
1998 /*
1999 * Go through our tx list and free mbufs for those
2000 * frames that have been uploaded. Note: the 3c905B
2001 * sets a special bit in the status word to let us
2002 * know that a frame has been downloaded, but the
2003 * original 3c900/3c905 adapters don't do that.
2004 * Consequently, we have to use a different test if
2005 * xl_type != XL_TYPE_905B.
2006 */
2007 while (sc->xl_cdata.xl_tx_head != NULL) {
2008 cur_tx = sc->xl_cdata.xl_tx_head;
2009
2010 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2011 break;
2012
2013 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2014 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2015 BUS_DMASYNC_POSTWRITE);
2016 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2017 m_freem(cur_tx->xl_mbuf);
2018 cur_tx->xl_mbuf = NULL;
2019 ifp->if_opackets++;
2020 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2021
2022 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2023 sc->xl_cdata.xl_tx_free = cur_tx;
2024 }
2025
2026 if (sc->xl_cdata.xl_tx_head == NULL) {
2027 sc->xl_wdog_timer = 0;
2028 sc->xl_cdata.xl_tx_tail = NULL;
2029 } else {
2030 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2031 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2032 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2033 sc->xl_cdata.xl_tx_head->xl_phys);
2034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2035 }
2036 }
2037 }
2038
2039 static void
2040 xl_txeof_90xB(struct xl_softc *sc)
2041 {
2042 struct xl_chain *cur_tx = NULL;
2043 struct ifnet *ifp = sc->xl_ifp;
2044 int idx;
2045
2046 XL_LOCK_ASSERT(sc);
2047
2048 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2049 BUS_DMASYNC_POSTREAD);
2050 idx = sc->xl_cdata.xl_tx_cons;
2051 while (idx != sc->xl_cdata.xl_tx_prod) {
2052 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2053
2054 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2055 XL_TXSTAT_DL_COMPLETE))
2056 break;
2057
2058 if (cur_tx->xl_mbuf != NULL) {
2059 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2060 BUS_DMASYNC_POSTWRITE);
2061 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2062 m_freem(cur_tx->xl_mbuf);
2063 cur_tx->xl_mbuf = NULL;
2064 }
2065
2066 ifp->if_opackets++;
2067
2068 sc->xl_cdata.xl_tx_cnt--;
2069 XL_INC(idx, XL_TX_LIST_CNT);
2070 }
2071
2072 if (sc->xl_cdata.xl_tx_cnt == 0)
2073 sc->xl_wdog_timer = 0;
2074 sc->xl_cdata.xl_tx_cons = idx;
2075
2076 if (cur_tx != NULL)
2077 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2078 }
2079
2080 /*
2081 * TX 'end of channel' interrupt handler. Actually, we should
2082 * only get a 'TX complete' interrupt if there's a transmit error,
2083 * so this is really TX error handler.
2084 */
2085 static void
2086 xl_txeoc(struct xl_softc *sc)
2087 {
2088 u_int8_t txstat;
2089
2090 XL_LOCK_ASSERT(sc);
2091
2092 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2093 if (txstat & XL_TXSTATUS_UNDERRUN ||
2094 txstat & XL_TXSTATUS_JABBER ||
2095 txstat & XL_TXSTATUS_RECLAIM) {
2096 device_printf(sc->xl_dev,
2097 "transmission error: 0x%02x\n", txstat);
2098 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2099 xl_wait(sc);
2100 if (sc->xl_type == XL_TYPE_905B) {
2101 if (sc->xl_cdata.xl_tx_cnt) {
2102 int i;
2103 struct xl_chain *c;
2104
2105 i = sc->xl_cdata.xl_tx_cons;
2106 c = &sc->xl_cdata.xl_tx_chain[i];
2107 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2108 c->xl_phys);
2109 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2110 sc->xl_wdog_timer = 5;
2111 }
2112 } else {
2113 if (sc->xl_cdata.xl_tx_head != NULL) {
2114 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2115 sc->xl_cdata.xl_tx_head->xl_phys);
2116 sc->xl_wdog_timer = 5;
2117 }
2118 }
2119 /*
2120 * Remember to set this for the
2121 * first generation 3c90X chips.
2122 */
2123 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2124 if (txstat & XL_TXSTATUS_UNDERRUN &&
2125 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2126 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2127 device_printf(sc->xl_dev,
2128 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2129 }
2130 CSR_WRITE_2(sc, XL_COMMAND,
2131 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2132 if (sc->xl_type == XL_TYPE_905B) {
2133 CSR_WRITE_2(sc, XL_COMMAND,
2134 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2135 }
2136 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2137 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2138 } else {
2139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2141 }
2142 /*
2143 * Write an arbitrary byte to the TX_STATUS register
2144 * to clear this interrupt/error and advance to the next.
2145 */
2146 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2147 }
2148 }
2149
2150 static void
2151 xl_intr(void *arg)
2152 {
2153 struct xl_softc *sc = arg;
2154 struct ifnet *ifp = sc->xl_ifp;
2155 u_int16_t status;
2156
2157 XL_LOCK(sc);
2158
2159 #ifdef DEVICE_POLLING
2160 if (ifp->if_capenable & IFCAP_POLLING) {
2161 XL_UNLOCK(sc);
2162 return;
2163 }
2164 #endif
2165
2166 for (;;) {
2167 status = CSR_READ_2(sc, XL_STATUS);
2168 if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2169 break;
2170 CSR_WRITE_2(sc, XL_COMMAND,
2171 XL_CMD_INTR_ACK|(status & XL_INTRS));
2172 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2173 break;
2174
2175 if (status & XL_STAT_UP_COMPLETE) {
2176 if (xl_rxeof(sc) == 0) {
2177 while (xl_rx_resync(sc))
2178 xl_rxeof(sc);
2179 }
2180 }
2181
2182 if (status & XL_STAT_DOWN_COMPLETE) {
2183 if (sc->xl_type == XL_TYPE_905B)
2184 xl_txeof_90xB(sc);
2185 else
2186 xl_txeof(sc);
2187 }
2188
2189 if (status & XL_STAT_TX_COMPLETE) {
2190 ifp->if_oerrors++;
2191 xl_txeoc(sc);
2192 }
2193
2194 if (status & XL_STAT_ADFAIL) {
2195 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2196 xl_init_locked(sc);
2197 break;
2198 }
2199
2200 if (status & XL_STAT_STATSOFLOW)
2201 xl_stats_update(sc);
2202 }
2203
2204 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2205 ifp->if_drv_flags & IFF_DRV_RUNNING) {
2206 if (sc->xl_type == XL_TYPE_905B)
2207 xl_start_90xB_locked(ifp);
2208 else
2209 xl_start_locked(ifp);
2210 }
2211
2212 XL_UNLOCK(sc);
2213 }
2214
2215 #ifdef DEVICE_POLLING
2216 static int
2217 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2218 {
2219 struct xl_softc *sc = ifp->if_softc;
2220 int rx_npkts = 0;
2221
2222 XL_LOCK(sc);
2223 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2224 rx_npkts = xl_poll_locked(ifp, cmd, count);
2225 XL_UNLOCK(sc);
2226 return (rx_npkts);
2227 }
2228
2229 static int
2230 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2231 {
2232 struct xl_softc *sc = ifp->if_softc;
2233 int rx_npkts;
2234
2235 XL_LOCK_ASSERT(sc);
2236
2237 sc->rxcycles = count;
2238 rx_npkts = xl_rxeof(sc);
2239 if (sc->xl_type == XL_TYPE_905B)
2240 xl_txeof_90xB(sc);
2241 else
2242 xl_txeof(sc);
2243
2244 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2245 if (sc->xl_type == XL_TYPE_905B)
2246 xl_start_90xB_locked(ifp);
2247 else
2248 xl_start_locked(ifp);
2249 }
2250
2251 if (cmd == POLL_AND_CHECK_STATUS) {
2252 u_int16_t status;
2253
2254 status = CSR_READ_2(sc, XL_STATUS);
2255 if (status & XL_INTRS && status != 0xFFFF) {
2256 CSR_WRITE_2(sc, XL_COMMAND,
2257 XL_CMD_INTR_ACK|(status & XL_INTRS));
2258
2259 if (status & XL_STAT_TX_COMPLETE) {
2260 ifp->if_oerrors++;
2261 xl_txeoc(sc);
2262 }
2263
2264 if (status & XL_STAT_ADFAIL) {
2265 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2266 xl_init_locked(sc);
2267 }
2268
2269 if (status & XL_STAT_STATSOFLOW)
2270 xl_stats_update(sc);
2271 }
2272 }
2273 return (rx_npkts);
2274 }
2275 #endif /* DEVICE_POLLING */
2276
2277 static void
2278 xl_tick(void *xsc)
2279 {
2280 struct xl_softc *sc = xsc;
2281 struct mii_data *mii;
2282
2283 XL_LOCK_ASSERT(sc);
2284
2285 if (sc->xl_miibus != NULL) {
2286 mii = device_get_softc(sc->xl_miibus);
2287 mii_tick(mii);
2288 }
2289
2290 xl_stats_update(sc);
2291 if (xl_watchdog(sc) == EJUSTRETURN)
2292 return;
2293
2294 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2295 }
2296
2297 static void
2298 xl_stats_update(struct xl_softc *sc)
2299 {
2300 struct ifnet *ifp = sc->xl_ifp;
2301 struct xl_stats xl_stats;
2302 u_int8_t *p;
2303 int i;
2304
2305 XL_LOCK_ASSERT(sc);
2306
2307 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2308
2309 p = (u_int8_t *)&xl_stats;
2310
2311 /* Read all the stats registers. */
2312 XL_SEL_WIN(6);
2313
2314 for (i = 0; i < 16; i++)
2315 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2316
2317 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2318
2319 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2320 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2321
2322 /*
2323 * Boomerang and cyclone chips have an extra stats counter
2324 * in window 4 (BadSSD). We have to read this too in order
2325 * to clear out all the stats registers and avoid a statsoflow
2326 * interrupt.
2327 */
2328 XL_SEL_WIN(4);
2329 CSR_READ_1(sc, XL_W4_BADSSD);
2330 XL_SEL_WIN(7);
2331 }
2332
2333 /*
2334 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2335 * pointers to the fragment pointers.
2336 */
2337 static int
2338 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2339 {
2340 struct mbuf *m_new;
2341 struct ifnet *ifp = sc->xl_ifp;
2342 int error, i, nseg, total_len;
2343 u_int32_t status;
2344
2345 XL_LOCK_ASSERT(sc);
2346
2347 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2348 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2349
2350 if (error && error != EFBIG) {
2351 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2352 return (error);
2353 }
2354
2355 /*
2356 * Handle special case: we used up all 63 fragments,
2357 * but we have more mbufs left in the chain. Copy the
2358 * data into an mbuf cluster. Note that we don't
2359 * bother clearing the values in the other fragment
2360 * pointers/counters; it wouldn't gain us anything,
2361 * and would waste cycles.
2362 */
2363 if (error) {
2364 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS);
2365 if (m_new == NULL) {
2366 m_freem(*m_head);
2367 *m_head = NULL;
2368 return (ENOBUFS);
2369 }
2370 *m_head = m_new;
2371
2372 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2373 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2374 if (error) {
2375 m_freem(*m_head);
2376 *m_head = NULL;
2377 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2378 return (error);
2379 }
2380 }
2381
2382 KASSERT(nseg <= XL_MAXFRAGS,
2383 ("%s: too many DMA segments (%d)", __func__, nseg));
2384 if (nseg == 0) {
2385 m_freem(*m_head);
2386 *m_head = NULL;
2387 return (EIO);
2388 }
2389 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2390
2391 total_len = 0;
2392 for (i = 0; i < nseg; i++) {
2393 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2394 ("segment size too large"));
2395 c->xl_ptr->xl_frag[i].xl_addr =
2396 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2397 c->xl_ptr->xl_frag[i].xl_len =
2398 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2399 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2400 }
2401 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2402
2403 if (sc->xl_type == XL_TYPE_905B) {
2404 status = XL_TXSTAT_RND_DEFEAT;
2405
2406 #ifndef XL905B_TXCSUM_BROKEN
2407 if ((*m_head)->m_pkthdr.csum_flags) {
2408 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2409 status |= XL_TXSTAT_IPCKSUM;
2410 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2411 status |= XL_TXSTAT_TCPCKSUM;
2412 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2413 status |= XL_TXSTAT_UDPCKSUM;
2414 }
2415 #endif
2416 } else
2417 status = total_len;
2418 c->xl_ptr->xl_status = htole32(status);
2419 c->xl_ptr->xl_next = 0;
2420
2421 c->xl_mbuf = *m_head;
2422 return (0);
2423 }
2424
2425 /*
2426 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2427 * to the mbuf data regions directly in the transmit lists. We also save a
2428 * copy of the pointers since the transmit list fragment pointers are
2429 * physical addresses.
2430 */
2431
2432 static void
2433 xl_start(struct ifnet *ifp)
2434 {
2435 struct xl_softc *sc = ifp->if_softc;
2436
2437 XL_LOCK(sc);
2438
2439 if (sc->xl_type == XL_TYPE_905B)
2440 xl_start_90xB_locked(ifp);
2441 else
2442 xl_start_locked(ifp);
2443
2444 XL_UNLOCK(sc);
2445 }
2446
2447 static void
2448 xl_start_locked(struct ifnet *ifp)
2449 {
2450 struct xl_softc *sc = ifp->if_softc;
2451 struct mbuf *m_head;
2452 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2453 struct xl_chain *prev_tx;
2454 int error;
2455
2456 XL_LOCK_ASSERT(sc);
2457
2458 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2459 IFF_DRV_RUNNING)
2460 return;
2461 /*
2462 * Check for an available queue slot. If there are none,
2463 * punt.
2464 */
2465 if (sc->xl_cdata.xl_tx_free == NULL) {
2466 xl_txeoc(sc);
2467 xl_txeof(sc);
2468 if (sc->xl_cdata.xl_tx_free == NULL) {
2469 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2470 return;
2471 }
2472 }
2473
2474 start_tx = sc->xl_cdata.xl_tx_free;
2475
2476 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2477 sc->xl_cdata.xl_tx_free != NULL;) {
2478 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2479 if (m_head == NULL)
2480 break;
2481
2482 /* Pick a descriptor off the free list. */
2483 prev_tx = cur_tx;
2484 cur_tx = sc->xl_cdata.xl_tx_free;
2485
2486 /* Pack the data into the descriptor. */
2487 error = xl_encap(sc, cur_tx, &m_head);
2488 if (error) {
2489 cur_tx = prev_tx;
2490 if (m_head == NULL)
2491 break;
2492 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2493 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2494 break;
2495 }
2496
2497 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2498 cur_tx->xl_next = NULL;
2499
2500 /* Chain it together. */
2501 if (prev != NULL) {
2502 prev->xl_next = cur_tx;
2503 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2504 }
2505 prev = cur_tx;
2506
2507 /*
2508 * If there's a BPF listener, bounce a copy of this frame
2509 * to him.
2510 */
2511 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2512 }
2513
2514 /*
2515 * If there are no packets queued, bail.
2516 */
2517 if (cur_tx == NULL)
2518 return;
2519
2520 /*
2521 * Place the request for the upload interrupt
2522 * in the last descriptor in the chain. This way, if
2523 * we're chaining several packets at once, we'll only
2524 * get an interrupt once for the whole chain rather than
2525 * once for each packet.
2526 */
2527 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2528
2529 /*
2530 * Queue the packets. If the TX channel is clear, update
2531 * the downlist pointer register.
2532 */
2533 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2534 xl_wait(sc);
2535
2536 if (sc->xl_cdata.xl_tx_head != NULL) {
2537 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2538 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2539 htole32(start_tx->xl_phys);
2540 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2541 htole32(~XL_TXSTAT_DL_INTR);
2542 sc->xl_cdata.xl_tx_tail = cur_tx;
2543 } else {
2544 sc->xl_cdata.xl_tx_head = start_tx;
2545 sc->xl_cdata.xl_tx_tail = cur_tx;
2546 }
2547 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2548 BUS_DMASYNC_PREWRITE);
2549 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2550 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2551
2552 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2553
2554 XL_SEL_WIN(7);
2555
2556 /*
2557 * Set a timeout in case the chip goes out to lunch.
2558 */
2559 sc->xl_wdog_timer = 5;
2560
2561 /*
2562 * XXX Under certain conditions, usually on slower machines
2563 * where interrupts may be dropped, it's possible for the
2564 * adapter to chew up all the buffers in the receive ring
2565 * and stall, without us being able to do anything about it.
2566 * To guard against this, we need to make a pass over the
2567 * RX queue to make sure there aren't any packets pending.
2568 * Doing it here means we can flush the receive ring at the
2569 * same time the chip is DMAing the transmit descriptors we
2570 * just gave it.
2571 *
2572 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2573 * nature of their chips in all their marketing literature;
2574 * we may as well take advantage of it. :)
2575 */
2576 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2577 }
2578
2579 static void
2580 xl_start_90xB_locked(struct ifnet *ifp)
2581 {
2582 struct xl_softc *sc = ifp->if_softc;
2583 struct mbuf *m_head;
2584 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2585 struct xl_chain *prev_tx;
2586 int error, idx;
2587
2588 XL_LOCK_ASSERT(sc);
2589
2590 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2591 IFF_DRV_RUNNING)
2592 return;
2593
2594 idx = sc->xl_cdata.xl_tx_prod;
2595 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2596
2597 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2598 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2599 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2600 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2601 break;
2602 }
2603
2604 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2605 if (m_head == NULL)
2606 break;
2607
2608 prev_tx = cur_tx;
2609 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2610
2611 /* Pack the data into the descriptor. */
2612 error = xl_encap(sc, cur_tx, &m_head);
2613 if (error) {
2614 cur_tx = prev_tx;
2615 if (m_head == NULL)
2616 break;
2617 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2618 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2619 break;
2620 }
2621
2622 /* Chain it together. */
2623 if (prev != NULL)
2624 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2625 prev = cur_tx;
2626
2627 /*
2628 * If there's a BPF listener, bounce a copy of this frame
2629 * to him.
2630 */
2631 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2632
2633 XL_INC(idx, XL_TX_LIST_CNT);
2634 sc->xl_cdata.xl_tx_cnt++;
2635 }
2636
2637 /*
2638 * If there are no packets queued, bail.
2639 */
2640 if (cur_tx == NULL)
2641 return;
2642
2643 /*
2644 * Place the request for the upload interrupt
2645 * in the last descriptor in the chain. This way, if
2646 * we're chaining several packets at once, we'll only
2647 * get an interrupt once for the whole chain rather than
2648 * once for each packet.
2649 */
2650 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2651
2652 /* Start transmission */
2653 sc->xl_cdata.xl_tx_prod = idx;
2654 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2655 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2656 BUS_DMASYNC_PREWRITE);
2657
2658 /*
2659 * Set a timeout in case the chip goes out to lunch.
2660 */
2661 sc->xl_wdog_timer = 5;
2662 }
2663
2664 static void
2665 xl_init(void *xsc)
2666 {
2667 struct xl_softc *sc = xsc;
2668
2669 XL_LOCK(sc);
2670 xl_init_locked(sc);
2671 XL_UNLOCK(sc);
2672 }
2673
2674 static void
2675 xl_init_locked(struct xl_softc *sc)
2676 {
2677 struct ifnet *ifp = sc->xl_ifp;
2678 int error, i;
2679 struct mii_data *mii = NULL;
2680
2681 XL_LOCK_ASSERT(sc);
2682
2683 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2684 return;
2685 /*
2686 * Cancel pending I/O and free all RX/TX buffers.
2687 */
2688 xl_stop(sc);
2689
2690 /* Reset the chip to a known state. */
2691 xl_reset(sc);
2692
2693 if (sc->xl_miibus == NULL) {
2694 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2695 xl_wait(sc);
2696 }
2697 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2698 xl_wait(sc);
2699 DELAY(10000);
2700
2701 if (sc->xl_miibus != NULL)
2702 mii = device_get_softc(sc->xl_miibus);
2703
2704 /*
2705 * Clear WOL status and disable all WOL feature as WOL
2706 * would interfere Rx operation under normal environments.
2707 */
2708 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2709 XL_SEL_WIN(7);
2710 CSR_READ_2(sc, XL_W7_BM_PME);
2711 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2712 }
2713 /* Init our MAC address */
2714 XL_SEL_WIN(2);
2715 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2716 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2717 IF_LLADDR(sc->xl_ifp)[i]);
2718 }
2719
2720 /* Clear the station mask. */
2721 for (i = 0; i < 3; i++)
2722 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2723 #ifdef notdef
2724 /* Reset TX and RX. */
2725 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2726 xl_wait(sc);
2727 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2728 xl_wait(sc);
2729 #endif
2730 /* Init circular RX list. */
2731 error = xl_list_rx_init(sc);
2732 if (error) {
2733 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2734 error);
2735 xl_stop(sc);
2736 return;
2737 }
2738
2739 /* Init TX descriptors. */
2740 if (sc->xl_type == XL_TYPE_905B)
2741 error = xl_list_tx_init_90xB(sc);
2742 else
2743 error = xl_list_tx_init(sc);
2744 if (error) {
2745 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2746 error);
2747 xl_stop(sc);
2748 return;
2749 }
2750
2751 /*
2752 * Set the TX freethresh value.
2753 * Note that this has no effect on 3c905B "cyclone"
2754 * cards but is required for 3c900/3c905 "boomerang"
2755 * cards in order to enable the download engine.
2756 */
2757 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2758
2759 /* Set the TX start threshold for best performance. */
2760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2761
2762 /*
2763 * If this is a 3c905B, also set the tx reclaim threshold.
2764 * This helps cut down on the number of tx reclaim errors
2765 * that could happen on a busy network. The chip multiplies
2766 * the register value by 16 to obtain the actual threshold
2767 * in bytes, so we divide by 16 when setting the value here.
2768 * The existing threshold value can be examined by reading
2769 * the register at offset 9 in window 5.
2770 */
2771 if (sc->xl_type == XL_TYPE_905B) {
2772 CSR_WRITE_2(sc, XL_COMMAND,
2773 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2774 }
2775
2776 /* Set RX filter bits. */
2777 xl_rxfilter(sc);
2778
2779 /*
2780 * Load the address of the RX list. We have to
2781 * stall the upload engine before we can manipulate
2782 * the uplist pointer register, then unstall it when
2783 * we're finished. We also have to wait for the
2784 * stall command to complete before proceeding.
2785 * Note that we have to do this after any RX resets
2786 * have completed since the uplist register is cleared
2787 * by a reset.
2788 */
2789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2790 xl_wait(sc);
2791 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2793 xl_wait(sc);
2794
2795 if (sc->xl_type == XL_TYPE_905B) {
2796 /* Set polling interval */
2797 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2798 /* Load the address of the TX list */
2799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2800 xl_wait(sc);
2801 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2802 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2804 xl_wait(sc);
2805 }
2806
2807 /*
2808 * If the coax transceiver is on, make sure to enable
2809 * the DC-DC converter.
2810 */
2811 XL_SEL_WIN(3);
2812 if (sc->xl_xcvr == XL_XCVR_COAX)
2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2814 else
2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2816
2817 /*
2818 * increase packet size to allow reception of 802.1q or ISL packets.
2819 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2820 * control register. For 3c90xB/C chips, use the RX packet size
2821 * register.
2822 */
2823
2824 if (sc->xl_type == XL_TYPE_905B)
2825 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2826 else {
2827 u_int8_t macctl;
2828 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2829 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2830 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2831 }
2832
2833 /* Clear out the stats counters. */
2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2835 xl_stats_update(sc);
2836 XL_SEL_WIN(4);
2837 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2839
2840 /*
2841 * Enable interrupts.
2842 */
2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2845 #ifdef DEVICE_POLLING
2846 /* Disable interrupts if we are polling. */
2847 if (ifp->if_capenable & IFCAP_POLLING)
2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2849 else
2850 #endif
2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2852 if (sc->xl_flags & XL_FLAG_FUNCREG)
2853 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2854
2855 /* Set the RX early threshold */
2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2857 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2858
2859 /* Enable receiver and transmitter. */
2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2861 xl_wait(sc);
2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2863 xl_wait(sc);
2864
2865 /* XXX Downcall to miibus. */
2866 if (mii != NULL)
2867 mii_mediachg(mii);
2868
2869 /* Select window 7 for normal operations. */
2870 XL_SEL_WIN(7);
2871
2872 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2873 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2874
2875 sc->xl_wdog_timer = 0;
2876 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2877 }
2878
2879 /*
2880 * Set media options.
2881 */
2882 static int
2883 xl_ifmedia_upd(struct ifnet *ifp)
2884 {
2885 struct xl_softc *sc = ifp->if_softc;
2886 struct ifmedia *ifm = NULL;
2887 struct mii_data *mii = NULL;
2888
2889 XL_LOCK(sc);
2890
2891 if (sc->xl_miibus != NULL)
2892 mii = device_get_softc(sc->xl_miibus);
2893 if (mii == NULL)
2894 ifm = &sc->ifmedia;
2895 else
2896 ifm = &mii->mii_media;
2897
2898 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2899 case IFM_100_FX:
2900 case IFM_10_FL:
2901 case IFM_10_2:
2902 case IFM_10_5:
2903 xl_setmode(sc, ifm->ifm_media);
2904 XL_UNLOCK(sc);
2905 return (0);
2906 }
2907
2908 if (sc->xl_media & XL_MEDIAOPT_MII ||
2909 sc->xl_media & XL_MEDIAOPT_BTX ||
2910 sc->xl_media & XL_MEDIAOPT_BT4) {
2911 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2912 xl_init_locked(sc);
2913 } else {
2914 xl_setmode(sc, ifm->ifm_media);
2915 }
2916
2917 XL_UNLOCK(sc);
2918
2919 return (0);
2920 }
2921
2922 /*
2923 * Report current media status.
2924 */
2925 static void
2926 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2927 {
2928 struct xl_softc *sc = ifp->if_softc;
2929 u_int32_t icfg;
2930 u_int16_t status = 0;
2931 struct mii_data *mii = NULL;
2932
2933 XL_LOCK(sc);
2934
2935 if (sc->xl_miibus != NULL)
2936 mii = device_get_softc(sc->xl_miibus);
2937
2938 XL_SEL_WIN(4);
2939 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2940
2941 XL_SEL_WIN(3);
2942 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2943 icfg >>= XL_ICFG_CONNECTOR_BITS;
2944
2945 ifmr->ifm_active = IFM_ETHER;
2946 ifmr->ifm_status = IFM_AVALID;
2947
2948 if ((status & XL_MEDIASTAT_CARRIER) == 0)
2949 ifmr->ifm_status |= IFM_ACTIVE;
2950
2951 switch (icfg) {
2952 case XL_XCVR_10BT:
2953 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2954 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2955 ifmr->ifm_active |= IFM_FDX;
2956 else
2957 ifmr->ifm_active |= IFM_HDX;
2958 break;
2959 case XL_XCVR_AUI:
2960 if (sc->xl_type == XL_TYPE_905B &&
2961 sc->xl_media == XL_MEDIAOPT_10FL) {
2962 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2963 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2964 ifmr->ifm_active |= IFM_FDX;
2965 else
2966 ifmr->ifm_active |= IFM_HDX;
2967 } else
2968 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2969 break;
2970 case XL_XCVR_COAX:
2971 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2972 break;
2973 /*
2974 * XXX MII and BTX/AUTO should be separate cases.
2975 */
2976
2977 case XL_XCVR_100BTX:
2978 case XL_XCVR_AUTO:
2979 case XL_XCVR_MII:
2980 if (mii != NULL) {
2981 mii_pollstat(mii);
2982 ifmr->ifm_active = mii->mii_media_active;
2983 ifmr->ifm_status = mii->mii_media_status;
2984 }
2985 break;
2986 case XL_XCVR_100BFX:
2987 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2988 break;
2989 default:
2990 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
2991 break;
2992 }
2993
2994 XL_UNLOCK(sc);
2995 }
2996
2997 static int
2998 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2999 {
3000 struct xl_softc *sc = ifp->if_softc;
3001 struct ifreq *ifr = (struct ifreq *) data;
3002 int error = 0, mask;
3003 struct mii_data *mii = NULL;
3004
3005 switch (command) {
3006 case SIOCSIFFLAGS:
3007 XL_LOCK(sc);
3008 if (ifp->if_flags & IFF_UP) {
3009 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3010 (ifp->if_flags ^ sc->xl_if_flags) &
3011 (IFF_PROMISC | IFF_ALLMULTI))
3012 xl_rxfilter(sc);
3013 else
3014 xl_init_locked(sc);
3015 } else {
3016 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3017 xl_stop(sc);
3018 }
3019 sc->xl_if_flags = ifp->if_flags;
3020 XL_UNLOCK(sc);
3021 break;
3022 case SIOCADDMULTI:
3023 case SIOCDELMULTI:
3024 /* XXX Downcall from if_addmulti() possibly with locks held. */
3025 XL_LOCK(sc);
3026 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3027 xl_rxfilter(sc);
3028 XL_UNLOCK(sc);
3029 break;
3030 case SIOCGIFMEDIA:
3031 case SIOCSIFMEDIA:
3032 if (sc->xl_miibus != NULL)
3033 mii = device_get_softc(sc->xl_miibus);
3034 if (mii == NULL)
3035 error = ifmedia_ioctl(ifp, ifr,
3036 &sc->ifmedia, command);
3037 else
3038 error = ifmedia_ioctl(ifp, ifr,
3039 &mii->mii_media, command);
3040 break;
3041 case SIOCSIFCAP:
3042 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3043 #ifdef DEVICE_POLLING
3044 if ((mask & IFCAP_POLLING) != 0 &&
3045 (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3046 ifp->if_capenable ^= IFCAP_POLLING;
3047 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3048 error = ether_poll_register(xl_poll, ifp);
3049 if (error)
3050 break;
3051 XL_LOCK(sc);
3052 /* Disable interrupts */
3053 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3054 ifp->if_capenable |= IFCAP_POLLING;
3055 XL_UNLOCK(sc);
3056 } else {
3057 error = ether_poll_deregister(ifp);
3058 /* Enable interrupts. */
3059 XL_LOCK(sc);
3060 CSR_WRITE_2(sc, XL_COMMAND,
3061 XL_CMD_INTR_ACK | 0xFF);
3062 CSR_WRITE_2(sc, XL_COMMAND,
3063 XL_CMD_INTR_ENB | XL_INTRS);
3064 if (sc->xl_flags & XL_FLAG_FUNCREG)
3065 bus_space_write_4(sc->xl_ftag,
3066 sc->xl_fhandle, 4, 0x8000);
3067 XL_UNLOCK(sc);
3068 }
3069 }
3070 #endif /* DEVICE_POLLING */
3071 XL_LOCK(sc);
3072 if ((mask & IFCAP_TXCSUM) != 0 &&
3073 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3074 ifp->if_capenable ^= IFCAP_TXCSUM;
3075 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3076 ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3077 else
3078 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3079 }
3080 if ((mask & IFCAP_RXCSUM) != 0 &&
3081 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3082 ifp->if_capenable ^= IFCAP_RXCSUM;
3083 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3084 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3085 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3086 XL_UNLOCK(sc);
3087 break;
3088 default:
3089 error = ether_ioctl(ifp, command, data);
3090 break;
3091 }
3092
3093 return (error);
3094 }
3095
3096 static int
3097 xl_watchdog(struct xl_softc *sc)
3098 {
3099 struct ifnet *ifp = sc->xl_ifp;
3100 u_int16_t status = 0;
3101 int misintr;
3102
3103 XL_LOCK_ASSERT(sc);
3104
3105 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3106 return (0);
3107
3108 xl_rxeof(sc);
3109 xl_txeoc(sc);
3110 misintr = 0;
3111 if (sc->xl_type == XL_TYPE_905B) {
3112 xl_txeof_90xB(sc);
3113 if (sc->xl_cdata.xl_tx_cnt == 0)
3114 misintr++;
3115 } else {
3116 xl_txeof(sc);
3117 if (sc->xl_cdata.xl_tx_head == NULL)
3118 misintr++;
3119 }
3120 if (misintr != 0) {
3121 device_printf(sc->xl_dev,
3122 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3123 return (0);
3124 }
3125
3126 ifp->if_oerrors++;
3127 XL_SEL_WIN(4);
3128 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3129 device_printf(sc->xl_dev, "watchdog timeout\n");
3130
3131 if (status & XL_MEDIASTAT_CARRIER)
3132 device_printf(sc->xl_dev,
3133 "no carrier - transceiver cable problem?\n");
3134
3135 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3136 xl_init_locked(sc);
3137
3138 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3139 if (sc->xl_type == XL_TYPE_905B)
3140 xl_start_90xB_locked(ifp);
3141 else
3142 xl_start_locked(ifp);
3143 }
3144
3145 return (EJUSTRETURN);
3146 }
3147
3148 /*
3149 * Stop the adapter and free any mbufs allocated to the
3150 * RX and TX lists.
3151 */
3152 static void
3153 xl_stop(struct xl_softc *sc)
3154 {
3155 register int i;
3156 struct ifnet *ifp = sc->xl_ifp;
3157
3158 XL_LOCK_ASSERT(sc);
3159
3160 sc->xl_wdog_timer = 0;
3161
3162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3166 xl_wait(sc);
3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3169 DELAY(800);
3170
3171 #ifdef foo
3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3173 xl_wait(sc);
3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3175 xl_wait(sc);
3176 #endif
3177
3178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3181 if (sc->xl_flags & XL_FLAG_FUNCREG)
3182 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3183
3184 /* Stop the stats updater. */
3185 callout_stop(&sc->xl_tick_callout);
3186
3187 /*
3188 * Free data in the RX lists.
3189 */
3190 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3191 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3192 bus_dmamap_unload(sc->xl_mtag,
3193 sc->xl_cdata.xl_rx_chain[i].xl_map);
3194 bus_dmamap_destroy(sc->xl_mtag,
3195 sc->xl_cdata.xl_rx_chain[i].xl_map);
3196 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3197 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3198 }
3199 }
3200 if (sc->xl_ldata.xl_rx_list != NULL)
3201 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3202 /*
3203 * Free the TX list buffers.
3204 */
3205 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3206 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3207 bus_dmamap_unload(sc->xl_mtag,
3208 sc->xl_cdata.xl_tx_chain[i].xl_map);
3209 bus_dmamap_destroy(sc->xl_mtag,
3210 sc->xl_cdata.xl_tx_chain[i].xl_map);
3211 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3212 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3213 }
3214 }
3215 if (sc->xl_ldata.xl_tx_list != NULL)
3216 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3217
3218 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3219 }
3220
3221 /*
3222 * Stop all chip I/O so that the kernel's probe routines don't
3223 * get confused by errant DMAs when rebooting.
3224 */
3225 static int
3226 xl_shutdown(device_t dev)
3227 {
3228
3229 return (xl_suspend(dev));
3230 }
3231
3232 static int
3233 xl_suspend(device_t dev)
3234 {
3235 struct xl_softc *sc;
3236
3237 sc = device_get_softc(dev);
3238
3239 XL_LOCK(sc);
3240 xl_stop(sc);
3241 xl_setwol(sc);
3242 XL_UNLOCK(sc);
3243
3244 return (0);
3245 }
3246
3247 static int
3248 xl_resume(device_t dev)
3249 {
3250 struct xl_softc *sc;
3251 struct ifnet *ifp;
3252
3253 sc = device_get_softc(dev);
3254 ifp = sc->xl_ifp;
3255
3256 XL_LOCK(sc);
3257
3258 if (ifp->if_flags & IFF_UP) {
3259 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3260 xl_init_locked(sc);
3261 }
3262
3263 XL_UNLOCK(sc);
3264
3265 return (0);
3266 }
3267
3268 static void
3269 xl_setwol(struct xl_softc *sc)
3270 {
3271 struct ifnet *ifp;
3272 u_int16_t cfg, pmstat;
3273
3274 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3275 return;
3276
3277 ifp = sc->xl_ifp;
3278 XL_SEL_WIN(7);
3279 /* Clear any pending PME events. */
3280 CSR_READ_2(sc, XL_W7_BM_PME);
3281 cfg = 0;
3282 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3283 cfg |= XL_BM_PME_MAGIC;
3284 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3285 /* Enable RX. */
3286 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3288 /* Request PME. */
3289 pmstat = pci_read_config(sc->xl_dev,
3290 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3291 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3292 pmstat |= PCIM_PSTAT_PMEENABLE;
3293 else
3294 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3295 pci_write_config(sc->xl_dev,
3296 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);
3297 }
Cache object: 89f82c3fe23872756fae1deb5bb1260b
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