The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/drivers/dp8390/3c503.h

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    1 /*
    2  *      3c503.h         A shared memory driver for Etherlink II board.
    3  *
    4  *      Created:        Dec. 20, 1996 by G. Falzoni <falzoni@marina.scn.de>
    5  */
    6 
    7 #define EL2_MEMTEST     0       /* Set to 1 for on board memory test */
    8 
    9 #define EL2_GA          0x0400  /* Offset of registers in Gate Array */
   10 
   11 /* EtherLink II card */
   12 
   13 #define EL2_STARTPG     (EL2_GA+0x00)   /* Start page matching DP_PSTARTPG */
   14 #define EL2_STOPPG      (EL2_GA+0x01)   /* Stop page matching DP_PSTOPPG   */
   15 #define EL2_DRQCNT      (EL2_GA+0x02)   /* DMA burst count                 */
   16 #define EL2_IOBASE      (EL2_GA+0x03)   /* I/O base jumpers (bit coded)    */
   17 #define EL2_MEMBASE     (EL2_GA+0x04)   /* Memory base jumpers (bit coded) */
   18 #define EL2_CFGR        (EL2_GA+0x05)   /* Configuration Register  for GA  */
   19 #define EL2_CNTR        (EL2_GA+0x06)   /* Control(write) and status(read) */
   20 #define EL2_STATUS      (EL2_GA+0x07)
   21 #define EL2_IDCFG       (EL2_GA+0x08)   /* Interrupt/DMA configuration reg */
   22 #define EL2_DMAAH       (EL2_GA+0x09)   /* DMA address register (High byte) */
   23 #define EL2_DMAAL       (EL2_GA+0x0A)   /* DMA address register (Low byte) */
   24 #define EL2_VP2         (EL2_GA+0x0B)   /* Vector pointer - set to         */
   25 #define EL2_VP1         (EL2_GA+0x0C)   /* reset address (0xFFFF:0)  */
   26 #define EL2_VP0         (EL2_GA+0x0D)   /* */
   27 #define EL2_FIFOH       (EL2_GA+0x0E)   /* FIFO for progr. I/O (High byte) */
   28 #define EL2_FIFOL       (EL2_GA+0x0F)   /* FIFO for progr. I/O (Low byte)  */
   29 
   30 #define EL2_EA0         0x00    /* Most significant byte of ethernet address */
   31 #define EL2_EA1         0x01
   32 #define EL2_EA2         0x02
   33 #define EL2_EA3         0x03
   34 #define EL2_EA4         0x04
   35 #define EL2_EA5         0x05    /* Least significant byte of ethernet address */
   36 
   37 /* Bits in EL2_CNTR register */
   38 #define ECNTR_RESET     0x01    /* Software Reset */
   39 #define ECNTR_THIN      0x02    /* Onboard transceiver enable */
   40 #define ECNTR_AUI       0x00    /* Onboard transceiver disable */
   41 #define ECNTR_SAPROM    0x04    /* Map the station address prom */
   42 
   43 /* Bits in EL2_CFGR register */
   44 #define ECFGR_NORM      0x49    /* Enable 8k shared memory, no DMA, TC int */
   45 #define ECFGR_IRQOFF    0xC9    /* As above, disable 8390 IRQ */
   46 
   47 /* Shared memory management parameters */
   48 #define EL2_SM_START_PG 0x20    /* First page of TX buffer */
   49 #define EL2_SM_STOP_PG  0x40    /* Last page +1 of RX ring */
   50 
   51 /* Physical addresses where an Etherlink board can be configured */
   52 #define EL2_BASE_0C8000 0x0C8000
   53 #define EL2_BASE_0CC000 0x0CC000
   54 #define EL2_BASE_0D8000 0x0D8000
   55 #define EL2_BASE_0DC000 0x0DC000
   56 
   57 #define inb_el2(dep,reg)        (inb((dep)->de_base_port+(reg)))
   58 #define outb_el2(dep,reg,data)  (outb((dep)->de_base_port+(reg),(data)))
   59 
   60 /** 3c503.h **/
   61 
   62 /*
   63  * $PchId: 3c503.h,v 1.3 2003/09/10 15:34:29 philip Exp $
   64  */

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