The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/drivers/dp8390/dp8390.h

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    1 /*
    2 dp8390.h
    3 
    4 Created:        before Dec 28, 1992 by Philip Homburg
    5 */
    6 
    7 /* National Semiconductor DP8390 Network Interface Controller. */
    8 
    9                                 /* Page 0, for reading ------------- */
   10 #define DP_CR           0x0     /* Read side of Command Register     */
   11 #define DP_CLDA0        0x1     /* Current Local Dma Address 0       */
   12 #define DP_CLDA1        0x2     /* Current Local Dma Address 1       */
   13 #define DP_BNRY         0x3     /* Boundary Pointer                  */
   14 #define DP_TSR          0x4     /* Transmit Status Register          */
   15 #define DP_NCR          0x5     /* Number of Collisions Register     */
   16 #define DP_FIFO         0x6     /* Fifo ??                           */
   17 #define DP_ISR          0x7     /* Interrupt Status Register         */
   18 #define DP_CRDA0        0x8     /* Current Remote Dma Address 0      */
   19 #define DP_CRDA1        0x9     /* Current Remote Dma Address 1      */
   20 #define DP_DUM1         0xA     /* unused                            */
   21 #define DP_DUM2         0xB     /* unused                            */
   22 #define DP_RSR          0xC     /* Receive Status Register           */
   23 #define DP_CNTR0        0xD     /* Tally Counter 0                   */
   24 #define DP_CNTR1        0xE     /* Tally Counter 1                   */
   25 #define DP_CNTR2        0xF     /* Tally Counter 2                   */
   26 
   27                                 /* Page 0, for writing ------------- */
   28 #define DP_CR           0x0     /* Write side of Command Register    */
   29 #define DP_PSTART       0x1     /* Page Start Register               */
   30 #define DP_PSTOP        0x2     /* Page Stop Register                */
   31 #define DP_BNRY         0x3     /* Boundary Pointer                  */
   32 #define DP_TPSR         0x4     /* Transmit Page Start Register      */
   33 #define DP_TBCR0        0x5     /* Transmit Byte Count Register 0    */
   34 #define DP_TBCR1        0x6     /* Transmit Byte Count Register 1    */
   35 #define DP_ISR          0x7     /* Interrupt Status Register         */
   36 #define DP_RSAR0        0x8     /* Remote Start Address Register 0   */
   37 #define DP_RSAR1        0x9     /* Remote Start Address Register 1   */
   38 #define DP_RBCR0        0xA     /* Remote Byte Count Register 0      */
   39 #define DP_RBCR1        0xB     /* Remote Byte Count Register 1      */
   40 #define DP_RCR          0xC     /* Receive Configuration Register    */
   41 #define DP_TCR          0xD     /* Transmit Configuration Register   */
   42 #define DP_DCR          0xE     /* Data Configuration Register       */
   43 #define DP_IMR          0xF     /* Interrupt Mask Register           */
   44 
   45                                 /* Page 1, read/write -------------- */
   46 #define DP_CR           0x0     /* Command Register                  */
   47 #define DP_PAR0         0x1     /* Physical Address Register 0       */
   48 #define DP_PAR1         0x2     /* Physical Address Register 1       */
   49 #define DP_PAR2         0x3     /* Physical Address Register 2       */
   50 #define DP_PAR3         0x4     /* Physical Address Register 3       */
   51 #define DP_PAR4         0x5     /* Physical Address Register 4       */
   52 #define DP_PAR5         0x6     /* Physical Address Register 5       */
   53 #define DP_CURR         0x7     /* Current Page Register             */
   54 #define DP_MAR0         0x8     /* Multicast Address Register 0      */
   55 #define DP_MAR1         0x9     /* Multicast Address Register 1      */
   56 #define DP_MAR2         0xA     /* Multicast Address Register 2      */
   57 #define DP_MAR3         0xB     /* Multicast Address Register 3      */
   58 #define DP_MAR4         0xC     /* Multicast Address Register 4      */
   59 #define DP_MAR5         0xD     /* Multicast Address Register 5      */
   60 #define DP_MAR6         0xE     /* Multicast Address Register 6      */
   61 #define DP_MAR7         0xF     /* Multicast Address Register 7      */
   62 
   63 /* Bits in dp_cr */
   64 #define CR_STP          0x01    /* Stop: software reset              */
   65 #define CR_STA          0x02    /* Start: activate NIC               */
   66 #define CR_TXP          0x04    /* Transmit Packet                   */
   67 #define CR_DMA          0x38    /* Mask for DMA control              */
   68 #define CR_DM_NOP       0x00    /* DMA: No Operation                 */
   69 #define CR_DM_RR        0x08    /* DMA: Remote Read                  */
   70 #define CR_DM_RW        0x10    /* DMA: Remote Write                 */
   71 #define CR_DM_SP        0x18    /* DMA: Send Packet                  */
   72 #define CR_DM_ABORT     0x20    /* DMA: Abort Remote DMA Operation   */
   73 #define CR_PS           0xC0    /* Mask for Page Select              */
   74 #define CR_PS_P0        0x00    /* Register Page 0                   */
   75 #define CR_PS_P1        0x40    /* Register Page 1                   */
   76 #define CR_PS_P2        0x80    /* Register Page 2                   */
   77 #define CR_PS_T1        0xC0    /* Test Mode Register Map            */
   78 
   79 /* Bits in dp_isr */
   80 #define ISR_PRX         0x01    /* Packet Received with no errors    */
   81 #define ISR_PTX         0x02    /* Packet Transmitted with no errors */
   82 #define ISR_RXE         0x04    /* Receive Error                     */
   83 #define ISR_TXE         0x08    /* Transmit Error                    */
   84 #define ISR_OVW         0x10    /* Overwrite Warning                 */
   85 #define ISR_CNT         0x20    /* Counter Overflow                  */
   86 #define ISR_RDC         0x40    /* Remote DMA Complete               */
   87 #define ISR_RST         0x80    /* Reset Status                      */
   88 
   89 /* Bits in dp_imr */
   90 #define IMR_PRXE        0x01    /* Packet Received iEnable           */
   91 #define IMR_PTXE        0x02    /* Packet Transmitted iEnable        */
   92 #define IMR_RXEE        0x04    /* Receive Error iEnable             */
   93 #define IMR_TXEE        0x08    /* Transmit Error iEnable            */
   94 #define IMR_OVWE        0x10    /* Overwrite Warning iEnable         */
   95 #define IMR_CNTE        0x20    /* Counter Overflow iEnable          */
   96 #define IMR_RDCE        0x40    /* DMA Complete iEnable              */
   97 
   98 /* Bits in dp_dcr */
   99 #define DCR_WTS         0x01    /* Word Transfer Select              */
  100 #define DCR_BYTEWIDE    0x00    /* WTS: byte wide transfers          */
  101 #define DCR_WORDWIDE    0x01    /* WTS: word wide transfers          */
  102 #define DCR_BOS         0x02    /* Byte Order Select                 */
  103 #define DCR_LTLENDIAN   0x00    /* BOS: Little Endian                */
  104 #define DCR_BIGENDIAN   0x02    /* BOS: Big Endian                   */
  105 #define DCR_LAS         0x04    /* Long Address Select               */
  106 #define DCR_BMS         0x08    /* Burst Mode Select
  107                                  * Called Loopback Select (LS) in 
  108                                  * later manuals. Should be set.     */
  109 #define DCR_AR          0x10    /* Autoinitialize Remote             */
  110 #define DCR_FTS         0x60    /* Fifo Threshold Select             */
  111 #define DCR_2BYTES      0x00    /* 2 bytes                           */
  112 #define DCR_4BYTES      0x40    /* 4 bytes                           */
  113 #define DCR_8BYTES      0x20    /* 8 bytes                           */
  114 #define DCR_12BYTES     0x60    /* 12 bytes                          */
  115 
  116 /* Bits in dp_tcr */
  117 #define TCR_CRC         0x01    /* Inhibit CRC                       */
  118 #define TCR_ELC         0x06    /* Encoded Loopback Control          */
  119 #define TCR_NORMAL      0x00    /* ELC: Normal Operation             */
  120 #define TCR_INTERNAL    0x02    /* ELC: Internal Loopback            */
  121 #define TCR_0EXTERNAL   0x04    /* ELC: External Loopback LPBK=0     */
  122 #define TCR_1EXTERNAL   0x06    /* ELC: External Loopback LPBK=1     */
  123 #define TCR_ATD         0x08    /* Auto Transmit Disable             */
  124 #define TCR_OFST        0x10    /* Collision Offset Enable (be nice) */
  125 
  126 /* Bits in dp_tsr */
  127 #define TSR_PTX         0x01    /* Packet Transmitted (without error)*/
  128 #define TSR_DFR         0x02    /* Transmit Deferred, reserved in
  129                                  * later manuals.                    */
  130 #define TSR_COL         0x04    /* Transmit Collided                 */
  131 #define TSR_ABT         0x08    /* Transmit Aborted                  */
  132 #define TSR_CRS         0x10    /* Carrier Sense Lost                */
  133 #define TSR_FU          0x20    /* FIFO Underrun                     */
  134 #define TSR_CDH         0x40    /* CD Heartbeat                      */
  135 #define TSR_OWC         0x80    /* Out of Window Collision           */
  136 
  137 /* Bits in tp_rcr */
  138 #define RCR_SEP         0x01    /* Save Errored Packets              */
  139 #define RCR_AR          0x02    /* Accept Runt Packets               */
  140 #define RCR_AB          0x04    /* Accept Broadcast                  */
  141 #define RCR_AM          0x08    /* Accept Multicast                  */
  142 #define RCR_PRO         0x10    /* Physical Promiscuous              */
  143 #define RCR_MON         0x20    /* Monitor Mode                      */
  144 
  145 /* Bits in dp_rsr */
  146 #define RSR_PRX         0x01    /* Packet Received Intact            */
  147 #define RSR_CRC         0x02    /* CRC Error                         */
  148 #define RSR_FAE         0x04    /* Frame Alignment Error             */
  149 #define RSR_FO          0x08    /* FIFO Overrun                      */
  150 #define RSR_MPA         0x10    /* Missed Packet                     */
  151 #define RSR_PHY         0x20    /* Multicast Address Match           */
  152 #define RSR_DIS         0x40    /* Receiver Disabled                 */
  153 #define RSR_DFR         0x80    /* In later manuals: Deferring       */
  154 
  155 typedef struct dp_rcvhdr
  156 {
  157         u8_t dr_status;                 /* Copy of rsr                       */
  158         u8_t dr_next;                   /* Pointer to next packet            */
  159         u8_t dr_rbcl;                   /* Receive Byte Count Low            */
  160         u8_t dr_rbch;                   /* Receive Byte Count High           */
  161 } dp_rcvhdr_t;
  162 
  163 #define DP_PAGESIZE     256
  164 
  165 /* Some macros to simplify accessing the dp8390 */
  166 #define inb_reg0(dep, reg)              (inb(dep->de_dp8390_port+reg))
  167 #define outb_reg0(dep, reg, data)       (outb(dep->de_dp8390_port+reg, data))
  168 #define inb_reg1(dep, reg)              (inb(dep->de_dp8390_port+reg))
  169 #define outb_reg1(dep, reg, data)       (outb(dep->de_dp8390_port+reg, data))
  170 
  171 /* Software interface to the dp8390 driver */
  172 
  173 struct dpeth;
  174 struct iovec_dat;
  175 _PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep)             );
  176 _PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep)             );
  177 _PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep,
  178                         struct iovec_dat *iovp, vir_bytes offset,
  179                         int nic_addr, vir_bytes count)                  );
  180 _PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep,
  181                         int nic_addr, struct iovec_dat *iovp,
  182                         vir_bytes offset, vir_bytes count)              );
  183 #if 0
  184 _PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep,
  185                         int page, struct dp_rcvhdr *h, u16_t *eth_type) );
  186 #endif
  187 _PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep,
  188                 int page, size_t offset, size_t size, void *dst)        );
  189 
  190 /* iovectors are handled IOVEC_NR entries at a time. */
  191 #define IOVEC_NR        16
  192 
  193 typedef int irq_hook_t;
  194 
  195 typedef struct iovec_dat
  196 {
  197   iovec_t iod_iovec[IOVEC_NR];
  198   int iod_iovec_s;
  199   int iod_proc_nr;
  200   vir_bytes iod_iovec_addr;
  201 } iovec_dat_t;
  202 
  203 #define SENDQ_NR        2       /* Maximum size of the send queue */
  204 #define SENDQ_PAGES     6       /* 6 * DP_PAGESIZE >= 1514 bytes */
  205 
  206 typedef struct dpeth
  207 {
  208         /* The de_base_port field is the starting point of the probe.
  209          * The conf routine also fills de_linmem and de_irq. If the probe
  210          * routine knows the irq and/or memory address because they are
  211          * hardwired in the board, the probe should modify these fields.
  212          * Futhermore, the probe routine should also fill in de_initf and
  213          * de_stopf fields with the appropriate function pointers and set
  214          * de_prog_IO iff programmed I/O is to be used.
  215          */
  216         port_t de_base_port;
  217         phys_bytes de_linmem;
  218         int de_irq;
  219         int de_int_pending;
  220         irq_hook_t de_hook;
  221         dp_initf_t de_initf; 
  222         dp_stopf_t de_stopf; 
  223         int de_prog_IO;
  224         char de_name[sizeof("dp8390#n")];
  225 
  226         /* The initf function fills the following fields. Only cards that do
  227          * programmed I/O fill in the de_pata_port field.
  228          * In addition, the init routine has to fill in the sendq data
  229          * structures.
  230          */
  231         ether_addr_t de_address;
  232         port_t de_dp8390_port;
  233         port_t de_data_port;
  234         int de_16bit;
  235         int de_ramsize;
  236         int de_offset_page;
  237         int de_startpage;
  238         int de_stoppage;
  239 
  240 #if ENABLE_PCI
  241         /* PCI config */
  242         char de_pci;                    /* TRUE iff PCI device */
  243         u8_t de_pcibus; 
  244         u8_t de_pcidev; 
  245         u8_t de_pcifunc;        
  246 #endif
  247 
  248         /* Do it yourself send queue */
  249         struct sendq
  250         {
  251                 int sq_filled;          /* this buffer contains a packet */
  252                 int sq_size;            /* with this size */
  253                 int sq_sendpage;        /* starting page of the buffer */
  254         } de_sendq[SENDQ_NR];
  255         int de_sendq_nr;
  256         int de_sendq_head;              /* Enqueue at the head */
  257         int de_sendq_tail;              /* Dequeue at the tail */
  258 
  259         /* Fields for internal use by the dp8390 driver. */
  260         int de_flags;
  261         int de_mode;
  262         eth_stat_t de_stat;
  263         iovec_dat_t de_read_iovec;
  264         iovec_dat_t de_write_iovec;
  265         iovec_dat_t de_tmp_iovec;
  266         vir_bytes de_read_s;
  267         int de_client;
  268         message de_sendmsg;
  269         dp_user2nicf_t de_user2nicf; 
  270         dp_nic2userf_t de_nic2userf; 
  271         dp_getblock_t de_getblockf; 
  272 } dpeth_t;
  273 
  274 #define DEI_DEFAULT     0x8000
  275 
  276 #define DEF_EMPTY       0x000
  277 #define DEF_PACK_SEND   0x001
  278 #define DEF_PACK_RECV   0x002
  279 #define DEF_SEND_AVAIL  0x004
  280 #define DEF_READING     0x010
  281 #define DEF_PROMISC     0x040
  282 #define DEF_MULTI       0x080
  283 #define DEF_BROAD       0x100
  284 #define DEF_ENABLED     0x200
  285 #define DEF_STOPPED     0x400
  286 
  287 #define DEM_DISABLED    0x0
  288 #define DEM_SINK        0x1
  289 #define DEM_ENABLED     0x2
  290 
  291 #if !__minix_vmd
  292 #define debug           0       /* Standard Minix lacks debug variable */
  293 #endif
  294 
  295 /*
  296  * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $
  297  */

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