The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/drivers/dpeth/3c501.h

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    1 /*
    2 **  File:       3c501.h         Jan. 14, 1997
    3 **
    4 **  Author:     Giovanni Falzoni <gfalzoni@inwind.it>
    5 **
    6 **  Interface description for 3Com Etherlink boards
    7 **
    8 **  $Log: 3c501.h,v $
    9 **  Revision 1.1  2005/06/29 10:16:46  beng
   10 **  Import of dpeth 3c501/3c509b/.. ethernet driver by
   11 **  Giovanni Falzoni <fgalzoni@inwind.it>.
   12 **
   13 **  Revision 2.0  2005/06/26 16:16:46  lsodgf0
   14 **  Initial revision for Minix 3.0.6
   15 **
   16 **  $Id: 3c501.h,v 1.1 2005/06/29 10:16:46 beng Exp $
   17 */
   18 
   19 /* The various board command registers                                   */
   20 #define EL1_ADDRESS     0x00    /* Board station address, 6 bytes        */
   21 #define EL1_RECV        0x06    /* Board Receive Config/Status Reg.      */
   22 #define EL1_XMIT        0x07    /* Board Transmit Config/Status Reg.     */
   23 #define EL1_XMITPTR     0x08    /* Transmit buffer pointer (word access) */
   24 #define EL1_RECVPTR     0x0A    /* Receive buffer pointer (word access)  */
   25 #define EL1_SAPROM      0x0C    /* Window on Station Addr prom           */
   26 #define EL1_CSR         0x0E    /* Board Command/Status Register         */
   27 #define EL1_DATAPORT    0x0F    /* Window on packet buffer (Data Port)   */
   28 
   29 /* Bits in EL1_RECV, interrupt enable on write, status when read         */
   30 #define ERSR_NONE       0x00    /* Match mode in bits 5-6 (wo)           */
   31 #define ERSR_ALL        0x40    /* Promiscuous receive (wo)              */
   32 #define ERSR_BROAD      0x80    /* Station address plus broadcast (wo)   */
   33 #define ERSR_MULTI      0x80    /* Station address plus multicast 0xC0   */
   34 #define ERSR_STALE      0x80    /* Receive status previously read (ro)   */
   35 #define ERSR_GOOD       0x20    /* Well formed packets only (rw)         */
   36 #define ERSR_ANY        0x10    /* Any packet, even with errors (rw)     */
   37 #define ERSR_SHORT      0x08    /* Short frame (rw)                      */
   38 #define ERSR_DRIBBLE    0x04    /* Dribble error (rw)                    */
   39 #define ERSR_FCS        0x02    /* CRC error (rw)                        */
   40 #define ERSR_OVER       0x01    /* Data overflow (rw)                    */
   41 
   42 #define ERSR_RERROR     (ERSR_SHORT|ERSR_DRIBBLE|ERSR_FCS|ERSR_OVER)
   43 #define ERSR_RMASK      (ERSR_GOOD|ERSR_RERROR)/*(ERSR_GOOD|ERSR_ANY|ERSR_RERROR)*/
   44 
   45 /* Bits in EL1_XMIT, interrupt enable on write, status when read         */
   46 #define EXSR_IDLE       0x08    /* Transmit idle (send completed)        */
   47 #define EXSR_16JAM      0x04    /* Packet sending got 16 collisions      */
   48 #define EXSR_JAM        0x02    /* Packet sending got a collision        */
   49 #define EXSR_UNDER      0x01    /* Data underflow in sending             */
   50 
   51 /* Bits in EL1_CSR (Configuration Status Register)                       */
   52 #define ECSR_RESET      0x80    /* Reset the controller (wo)             */
   53 #define ECSR_XMTBSY     0x80    /* Transmitter busy (ro)                 */
   54 #define ECSR_RIDE       0x01    /* Request interrupt/DMA enable (rw)     */
   55 #define ECSR_DMA        0x20    /* DMA request (rw)                      */
   56 #define ECSR_EDMA       0x10    /* DMA done (ro)                         */
   57 #define ECSR_CRC        0x02    /* Causes CRC error on transmit (wo)     */
   58 #define ECSR_RCVBSY     0x01    /* Receive in progress (ro)              */
   59 #define ECSR_LOOP       (3<<2)  /* 2 bit field in bits 2,3, loopback     */
   60 #define ECSR_RECV       (2<<2)  /* Gives buffer to receiver (rw)         */
   61 #define ECSR_XMIT       (1<<2)  /* Gives buffer to transmit (rw)         */
   62 #define ECSR_SYS        (0<<2)  /* Gives buffer to processor (wo)        */
   63 
   64 #define EL1_BFRSIZ      2048    /* Number of bytes in board buffer       */
   65 
   66 #define inb_el1(dep,reg) (inb(dep->de_base_port+(reg)))
   67 #define inw_el1(dep,reg) (inw(dep->de_base_port+(reg)))
   68 #define outb_el1(dep,reg,data) (outb(dep->de_base_port+(reg),data))
   69 #define outw_el1(dep,reg,data) (outw(dep->de_base_port+(reg),data))
   70 
   71 /** 3c501.h **/

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