Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/drivers/rtl8139/rtl8139.h
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1 /* 2 ibm/rtl8139.h 3 4 Created: Aug 2003 by Philip Homburg <philip@cs.vu.nl> 5 */ 6 7 #define RL_IDR 0x00 /* Ethernet address 8 * Note: RL_9346CR_EEM_CONFIG mode is 9 * required the change the ethernet 10 * address. 11 * Note: 4-byte write access only. 12 */ 13 #define RL_N_TX 4 /* Number of transmit buffers */ 14 #define RL_TSD0 0x010 /* Transmit Status of Descriptor 0 */ 15 #define RL_TSD_CRS 0x80000000 /* Carrier Sense Lost */ 16 #define RL_TSD_TABT 0x40000000 /* Transmit Abort */ 17 #define RL_TSD_OWC 0x20000000 /* Out of Window Collision */ 18 #define RL_TSD_CDH 0x10000000 /* CD Heart Beat */ 19 #define RL_TSD_NCC_M 0x0F000000 /* Number of Collision Count */ 20 #define RL_TSD_RES 0x00C00000 /* Reserved */ 21 #define RL_TSD_ERTXTH_M 0x003F0000 /* Early Tx Threshold */ 22 #define RL_TSD_ERTXTH_S 16 /* shift */ 23 #define RL_TSD_ERTXTH_8 0x00000000 /* 8 bytes */ 24 #define RL_TSD_TOK 0x00008000 /* Transmit OK */ 25 #define RL_TSD_TUN 0x00004000 /* Transmit FIFO Underrun */ 26 #define RL_TSD_OWN 0x00002000 /* Controller (does not) Own Buf. */ 27 #define RL_TSD_SIZE 0x00001FFF /* Descriptor Size */ 28 #define RL_TSAD0 0x20 /* Transmit Start Address of Descriptor 0 */ 29 #define RL_RBSTART 0x30 /* Receive Buffer Start Address */ 30 #define RL_CR 0x37 /* Command Register */ 31 #define RL_CR_RES0 0xE0 /* Reserved */ 32 #define RL_CR_RST 0x10 /* Reset */ 33 #define RL_CR_RE 0x08 /* Receiver Enable */ 34 #define RL_CR_TE 0x04 /* Transmitter Enable * 35 * Note: start with transmit buffer 36 * 0 after RL_CR_TE has been reset. 37 */ 38 #define RL_CR_RES1 0x02 /* Reserved */ 39 #define RL_CR_BUFE 0x01 /* Receive Buffer Empty */ 40 #define RL_CAPR 0x38 /* Current Address of Packet Read */ 41 #define RL_CAPR_DATA_OFF 0x10 /* Packet Starts at Offset */ 42 #define RL_CBR 0x3A /* Current Buffer Address */ 43 #define RL_IMR 0x3C /* Interrupt Mask Register */ 44 #define RL_IMR_SERR 0x8000 /* System Error */ 45 #define RL_IMR_TIMEOUT 0x4000 /* Time Out */ 46 #define RL_IMR_LENCHG 0x2000 /* Cable Length Change */ 47 #define RL_IMR_RES 0x1F80 /* Reserved */ 48 #define RL_IMR_FOVW 0x0040 /* Rx FIFO Overflow */ 49 #define RL_IMR_PUN 0x0020 /* Packet Underrun / Link Change */ 50 #define RL_IMR_RXOVW 0x0010 /* Rx Buffer Overflow */ 51 #define RL_IMR_TER 0x0008 /* Transmit Error */ 52 #define RL_IMR_TOK 0x0004 /* Transmit OK */ 53 #define RL_IMR_RER 0x0002 /* Receive Error */ 54 #define RL_IMR_ROK 0x0001 /* Receive OK */ 55 #define RL_ISR 0x3E /* Interrupt Status Register */ 56 #define RL_ISR_SERR 0x8000 /* System Error */ 57 #define RL_ISR_TIMEOUT 0x4000 /* Time Out */ 58 #define RL_ISR_LENCHG 0x2000 /* Cable Length Change */ 59 #define RL_ISR_RES 0x1F80 /* Reserved */ 60 #define RL_ISR_FOVW 0x0040 /* Rx FIFO Overflow */ 61 #define RL_ISR_PUN 0x0020 /* Packet Underrun / Link Change */ 62 #define RL_ISR_RXOVW 0x0010 /* Rx Buffer Overflow */ 63 #define RL_ISR_TER 0x0008 /* Transmit Error */ 64 #define RL_ISR_TOK 0x0004 /* Transmit OK */ 65 #define RL_ISR_RER 0x0002 /* Receive Error */ 66 #define RL_ISR_ROK 0x0001 /* Receive OK */ 67 #define RL_TCR 0x40 /* Transmit Configuration Register 68 * Note: RL_CR_TE has to be set to 69 * set/change RL_TCR. 70 */ 71 #define RL_TCR_RES0 0x80000000 /* Reserved */ 72 #define RL_TCR_HWVER_AM 0x7C000000 /* Hardware Version ID A */ 73 #define RL_TCR_IFG_M 0x03000000 /* Interframe Gap Time */ 74 #define RL_TCR_IFG_STD 0x03000000 /* IEEE 802.3 std */ 75 #if 0 76 #undef RL_TCR_IFG_STD 77 #define RL_TCR_IFG_STD 0x00000000 78 #endif 79 #define RL_TCR_HWVER_BM 0x00C00000 /* Hardware Version ID B */ 80 #define RL_TCR_HWVER_RTL8139 0x60000000 /* RTL8139 */ 81 #define RL_TCR_HWVER_RTL8139A 0x70000000 /* RTL8139A */ 82 #define RL_TCR_HWVER_RTL8139AG 0x74000000 /* RTL8139A-G */ 83 #define RL_TCR_HWVER_RTL8139B 0x78000000 /* RTL8139B */ 84 #define RL_TCR_HWVER_RTL8130 0x78000000 /* RTL8130 (dup) */ 85 #define RL_TCR_HWVER_RTL8139C 0x74000000 /* RTL8139C (dup) */ 86 #define RL_TCR_HWVER_RTL8100 0x78800000 /* RTL8100 */ 87 #define RL_TCR_HWVER_RTL8100B 0x74400000 /* RTL8100B / 88 RTL8139D */ 89 #define RL_TCR_HWVER_RTL8139CP 0x74800000 /* RTL8139C+ */ 90 #define RL_TCR_HWVER_RTL8101 0x74C00000 /* RTL8101 */ 91 #define RL_TCR_RES1 0x00380000 /* Reserved */ 92 #define RL_TCR_LBK_M 0x00060000 /* Loopback Test */ 93 #define RL_TCR_LBK_NORMAL 0x00000000 /* Normal */ 94 #define RL_TCR_LBK_LOOKBOCK 0x00060000 /* Loopback Mode */ 95 #define RL_TCR_CRC 0x00010000 /* (Do not) Append CRC */ 96 #define RL_TCR_RES2 0x0000F800 /* Reserved */ 97 #define RL_TCR_MXDMA_M 0x00000700 /* Max DMA Burst Size Tx */ 98 #define RL_TCR_MXDMA_16 0x00000000 /* 16 bytes */ 99 #define RL_TCR_MXDMA_32 0x00000100 /* 32 bytes */ 100 #define RL_TCR_MXDMA_64 0x00000200 /* 64 bytes */ 101 #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */ 102 #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */ 103 #define RL_TCR_MXDMA_256 0x00000400 /* 256 bytes */ 104 #define RL_TCR_MXDMA_512 0x00000500 /* 512 bytes */ 105 #define RL_TCR_MXDMA_1024 0x00000600 /* 1024 bytes */ 106 #define RL_TCR_MXDMA_2048 0x00000700 /* 2048 bytes */ 107 #define RL_TCR_TXRR_M 0x000000F0 /* Tx Retry Count */ 108 #define RL_TCR_RES3 0x0000000E /* Reserved */ 109 #define RL_TCR_CLRABT 0x00000001 /* Clear Abort */ 110 #define RL_RCR 0x44 /* Receive Configuration Register 111 * Note: RL_CR_RE has to be set to 112 * set/change RL_RCR. 113 */ 114 #define RL_RCR_RES0 0xF0000000 /& Reserved */ 115 #define RL_RCR_ERTH_M 0x0F000000 /* Early Rx Threshold */ 116 #define RL_RCR_ERTH_0 0x00000000 /* No threshold */ 117 #define RL_RCR_ERTH_1 0x01000000 /* 1/16 */ 118 #define RL_RCR_ERTH_2 0x02000000 /* 2/16 */ 119 #define RL_RCR_ERTH_3 0x03000000 /* 3/16 */ 120 #define RL_RCR_ERTH_4 0x04000000 /* 4/16 */ 121 #define RL_RCR_ERTH_5 0x05000000 /* 5/16 */ 122 #define RL_RCR_ERTH_6 0x06000000 /* 6/16 */ 123 #define RL_RCR_ERTH_7 0x07000000 /* 7/16 */ 124 #define RL_RCR_ERTH_8 0x08000000 /* 8/16 */ 125 #define RL_RCR_ERTH_9 0x09000000 /* 9/16 */ 126 #define RL_RCR_ERTH_10 0x0A000000 /* 10/16 */ 127 #define RL_RCR_ERTH_11 0x0B000000 /* 11/16 */ 128 #define RL_RCR_ERTH_12 0x0C000000 /* 12/16 */ 129 #define RL_RCR_ERTH_13 0x0D000000 /* 13/16 */ 130 #define RL_RCR_ERTH_14 0x0E000000 /* 14/16 */ 131 #define RL_RCR_ERTH_15 0x0F000000 /* 15/16 */ 132 #define RL_RCR_RES1 0x00FC0000 /* Reserved */ 133 #define RL_RCR_MULERINT 0x00020000 /* Multiple Early Int Select */ 134 #define RL_RCR_RER8 0x00010000 /* Receive small error packet */ 135 #define RL_RCR_RXFTH_M 0x0000E000 /* Rx FIFO Threshold */ 136 #define RL_RCR_RXFTH_16 0x00000000 /* 16 bytes */ 137 #define RL_RCR_RXFTH_32 0x00002000 /* 32 bytes */ 138 #define RL_RCR_RXFTH_64 0x00004000 /* 64 bytes */ 139 #define RL_RCR_RXFTH_128 0x00006000 /* 128 bytes */ 140 #define RL_RCR_RXFTH_256 0x00008000 /* 256 bytes */ 141 #define RL_RCR_RXFTH_512 0x0000A000 /* 512 bytes */ 142 #define RL_RCR_RXFTH_1024 0x0000C000 /* 1024 bytes */ 143 #define RL_RCR_RXFTH_UNLIM 0x0000E000 /* unlimited */ 144 #define RL_RCR_RBLEM_M 0x00001800 /* Rx Buffer Length */ 145 #define RL_RCR_RBLEN_8K 0x00000000 /* 8KB + 16 bytes */ 146 #define RL_RCR_RBLEN_8K_SIZE (8*1024) 147 #define RL_RCR_RBLEN_16K 0x00000800 /* 16KB + 16 bytes */ 148 #define RL_RCR_RBLEN_16K_SIZE (16*1024) 149 #define RL_RCR_RBLEN_32K 0x00001000 /* 32KB + 16 bytes */ 150 #define RL_RCR_RBLEN_32K_SIZE (32*1024) 151 #define RL_RCR_RBLEN_64K 0x00001800 /* 64KB + 16 bytes */ 152 #define RL_RCR_RBLEN_64K_SIZE (64*1024) 153 /* Note: the documentation for the RTL8139C(L) or 154 * for the RTL8139D(L) claims that the buffer should 155 * be 16 bytes larger. Multiples of 8KB are the 156 * correct values. 157 */ 158 #define RL_RCR_MXDMA_M 0x00000700 /* Rx DMA burst size */ 159 #define RL_RCR_MXDMA_16 0x00000000 /* 16 bytes */ 160 #define RL_RCR_MXDMA_32 0x00000100 /* 32 bytes */ 161 #define RL_RCR_MXDMA_64 0x00000200 /* 64 bytes */ 162 #define RL_RCR_MXDMA_128 0x00000300 /* 128 bytes */ 163 #define RL_RCR_MXDMA_256 0x00000400 /* 256 bytes */ 164 #define RL_RCR_MXDMA_512 0x00000500 /* 512 bytes */ 165 #define RL_RCR_MXDMA_1024 0x00000600 /* 1024 bytes */ 166 #define RL_RCR_MXDMA_UNLIM 0x00000700 /* unlimited */ 167 #define RL_RCR_WRAP 0x00000080 /* (Do not) Wrap on receive */ 168 #define RL_RCR_RES2 0x00000040 /* EEPROM type? */ 169 #define RL_RCR_AER 0x00000020 /* Accept Error Packets */ 170 #define RL_RCR_AR 0x00000010 /* Accept Runt Packets */ 171 #define RL_RCR_AB 0x00000008 /* Accept Broadcast Packets */ 172 #define RL_RCR_AM 0x00000004 /* Accept Multicast Packets */ 173 #define RL_RCR_APM 0x00000002 /* Accept Physical Match Packets */ 174 #define RL_RCR_AAP 0x00000001 /* Accept All Packets */ 175 #define RL_MPC 0x4c /* Missed Packet Counter */ 176 #define RL_9346CR 0x50 /* 93C46 Command Register */ 177 #define RL_9346CR_EEM_M 0xC0 /* Operating Mode */ 178 #define RL_9346CR_EEM_NORMAL 0x00 /* Normal Mode */ 179 #define RL_9346CR_EEM_AUTOLOAD 0x40 /* Load from 93C46 */ 180 #define RL_9346CR_EEM_PROG 0x80 /* 93C46 Programming */ 181 #define RL_9346CR_EEM_CONFIG 0xC0 /* Config Write Enable */ 182 #define RL_9346CR_RES 0x30 /* Reserved */ 183 #define RL_9346CR_EECS 0x08 /* EECS Pin */ 184 #define RL_9346CR_EESK 0x04 /* EESK Pin */ 185 #define RL_9346CR_EEDI 0x02 /* EEDI Pin */ 186 #define RL_9346CR_EEDO 0x01 /* EEDO Pin */ 187 #define RL_CONFIG0 0x51 /* Configuration Register 0 */ 188 #define RL_CONFIG1 0x52 /* Configuration Register 1 */ 189 #define RL_MSR 0x58 /* Media Status Register */ 190 #define RL_MSR_TXFCE 0x80 /* Tx Flow Control Enable */ 191 #define RL_MSR_RXFCE 0x40 /* Rx Flow Control Enable */ 192 #define RL_MSR_RES 0x20 /* Reserved */ 193 #define RL_MSR_AUXSTAT 0x10 /* Aux. Power Present */ 194 #define RL_MSR_SPEED_10 0x08 /* In 10 Mbps mode */ 195 #define RL_MSR_LINKB 0x04 /* link Failed */ 196 #define RL_MSR_TXPF 0x02 /* Sent Pause Packet */ 197 #define RL_MSR_RXPF 0x01 /* Received Pause Packet */ 198 #define RL_CONFIG3 0x59 /* Configuration Register 3 */ 199 #define RL_CONFIG4 0x5A /* Configuration Register 4 */ 200 /* 0x5B */ /* Reserved */ 201 #define RL_REVID 0x5E /* PCI Revision ID */ 202 /* 0x5F */ /* Reserved */ 203 #define RL_TSAD 0x60 /* Transmit Status of All Descriptors */ 204 #define RL_TSAD_TOK3 0x8000 /* TOK bit of Descriptor 3 */ 205 #define RL_TSAD_TOK2 0x4000 /* TOK bit of Descriptor 2 */ 206 #define RL_TSAD_TOK1 0x2000 /* TOK bit of Descriptor 1 */ 207 #define RL_TSAD_TOK0 0x1000 /* TOK bit of Descriptor 0 */ 208 #define RL_TSAD_TUN3 0x0800 /* TUN bit of Descriptor 3 */ 209 #define RL_TSAD_TUN2 0x0400 /* TUN bit of Descriptor 2 */ 210 #define RL_TSAD_TUN1 0x0200 /* TUN bit of Descriptor 1 */ 211 #define RL_TSAD_TUN0 0x0100 /* TUN bit of Descriptor 0 */ 212 #define RL_TSAD_TABT3 0x0080 /* TABT bit of Descriptor 3 */ 213 #define RL_TSAD_TABT2 0x0040 /* TABT bit of Descriptor 2 */ 214 #define RL_TSAD_TABT1 0x0020 /* TABT bit of Descriptor 1 */ 215 #define RL_TSAD_TABT0 0x0010 /* TABT bit of Descriptor 0 */ 216 #define RL_TSAD_OWN3 0x0008 /* OWN bit of Descriptor 3 */ 217 #define RL_TSAD_OWN2 0x0004 /* OWN bit of Descriptor 2 */ 218 #define RL_TSAD_OWN1 0x0002 /* OWN bit of Descriptor 1 */ 219 #define RL_TSAD_OWN0 0x0001 /* OWN bit of Descriptor 0 */ 220 #define RL_BMCR 0x62 /* Basic Mode Control Register (MII_CTRL) */ 221 #define RL_BMSR 0x64 /* Basic Mode Status Register (MII_STATUS) */ 222 #define RL_ANAR 0x66 /* Auto-Neg Advertisement Register (MII_ANA) */ 223 #define RL_ANLPAR 0x68 /* Auto-Neg Link Partner Register (MII_ANLPA) */ 224 #define RL_ANER 0x6a /* Auto-Neg Expansion Register (MII_ANE) */ 225 #define RL_NWAYTR 0x70 /* N-way Test Register */ 226 #define RL_CSCR 0x74 /* CS Configuration Register */ 227 #define RL_CONFIG5 0xD8 /* Configuration Register 5 */ 228 229 /* Status word in receive buffer */ 230 #define RL_RXS_LEN_M 0xFFFF0000 /* Length Field, Excl. Status word */ 231 #define RL_RXS_LEN_S 16 /* Shift For Length */ 232 #define RL_RXS_MAR 0x00008000 /* Multicast Address Received */ 233 #define RL_RXS_PAR 0x00004000 /* Physical Address Matched */ 234 #define RL_RXS_BAR 0x00002000 /* Broadcast Address Received */ 235 #define RL_RXS_RES_M 0x00001FC0 /* Reserved */ 236 #define RL_RXS_ISE 0x00000020 /* Invalid Symbol Error */ 237 #define RL_RXS_RUNT 0x00000010 /* Runt Packet Received */ 238 #define RL_RXS_LONG 0x00000008 /* Long (>4KB) Packet */ 239 #define RL_RXS_CRC 0x00000004 /* CRC Error */ 240 #define RL_RXS_FAE 0x00000002 /* Frame Alignment Error */ 241 #define RL_RXS_ROK 0x00000001 /* Receive OK */ 242 243 /* Registers in the Machine Independent Interface (MII) to the PHY. 244 * IEEE 802.3 (2000 Edition) Clause 22. 245 */ 246 #define MII_CTRL 0x0 /* Control Register (basic) */ 247 #define MII_CTRL_RST 0x8000 /* Reset PHY */ 248 #define MII_CTRL_LB 0x4000 /* Enable Loopback Mode */ 249 #define MII_CTRL_SP_LSB 0x2000 /* Speed Selection (LSB) */ 250 #define MII_CTRL_ANE 0x1000 /* Auto Negotiation Enable */ 251 #define MII_CTRL_PD 0x0800 /* Power Down */ 252 #define MII_CTRL_ISO 0x0400 /* Isolate */ 253 #define MII_CTRL_RAN 0x0200 /* Restart Auto-Negotiation Process */ 254 #define MII_CTRL_DM 0x0100 /* Full Duplex */ 255 #define MII_CTRL_CT 0x0080 /* Enable COL Signal Test */ 256 #define MII_CTRL_SP_MSB 0x0040 /* Speed Selection (MSB) */ 257 #define MII_CTRL_SP_10 0x0000 /* 10 Mb/s */ 258 #define MII_CTRL_SP_100 0x2000 /* 100 Mb/s */ 259 #define MII_CTRL_SP_1000 0x0040 /* 1000 Mb/s */ 260 #define MII_CTRL_SP_RES 0x2040 /* Reserved */ 261 #define MII_CTRL_RES 0x003F /* Reserved */ 262 #define MII_STATUS 0x1 /* Status Register (basic) */ 263 #define MII_STATUS_100T4 0x8000 /* 100Base-T4 support */ 264 #define MII_STATUS_100XFD 0x4000 /* 100Base-X FD support */ 265 #define MII_STATUS_100XHD 0x2000 /* 100Base-X HD support */ 266 #define MII_STATUS_10FD 0x1000 /* 10 Mb/s FD support */ 267 #define MII_STATUS_10HD 0x0800 /* 10 Mb/s HD support */ 268 #define MII_STATUS_100T2FD 0x0400 /* 100Base-T2 FD support */ 269 #define MII_STATUS_100T2HD 0x0200 /* 100Base-T2 HD support */ 270 #define MII_STATUS_EXT_STAT 0x0100 /* Supports MII_EXT_STATUS */ 271 #define MII_STATUS_RES 0x0080 /* Reserved */ 272 #define MII_STATUS_MFPS 0x0040 /* MF Preamble Suppression */ 273 #define MII_STATUS_ANC 0x0020 /* Auto-Negotiation Completed */ 274 #define MII_STATUS_RF 0x0010 /* Remote Fault Detected */ 275 #define MII_STATUS_ANA 0x0008 /* Auto-Negotiation Ability */ 276 #define MII_STATUS_LS 0x0004 /* Link Up */ 277 #define MII_STATUS_JD 0x0002 /* Jabber Condition Detected */ 278 #define MII_STATUS_EC 0x0001 /* Ext Register Capabilities */ 279 #define MII_PHYID_H 0x2 /* PHY ID (high) */ 280 #define MII_PHYID_L 0x3 /* PHY ID (low) */ 281 #define MII_ANA 0x4 /* Auto-Negotiation Advertisement */ 282 #define MII_ANA_NP 0x8000 /* Next PAge */ 283 #define MII_ANA_RES 0x4000 /* Reserved */ 284 #define MII_ANA_RF 0x2000 /* Remote Fault */ 285 #define MII_ANA_TAF_M 0x1FE0 /* Technology Ability Field */ 286 #define MII_ANA_TAF_S 5 /* Shift */ 287 #define MII_ANA_TAF_RES 0x1000 /* Reserved */ 288 #define MII_ANA_PAUSE_ASYM 0x0800 /* Asym. Pause */ 289 #define MII_ANA_PAUSE_SYM 0x0400 /* Sym. Pause */ 290 #define MII_ANA_100T4 0x0200 /* 100Base-T4 */ 291 #define MII_ANA_100TXFD 0x0100 /* 100Base-TX FD */ 292 #define MII_ANA_100TXHD 0x0080 /* 100Base-TX HD */ 293 #define MII_ANA_10TFD 0x0040 /* 10Base-T FD */ 294 #define MII_ANA_10THD 0x0020 /* 10Base-T HD */ 295 #define MII_ANA_SEL_M 0x001F /* Selector Field */ 296 #define MII_ANA_SEL_802_3 0x0001 /* 802.3 */ 297 #define MII_ANLPA 0x5 /* Auto-Neg Link Partner Ability Register */ 298 #define MII_ANLPA_NP 0x8000 /* Next Page */ 299 #define MII_ANLPA_ACK 0x4000 /* Acknowledge */ 300 #define MII_ANLPA_RF 0x2000 /* Remote Fault */ 301 #define MII_ANLPA_TAF_M 0x1FC0 /* Technology Ability Field */ 302 #define MII_ANLPA_SEL_M 0x001F /* Selector Field */ 303 #define MII_ANE 0x6 /* Auto-Negotiation Expansion */ 304 #define MII_ANE_RES 0xFFE0 /* Reserved */ 305 #define MII_ANE_PDF 0x0010 /* Parallel Detection Fault */ 306 #define MII_ANE_LPNPA 0x0008 /* Link Partner is Next Page Able */ 307 #define MII_ANE_NPA 0x0002 /* Local Device is Next Page Able */ 308 #define MII_ANE_PR 0x0002 /* New Page has been received */ 309 #define MII_ANE_LPANA 0x0001 /* Link Partner is Auto-Neg.able */ 310 #define MII_ANNPT 0x7 /* Auto-Negotiation Next Page Transmit */ 311 #define MII_ANLPRNP 0x8 /* Auto-Neg Link Partner Received Next Page */ 312 #define MII_MS_CTRL 0x9 /* MASTER-SLAVE Control Register */ 313 #define MII_MS_STATUS 0xA /* MASTER-SLAVE Status Register */ 314 /* 0xB ... 0xE */ /* Reserved */ 315 #define MII_EXT_STATUS 0xF /* Extended Status */ 316 #define MII_ESTAT_1000XFD 0x8000 /* 1000Base-X Full Duplex */ 317 #define MII_ESTAT_1000XHD 0x4000 /* 1000Base-X Half Duplex */ 318 #define MII_ESTAT_1000TFD 0x2000 /* 1000Base-T Full Duplex */ 319 #define MII_ESTAT_1000THD 0x1000 /* 1000Base-T Half Duplex */ 320 #define MII_ESTAT_RES 0x0FFF /* Reserved */ 321 /* 0x10 ... 0x1F */ /* Vendor Specific */ 322 323 #if 0 324 34-35 R ERBCR Early Receive (Rx) Byte Count Register 325 36 R ERSR Early Rx Status Register 326 7-4 reserved 327 3 R ERGood Early Rx Good packet 328 2 R ERBad Early Rx Bad packet 329 1 R EROVW Early Rx OverWrite 330 0 R EROK Early Rx OK 331 51 R/W CONFIG0 Configuration Register 0 332 7 R SCR Scrambler Mode 333 6 R PCS PCS Mode 334 5 R T10 10 Mbps Mode 335 4-3 R PL[1-0] Select 10 Mbps medium type 336 2-0 R BS[2-0] Select Boot ROM size 337 52 R/W CONFIG1 Configuration Register 1 338 7-6 R/W LEDS[1-0] LED PIN 339 5 R/W DVRLOAD Driver Load 340 4 R/W LWACT LWAKE active mode 341 3 R MEMMAP Memory Mapping 342 2 R IOMAP I/O Mapping 343 1 R/W VPD Set to enable Vital Product Data 344 0 R/W PMEn Power Management Enable 345 59 R/W CONFIG3 Configuration Register 3 346 7 R GNTSel Gnt Select 347 6 R/W PARM_En Parameter Enable 348 5 R/W Magic Magic Packet 349 4 R/W LinkUp Link Up 350 3 reserved 351 2 R CLKRUN_En CLKRUN Enable 352 1 reserved 353 0 R FBtBEn Fast Back to Back Enable 354 5a R/W CONFIG4 Configuration Register 4 355 7 R/W RxFIFOAutoClr Auto Clear the Rx FIFO on overflow 356 6 R/W AnaOff Analog Power Off 357 5 R/W LongWF Long Wake-up Frame 358 4 R/W LWPME LANWAKE vs PMEB 359 3 reserved 360 2 R/W LWPTN LWAKE pattern 361 1 reserved 362 0 R/W PBWakeup Pre-Boot Wakeup 363 5c-5d R/W MULINT Multiple Interrupt Select 364 15-12 reserved 365 11-0 R/W MISR[11-0] Multiple Interrupt Select 366 68-69 R ANLPAR Auto-Negotiation Link Partnet Register 367 15 R NP Next Page bit 368 14 R ACK acknowledge received from link partner 369 13 R/W RF received remote fault detection capability 370 12-11 reserved 371 10 R Pause Flow control is supported 372 9 R T4 100Base-T4 is supported 373 8 R/W TXFD 100Base-TX full duplex is supported 374 7 R/W TX 100Base-TX is supported 375 6 R/W 10FD 10Base-T full duplex is supported 376 5 R/W 10 10Base-T is supported 377 4-0 R/W Selector Binary encoded selector 378 6a-6b R ANER Auto-Negotiation Expansion Register 379 15-5 reserved 380 4 R MLF Multiple link fault occured 381 3 R LP_NP_ABLE Link partner supports Next Page 382 2 R NP_ABLE Local node is able to send add. Next Pages 383 1 R PAGE_RX Link Code Word Page received 384 0 R LP_NW_ABLE Link partner supports NWay auto-negotiation 385 70-71 R/W NWAYTR N-way Test Register 386 15-8 reserved 387 7 R/W NWLPBK NWay loopback mode 388 6-4 reserved 389 3 R ENNWLE LED0 pin indicates linkpulse 390 2 R FLAGABD Auto-neg experienced ability detect state 391 1 R FLAGPDF Auto-neg exp. par. detection fault state 392 0 R FLAGLSC Auto-neg experienced link status check state 393 74-75 R/W CSCR CS Configuration Register 394 15 W Testfun Auto-neg speeds up internal timer 395 14-10 reserved 396 9 R/W LD Active low TPI link disable signal 397 8 R/W HEARTBEAT HEART BEAT enable 398 7 R/W JBEN Enable jabber function 399 6 R/W F_LINK_100 Force 100 Mbps 400 5 R/W F_Conect Bypass disconnect function 401 4 reserved 402 3 R Con_status Connected link detected 403 2 R/W Con_status_En Configures LED1 to indicate conn. stat. 404 1 reserved 405 0 R/W PASS_SCR Bypass scramble 406 76-77 reserved 407 78-7b R/W PHY1_PARM PHY parameter 1 408 7c-7f R/W TW_PARM Twister parameter 409 80 R/W PHY2_PARM PHY parameter 2 410 81-83 reserved 411 84-8b R/W CRC[0-7] Power Management CRC reg.[0-7] for frame[0-7] 412 8c-cb R/W Wakeup[0-7] Power Management wakeup frame[0-7] (64 bit) 413 cc-d3 R/W LSBCRC[0-7] LSB of the mask byte of makeup frame[0-7] 414 d4-d7 reserved 415 d8 R/W Config5 Configuration register 5 416 7 reserved 417 6 R/W BWF Broadcast Wakeup Frame 418 5 R/W MWF Multicast Wakeup Frame 419 4 R/W UWF Unicast Wakeup Frame 420 3 R/W FifoAddrPtr FIFO Address Pointer 421 2 R/W LDPS Link Down Power Saving mode 422 1 R/W LANWake LANWake Signal 423 0 R/W PME_STS PME_Status bit 424 d9-ff reserved 425 #endif 426 427 /* 428 * $PchId: rtl8139.h,v 1.1 2003/09/05 10:58:50 philip Exp $ 429 */
Cache object: bcf440751b9f37a186197909c4221230
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