The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dts/arm/db78100.dts

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Copyright (c) 2010 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Semihalf under sponsorship from
    6  * the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * Marvell DB-78100 Device Tree Source.
   30  *
   31  * $FreeBSD: stable/12/sys/dts/arm/db78100.dts 333031 2018-04-26 19:00:48Z mw $
   32  */
   33 
   34 /dts-v1/;
   35 
   36 / {
   37         model = "mrvl,DB-78100";
   38         compatible = "DB-78100-BP", "DB-78100-BP-A";
   39         #address-cells = <1>;
   40         #size-cells = <1>;
   41 
   42         aliases {
   43                 ethernet0 = &enet0;
   44                 serial0 = &serial0;
   45                 serial1 = &serial1;
   46                 mpp = &MPP;
   47         };
   48 
   49         cpus {
   50                 #address-cells = <1>;
   51                 #size-cells = <0>;
   52 
   53                 cpu@0 {
   54                         device_type = "cpu";
   55                         compatible = "ARM,88FR571";
   56                         reg = <0x0>;
   57                         d-cache-line-size = <32>;       // 32 bytes
   58                         i-cache-line-size = <32>;       // 32 bytes
   59                         d-cache-size = <0x4000>;        // L1, 16K
   60                         i-cache-size = <0x4000>;        // L1, 16K
   61                         timebase-frequency = <0>;
   62                         bus-frequency = <0>;
   63                         clock-frequency = <0>;
   64                 };
   65         };
   66 
   67         memory {
   68                 device_type = "memory";
   69                 reg = <0x0 0x20000000>;         // 512M at 0x0
   70         };
   71 
   72         localbus@0 {
   73                 #address-cells = <2>;
   74                 #size-cells = <1>;
   75                 compatible = "mrvl,lbc";
   76                 bank-count = <5>;
   77 
   78                 /* This reflects CPU decode windows setup. */
   79                 ranges = <0x0 0x2f 0xf9300000 0x00100000
   80                           0x1 0x3e 0xf9400000 0x00100000
   81                           0x2 0x3d 0xf9500000 0x02000000
   82                           0x3 0x3b 0xfb500000 0x00100000>;
   83 
   84                 nor@0,0 {
   85                         #address-cells = <1>;
   86                         #size-cells = <1>;
   87                         compatible = "cfi-flash";
   88                         reg = <0x0 0x0 0x00100000>;
   89                 };
   90 
   91                 led@1,0 {
   92                         #address-cells = <1>;
   93                         #size-cells = <1>;
   94                         compatible = "led";
   95                         reg = <0x1 0x0 0x00100000>;
   96                 };
   97 
   98                 nor@2,0 {
   99                         #address-cells = <1>;
  100                         #size-cells = <1>;
  101                         compatible = "cfi-flash";
  102                         reg = <0x2 0x0 0x02000000>;
  103                 };
  104 
  105                 nand@3,0 {
  106                         #address-cells = <1>;
  107                         #size-cells = <1>;
  108                         compatible = "mrvl,nfc";
  109                         reg = <0x3 0x0 0x00100000>;
  110                 };
  111         };
  112 
  113         soc78100@f1000000 {
  114                 #address-cells = <1>;
  115                 #size-cells = <1>;
  116                 compatible = "simple-bus";
  117                 ranges = <0x0 0xf1000000 0x00100000>;
  118                 bus-frequency = <0>;
  119 
  120                 PIC: pic@20200 {
  121                         interrupt-controller;
  122                         #address-cells = <0>;
  123                         #interrupt-cells = <1>;
  124                         reg = <0x20200 0x3c>;
  125                         compatible = "mrvl,pic";
  126                 };
  127 
  128                 timer@20300 {
  129                         compatible = "mrvl,timer";
  130                         reg = <0x20300 0x30>;
  131                         interrupts = <8>;
  132                         interrupt-parent = <&PIC>;
  133                         mrvl,has-wdt;
  134                 };
  135 
  136                 MPP: mpp@10000 {
  137                         #pin-cells = <2>;
  138                         compatible = "mrvl,mpp";
  139                         reg = <0x10000 0x34>;
  140                         pin-count = <50>;
  141                         pin-map = <
  142                                 0  2            /* MPP[0]:  GE1_TXCLK */
  143                                 1  2            /* MPP[1]:  GE1_TXCTL */
  144                                 2  2            /* MPP[2]:  GE1_RXCTL */
  145                                 3  2            /* MPP[3]:  GE1_RXCLK */
  146                                 4  2            /* MPP[4]:  GE1_TXD[0] */
  147                                 5  2            /* MPP[5]:  GE1_TXD[1] */
  148                                 6  2            /* MPP[6]:  GE1_TXD[2] */
  149                                 7  2            /* MPP[7]:  GE1_TXD[3] */
  150                                 8  2            /* MPP[8]:  GE1_RXD[0] */
  151                                 9  2            /* MPP[9]:  GE1_RXD[1] */
  152                                 10 2            /* MPP[10]: GE1_RXD[2] */
  153                                 11 2            /* MPP[11]: GE1_RXD[3] */
  154                                 13 3            /* MPP[13]: SYSRST_OUTn */
  155                                 14 3            /* MPP[14]: SATA1_ACTn */
  156                                 15 3            /* MPP[15]: SATA0_ACTn */
  157                                 16 4            /* MPP[16]: UA2_TXD */
  158                                 17 4            /* MPP[17]: UA2_RXD */
  159                                 18 3            /* MPP[18]: <UNKNOWN> */
  160                                 19 3            /* MPP[19]: <UNKNOWN> */
  161                                 20 3            /* MPP[20]: <UNKNOWN> */
  162                                 21 3            /* MPP[21]: <UNKNOWN> */
  163                                 22 4            /* MPP[22]: UA3_TXD */
  164                                 23 4 >;         /* MPP[21]: UA3_RXD */
  165                 };
  166 
  167                 GPIO: gpio@10100 {
  168                         #gpio-cells = <2>;
  169                         compatible = "mrvl,gpio";
  170                         reg = <0x10100 0x20>;
  171                         gpio-controller;
  172                         interrupts = <56 57 58 59>;
  173                         interrupt-parent = <&PIC>;
  174                 };
  175 
  176                 rtc@10300 {
  177                         compatible = "mrvl,rtc";
  178                         reg = <0x10300 0x08>;
  179                 };
  180 
  181                 twsi@11000 {
  182                         #address-cells = <1>;
  183                         #size-cells = <0>;
  184                         compatible = "mrvl,twsi";
  185                         reg = <0x11000 0x20>;
  186                         interrupts = <2>;
  187                         interrupt-parent = <&PIC>;
  188                 };
  189 
  190                 twsi@11100 {
  191                         #address-cells = <1>;
  192                         #size-cells = <0>;
  193                         compatible = "mrvl,twsi";
  194                         reg = <0x11100 0x20>;
  195                         interrupts = <3>;
  196                         interrupt-parent = <&PIC>;
  197                 };
  198 
  199                 enet0: ethernet@72000 {
  200                         #address-cells = <1>;
  201                         #size-cells = <1>;
  202                         model = "V2";
  203                         compatible = "mrvl,ge";
  204                         reg = <0x72000 0x2000>;
  205                         ranges = <0x0 0x72000 0x2000>;
  206                         local-mac-address = [ 00 00 00 00 00 00 ];
  207                         interrupts = <41 42 43 40 70>;
  208                         interrupt-parent = <&PIC>;
  209                         phy-handle = <&phy0>;
  210 
  211                         mdio@0 {
  212                                 #address-cells = <1>;
  213                                 #size-cells = <0>;
  214                                 compatible = "mrvl,mdio";
  215 
  216                                 phy0: ethernet-phy@0 {
  217                                         reg = <0x8>;
  218                                 };
  219                                 phy1: ethernet-phy@1 {
  220                                         reg = <0x9>;
  221                                 };
  222                         };
  223                 };
  224 
  225                 enet1: ethernet@76000 {
  226                         #address-cells = <1>;
  227                         #size-cells = <1>;
  228                         model = "V2";
  229                         compatible = "mrvl,ge";
  230                         reg = <0x76000 0x2000>;
  231                         ranges = <0x0 0x76000 0x2000>;
  232                         local-mac-address = [ 00 00 00 00 00 00 ];
  233                         interrupts = <45 46 47 44 70>;
  234                         interrupt-parent = <&PIC>;
  235                         phy-handle = <&phy1>;
  236                 };
  237 
  238                 serial0: serial@12000 {
  239                         compatible = "ns16550";
  240                         reg = <0x12000 0x20>;
  241                         reg-shift = <2>;
  242                         clock-frequency = <0>;
  243                         interrupts = <12>;
  244                         interrupt-parent = <&PIC>;
  245                 };
  246 
  247                 serial1: serial@12100 {
  248                         compatible = "ns16550";
  249                         reg = <0x12100 0x20>;
  250                         reg-shift = <2>;
  251                         clock-frequency = <0>;
  252                         interrupts = <13>;
  253                         interrupt-parent = <&PIC>;
  254                 };
  255 
  256                 usb@50000 {
  257                         compatible = "mrvl,usb-ehci", "usb-ehci";
  258                         reg = <0x50000 0x1000>;
  259                         interrupts = <72 16>;
  260                         interrupt-parent = <&PIC>;
  261                 };
  262 
  263                 usb@51000 {
  264                         compatible = "mrvl,usb-ehci", "usb-ehci";
  265                         reg = <0x51000 0x1000>;
  266                         interrupts = <72 17>;
  267                         interrupt-parent = <&PIC>;
  268                 };
  269 
  270                 usb@52000 {
  271                         compatible = "mrvl,usb-ehci", "usb-ehci";
  272                         reg = <0x52000 0x1000>;
  273                         interrupts = <72 18>;
  274                         interrupt-parent = <&PIC>;
  275                 };
  276 
  277                 xor@60000 {
  278                         compatible = "mrvl,xor";
  279                         reg = <0x60000 0x1000>;
  280                         interrupts = <22 23>;
  281                         interrupt-parent = <&PIC>;
  282                 };
  283 
  284                 crypto@90000 {
  285                         compatible = "mrvl,cesa";
  286                         reg = <0x90000 0x1000   /* tdma base reg chan 0 */
  287                                0x9D000 0x1000>; /* cesa base reg chan 0 */
  288                         interrupts = <19>;
  289                         interrupt-parent = <&PIC>;
  290                 };
  291 
  292                 sata@a0000 {
  293                         compatible = "mrvl,sata";
  294                         reg = <0xa0000 0x6000>;
  295                         interrupts = <26>;
  296                         interrupt-parent = <&PIC>;
  297                 };
  298         };
  299 
  300         pci0: pcie@f1040000 {
  301                 compatible = "mrvl,pcie";
  302                 device_type = "pci";
  303                 #interrupt-cells = <1>;
  304                 #size-cells = <2>;
  305                 #address-cells = <3>;
  306                 reg = <0xf1040000 0x2000>;
  307                 bus-range = <0 255>;
  308                 ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
  309                           0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
  310                 clock-frequency = <33333333>;
  311                 interrupt-parent = <&PIC>;
  312                 interrupts = <68>;
  313                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  314                 interrupt-map = <
  315                         /* IDSEL 0x1 */
  316                         0x0800 0x0 0x0 0x1 &PIC 0x20
  317                         0x0800 0x0 0x0 0x2 &PIC 0x21
  318                         0x0800 0x0 0x0 0x3 &PIC 0x22
  319                         0x0800 0x0 0x0 0x4 &PIC 0x23
  320                         >;
  321         };
  322 
  323         sram@fd000000 {
  324                 compatible = "mrvl,cesa-sram";
  325                 reg = <0xfd000000 0x00100000>;
  326         };
  327 
  328         chosen {
  329                 stdin = "serial0";
  330                 stdout = "serial0";
  331         };
  332 };

Cache object: 525ad240b8583066224ebfb73699e4d4


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.