The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dts/arm/db88f5281.dts

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    1 /*
    2  * Copyright (c) 2010 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Semihalf under sponsorship from
    6  * the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * Marvell DB-88F5281 Device Tree Source.
   30  *
   31  * $FreeBSD: stable/12/sys/dts/arm/db88f5281.dts 333031 2018-04-26 19:00:48Z mw $
   32  */
   33 
   34 /dts-v1/;
   35 
   36 / {
   37         model = "mrvl,DB-88F5281";
   38         compatible = "DB-88F5281-BP", "DB-88F5281-BP-A";
   39         #address-cells = <1>;
   40         #size-cells = <1>;
   41 
   42         aliases {
   43                 ethernet0 = &enet0;
   44                 serial0 = &serial0;
   45                 serial1 = &serial1;
   46                 mpp = &MPP;
   47         };
   48 
   49         cpus {
   50                 #address-cells = <1>;
   51                 #size-cells = <0>;
   52 
   53                 cpu@0 {
   54                         device_type = "cpu";
   55                         compatible = "ARM,88FR531";
   56                         reg = <0x0>;
   57                         d-cache-line-size = <32>;       // 32 bytes
   58                         i-cache-line-size = <32>;       // 32 bytes
   59                         d-cache-size = <0x8000>;        // L1, 32K
   60                         i-cache-size = <0x8000>;        // L1, 32K
   61                         timebase-frequency = <0>;
   62                         bus-frequency = <0>;
   63                         clock-frequency = <0>;
   64                 };
   65         };
   66 
   67         memory {
   68                 device_type = "memory";
   69                 reg = <0x0 0x08000000>;         // 128M at 0x0
   70         };
   71 
   72         localbus@f1000000 {
   73                 #address-cells = <2>;
   74                 #size-cells = <1>;
   75                 compatible = "mrvl,lbc";
   76 
   77                 /* This reflects CPU decode windows setup. */
   78                 ranges = <0x0 0x0f 0xf9300000 0x00100000
   79                           0x1 0x1e 0xfa000000 0x00100000
   80                           0x2 0x1d 0xfa100000 0x02000000>;
   81 
   82                 nor@0,0 {
   83                         #address-cells = <1>;
   84                         #size-cells = <1>;
   85                         compatible = "cfi-flash";
   86                         reg = <0x0 0x0 0x00100000>;
   87                         bank-width = <2>;
   88                         device-width = <1>;
   89                 };
   90 
   91                 led@1,0 {
   92                         #address-cells = <1>;
   93                         #size-cells = <1>;
   94                         compatible = "led";
   95                         reg = <0x1 0x0 0x00100000>;
   96                 };
   97 
   98                 nor@2,0 {
   99                         #address-cells = <1>;
  100                         #size-cells = <1>;
  101                         compatible = "cfi-flash";
  102                         reg = <0x2 0x0 0x02000000>;
  103                         bank-width = <2>;
  104                         device-width = <1>;
  105                 };
  106         };
  107 
  108         soc88f5281@f1000000 {
  109                 #address-cells = <1>;
  110                 #size-cells = <1>;
  111                 compatible = "simple-bus";
  112                 ranges = <0x0 0xf1000000 0x00100000>;
  113                 bus-frequency = <0>;
  114 
  115                 PIC: pic@20200 {
  116                         interrupt-controller;
  117                         #address-cells = <0>;
  118                         #interrupt-cells = <1>;
  119                         reg = <0x20200 0x3c>;
  120                         compatible = "mrvl,pic";
  121                 };
  122 
  123                 timer@20300 {
  124                         compatible = "mrvl,timer";
  125                         reg = <0x20300 0x30>;
  126                         interrupts = <0>;
  127                         interrupt-parent = <&PIC>;
  128                         mrvl,has-wdt;
  129                 };
  130 
  131                 MPP: mpp@10000 {
  132                         #pin-cells = <2>;
  133                         compatible = "mrvl,mpp";
  134                         reg = <0x10000 0x54>;
  135                         pin-count = <20>;
  136                         pin-map = <
  137                                 0  3            /* MPP[0]:  GPIO[0] */
  138                                 2  2            /* MPP[2]:  PCI_REQn[3] */
  139                                 3  2            /* MPP[3]:  PCI_GNTn[3] */
  140                                 4  2            /* MPP[4]:  PCI_REQn[4] */
  141                                 5  2            /* MPP[5]:  PCI_GNTn[4] */
  142                                 6  3            /* MPP[6]:  <UNKNOWN> */
  143                                 7  3            /* MPP[7]:  <UNKNOWN> */
  144                                 8  3            /* MPP[8]:  <UNKNOWN> */
  145                                 9  3            /* MPP[9]:  <UNKNOWN> */
  146                                 14 4            /* MPP[14]: NAND Flash REn[2] */
  147                                 15 4            /* MPP[15]: NAND Flash WEn[2] */
  148                                 16 0            /* MPP[16]: UA1_RXD */
  149                                 17 0            /* MPP[17]: UA1_TXD */
  150                                 18 0            /* MPP[18]: UA1_CTS */
  151                                 19 0 >;         /* MPP[19]: UA1_RTS */
  152                 };
  153 
  154                 GPIO: gpio@10100 {
  155                         #gpio-cells = <2>;
  156                         compatible = "mrvl,gpio";
  157                         reg = <0x10100 0x20>;
  158                         gpio-controller;
  159                         interrupts = <6 7 8 9>;
  160                         interrupt-parent = <&PIC>;
  161                 };
  162 
  163                 twsi@11000 {
  164                         #address-cells = <1>;
  165                         #size-cells = <0>;
  166                         compatible = "mrvl,twsi";
  167                         reg = <0x11000 0x20>;
  168                         interrupts = <43>;
  169                         interrupt-parent = <&PIC>;
  170                 };
  171 
  172                 enet0: ethernet@72000 {
  173                         #address-cells = <1>;
  174                         #size-cells = <1>;
  175                         model = "V1";
  176                         compatible = "mrvl,ge";
  177                         reg = <0x72000 0x2000>;
  178                         ranges = <0x0 0x72000 0x2000>;
  179                         local-mac-address = [ 00 00 00 00 00 00 ];
  180                         interrupts = <18 19 20 21 22>;
  181                         interrupt-parent = <&PIC>;
  182                         phy-handle = <&phy0>;
  183 
  184                         mdio@0 {
  185                                 #address-cells = <1>;
  186                                 #size-cells = <0>;
  187                                 compatible = "mrvl,mdio";
  188 
  189                                 phy0: ethernet-phy@0 {
  190                                         reg = <0x8>;
  191                                 };
  192                         };
  193                 };
  194 
  195                 serial0: serial@12000 {
  196                         compatible = "ns16550";
  197                         reg = <0x12000 0x20>;
  198                         reg-shift = <2>;
  199                         clock-frequency = <0>;
  200                         interrupts = <3>;
  201                         interrupt-parent = <&PIC>;
  202                 };
  203 
  204                 serial1: serial@12100 {
  205                         compatible = "ns16550";
  206                         reg = <0x12100 0x20>;
  207                         reg-shift = <2>;
  208                         clock-frequency = <0>;
  209                         interrupts = <4>;
  210                         interrupt-parent = <&PIC>;
  211                 };
  212 
  213                 usb@50000 {
  214                         compatible = "mrvl,usb-ehci", "usb-ehci";
  215                         reg = <0x50000 0x1000>;
  216                         interrupts = <17 16>;
  217                         interrupt-parent = <&PIC>;
  218                 };
  219 
  220                 idma@60000 {
  221                         compatible = "mrvl,idma";
  222                         reg = <0x60000 0x1000>;
  223                         interrupts = <24 25 26 27 23>;
  224                         interrupt-parent = <&PIC>;
  225                 };
  226         };
  227 };

Cache object: 43511bc274fc1f6bfc2ee7d7dba43dd6


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