Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dts/arm/imx51x.dtsi
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1 /* 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under sponsorship from 5 * the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Freescale i.MX515 Device Tree Source. 29 * 30 * $FreeBSD$ 31 */ 32 33 / { 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 aliases { 38 soc = &SOC; 39 }; 40 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "ARM,MCIMX515"; 49 reg = <0x0>; 50 d-cache-line-size = <32>; 51 i-cache-line-size = <32>; 52 d-cache-size = <0x8000>; 53 i-cache-size = <0x8000>; 54 /* TODO: describe L2 cache also */ 55 timebase-frequency = <0>; 56 bus-frequency = <0>; 57 clock-frequency = <0>; 58 }; 59 }; 60 61 localbus@e0000000 { 62 compatible = "simple-bus"; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 66 /* This reflects CPU decode windows setup. */ 67 ranges; 68 69 tzic: tz-interrupt-controller@e0000000 { 70 compatible = "fsl,imx51-tzic", "fsl,tzic"; 71 interrupt-controller; 72 #interrupt-cells = <1>; 73 reg = <0xe0000000 0x00004000>; 74 }; 75 /* 76 * 60000000 60000FFF 4K Debug ROM 77 * 60001000 60001FFF 4K ETB 78 * 60002000 60002FFF 4K ETM 79 * 60003000 60003FFF 4K TPIU 80 * 60004000 60004FFF 4K CTI0 81 * 60005000 60005FFF 4K CTI1 82 * 60006000 60006FFF 4K CTI2 83 * 60007000 60007FFF 4K CTI3 84 * 60008000 60008FFF 4K Cortex Debug Unit 85 * 86 * E0000000 E0003FFF 0x4000 TZIC 87 */ 88 }; 89 90 SOC: soc@70000000 { 91 compatible = "simple-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 interrupt-parent = <&tzic>; 95 ranges = <0x70000000 0x70000000 0x14000000>; 96 97 aips@70000000 { /* AIPS1 */ 98 compatible = "fsl,aips-bus", "simple-bus"; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 interrupt-parent = <&tzic>; 102 ranges; 103 104 /* Required by many devices, so better to stay first */ 105 /* 73FD4000 0x4000 CCM */ 106 clock@73fd4000 { 107 compatible = "fsl,imx51-ccm"; 108 /* 83F80000 0x4000 DPLLIP1 */ 109 /* 83F84000 0x4000 DPLLIP2 */ 110 /* 83F88000 0x4000 DPLLIP3 */ 111 reg = <0x73fd4000 0x4000 112 0x83F80000 0x4000 113 0x83F84000 0x4000 114 0x83F88000 0x4000>; 115 interrupt-parent = <&tzic>; 116 interrupts = <71 72>; 117 status = "disabled"; 118 }; 119 120 /* 121 * GPIO modules moved up - to have it attached for 122 * drivers which rely on GPIO 123 */ 124 /* 73F84000 0x4000 GPIO1 */ 125 gpio1: gpio@73f84000 { 126 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 127 reg = <0x73f84000 0x4000>; 128 interrupt-parent = <&tzic>; 129 interrupts = <50 51 42 43 44 45 46 47 48 49>; 130 /* TODO: use <> also */ 131 gpio-controller; 132 #gpio-cells = <2>; 133 interrupt-controller; 134 #interrupt-cells = <1>; 135 }; 136 137 /* 73F88000 0x4000 GPIO2 */ 138 gpio2: gpio@73f88000 { 139 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 140 reg = <0x73f88000 0x4000>; 141 interrupt-parent = <&tzic>; 142 interrupts = <52 53>; 143 gpio-controller; 144 #gpio-cells = <2>; 145 interrupt-controller; 146 #interrupt-cells = <1>; 147 }; 148 149 /* 73F8C000 0x4000 GPIO3 */ 150 gpio3: gpio@73f8c000 { 151 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 152 reg = <0x73f8c000 0x4000>; 153 interrupt-parent = <&tzic>; 154 interrupts = <54 55>; 155 gpio-controller; 156 #gpio-cells = <2>; 157 interrupt-controller; 158 #interrupt-cells = <1>; 159 }; 160 161 /* 73F90000 0x4000 GPIO4 */ 162 gpio4: gpio@73f90000 { 163 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 164 reg = <0x73f90000 0x4000>; 165 interrupt-parent = <&tzic>; 166 interrupts = <56 57>; 167 gpio-controller; 168 #gpio-cells = <2>; 169 interrupt-controller; 170 #interrupt-cells = <1>; 171 }; 172 173 spba@70000000 { 174 compatible = "fsl,spba-bus", "simple-bus"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 interrupt-parent = <&tzic>; 178 ranges; 179 180 /* 70004000 0x4000 ESDHC 1 */ 181 esdhc@70004000 { 182 compatible = "fsl,imx51-esdhc"; 183 reg = <0x70004000 0x4000>; 184 interrupt-parent = <&tzic>; interrupts = <1>; 185 status = "disabled"; 186 }; 187 188 /* 70008000 0x4000 ESDHC 2 */ 189 esdhc@70008000 { 190 compatible = "fsl,imx51-esdhc"; 191 reg = <0x70008000 0x4000>; 192 interrupt-parent = <&tzic>; interrupts = <2>; 193 status = "disabled"; 194 }; 195 196 /* 7000C000 0x4000 UART 3 */ 197 uart3: serial@7000c000 { 198 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 199 reg = <0x7000c000 0x4000>; 200 interrupt-parent = <&tzic>; interrupts = <33>; 201 status = "disabled"; 202 }; 203 204 /* 70010000 0x4000 eCSPI1 */ 205 ecspi@70010000 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "fsl,imx51-ecspi"; 209 reg = <0x70010000 0x4000>; 210 interrupt-parent = <&tzic>; interrupts = <36>; 211 status = "disabled"; 212 }; 213 214 /* 70014000 0x4000 SSI2 irq30 */ 215 SSI2: ssi@70014000 { 216 compatible = "fsl,imx51-ssi"; 217 reg = <0x70014000 0x4000>; 218 interrupt-parent = <&tzic>; interrupts = <30>; 219 status = "disabled"; 220 }; 221 222 /* 70020000 0x4000 ESDHC 3 */ 223 esdhc@70020000 { 224 compatible = "fsl,imx51-esdhc"; 225 reg = <0x70020000 0x4000>; 226 interrupt-parent = <&tzic>; interrupts = <3>; 227 status = "disabled"; 228 }; 229 230 /* 70024000 0x4000 ESDHC 4 */ 231 esdhc@70024000 { 232 compatible = "fsl,imx51-esdhc"; 233 reg = <0x70024000 0x4000>; 234 interrupt-parent = <&tzic>; interrupts = <4>; 235 status = "disabled"; 236 }; 237 238 /* 70028000 0x4000 SPDIF */ 239 /* 91 SPDIF */ 240 241 /* 70030000 0x4000 PATA (PORT UDMA) irq70 */ 242 243 /* 70034000 0x4000 SLM */ 244 /* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */ 245 /* 7003C000 0x4000 SPBA */ 246 }; 247 248 usbphy0: usbphy@0 { 249 compatible = "usb-nop-xceiv"; 250 status = "okay"; 251 }; 252 253 usbotg: usb@73f80000 { 254 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 255 reg = <0x73f80000 0x0200>; 256 interrupts = <18>; 257 fsl,usbmisc = <&usbmisc 0>; 258 fsl,usbphy = <&usbphy0>; 259 status = "disabled"; 260 }; 261 262 usbh1: usb@73f80200 { 263 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 264 reg = <0x73f80200 0x0200>; 265 interrupts = <14>; 266 fsl,usbmisc = <&usbmisc 1>; 267 status = "disabled"; 268 }; 269 270 usbh2: usb@73f80400 { 271 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 272 reg = <0x73f80400 0x0200>; 273 interrupts = <16>; 274 fsl,usbmisc = <&usbmisc 2>; 275 status = "disabled"; 276 }; 277 278 usbh3: usb@73f80600 { 279 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 280 reg = <0x73f80600 0x0200>; 281 interrupts = <17>; 282 fsl,usbmisc = <&usbmisc 3>; 283 status = "disabled"; 284 }; 285 286 usbmisc: usbmisc@73f80800 { 287 #index-cells = <1>; 288 compatible = "fsl,imx51-usbmisc"; 289 reg = <0x73f80800 0x200>; 290 }; 291 292 /* 73F98000 0x4000 WDOG1 */ 293 wdog@73f98000 { 294 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 295 reg = <0x73f98000 0x4000>; 296 interrupt-parent = <&tzic>; interrupts = <58>; 297 status = "disabled"; 298 }; 299 300 /* 73F9C000 0x4000 WDOG2 (TZ) */ 301 wdog@73f9c000 { 302 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 303 reg = <0x73f9c000 0x4000>; 304 interrupt-parent = <&tzic>; interrupts = <59>; 305 status = "disabled"; 306 }; 307 308 /* 73F94000 0x4000 KPP */ 309 keyboard@73f94000 { 310 compatible = "fsl,imx51-kpp"; 311 reg = <0x73f94000 0x4000>; 312 interrupt-parent = <&tzic>; interrupts = <60>; 313 status = "disabled"; 314 }; 315 316 /* 73FA0000 0x4000 GPT */ 317 timer@73fa0000 { 318 compatible = "fsl,imx51-gpt"; 319 reg = <0x73fa0000 0x4000>; 320 interrupt-parent = <&tzic>; interrupts = <39>; 321 status = "disabled"; 322 }; 323 324 /* 73FA4000 0x4000 SRTC */ 325 326 rtc@73fa4000 { 327 compatible = "fsl,imx51-srtc"; 328 reg = <0x73fa4000 0x4000>; 329 interrupt-parent = <&tzic>; interrupts = <24 25>; 330 status = "disabled"; 331 }; 332 333 /* 73FA8000 0x4000 IOMUXC */ 334 iomux@73fa8000 { 335 compatible = "fsl,imx51-iomux"; 336 reg = <0x73fa8000 0x4000>; 337 interrupt-parent = <&tzic>; interrupts = <7>; 338 }; 339 340 /* 73FAC000 0x4000 EPIT1 */ 341 epit1: timer@73fac000 { 342 compatible = "fsl,imx51-epit"; 343 reg = <0x73fac000 0x4000>; 344 interrupt-parent = <&tzic>; interrupts = <40>; 345 status = "disabled"; 346 }; 347 348 /* 73FB0000 0x4000 EPIT2 */ 349 epit2: timer@73fb0000 { 350 compatible = "fsl,imx51-epit"; 351 reg = <0x73fb0000 0x4000>; 352 interrupt-parent = <&tzic>; interrupts = <41>; 353 status = "disabled"; 354 }; 355 356 /* 73FB4000 0x4000 PWM1 */ 357 pwm@73fb4000 { 358 compatible = "fsl,imx51-pwm"; 359 reg = <0x73fb4000 0x4000>; 360 interrupt-parent = <&tzic>; interrupts = <61>; 361 status = "disabled"; 362 }; 363 364 /* 73FB8000 0x4000 PWM2 */ 365 pwm@73fb8000 { 366 compatible = "fsl,imx51-pwm"; 367 reg = <0x73fb8000 0x4000>; 368 interrupt-parent = <&tzic>; interrupts = <94>; 369 status = "disabled"; 370 }; 371 372 /* 73FBC000 0x4000 UART 1 */ 373 uart1: serial@73fbc000 { 374 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 375 reg = <0x73fbc000 0x4000>; 376 interrupt-parent = <&tzic>; interrupts = <31>; 377 status = "disabled"; 378 }; 379 380 /* 73FC0000 0x4000 UART 2 */ 381 uart2: serial@73fc0000 { 382 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 383 reg = <0x73fc0000 0x4000>; 384 interrupt-parent = <&tzic>; interrupts = <32>; 385 status = "disabled"; 386 }; 387 388 /* 73FC4000 0x4000 USBOH3 */ 389 /* NOTYET 390 usb@73fc4000 { 391 compatible = "fsl,imx51-otg"; 392 reg = <0x73fc4000 0x4000>; 393 interrupt-parent = <&tzic>; interrupts = <>; 394 status = "disabled"; 395 }; 396 */ 397 /* 73FD0000 0x4000 SRC */ 398 reset@73fd0000 { 399 compatible = "fsl,imx51-src"; 400 reg = <0x73fd0000 0x4000>; 401 interrupt-parent = <&tzic>; interrupts = <75>; 402 status = "disabled"; 403 }; 404 /* 73FD8000 0x4000 GPC */ 405 power@73fd8000 { 406 compatible = "fsl,imx51-gpc"; 407 reg = <0x73fd8000 0x4000>; 408 interrupt-parent = <&tzic>; interrupts = <73 74>; 409 status = "disabled"; 410 }; 411 412 }; 413 414 aips@80000000 { /* AIPS2 */ 415 compatible = "fsl,aips-bus", "simple-bus"; 416 #address-cells = <1>; 417 #size-cells = <1>; 418 interrupt-parent = <&tzic>; 419 ranges; 420 421 /* 83F94000 0x4000 AHBMAX */ 422 /* 83F98000 0x4000 IIM */ 423 /* 424 * 69 IIM Interrupt request to the processor. 425 * Indicates to the processor that program or 426 * explicit. 427 */ 428 /* 83F9C000 0x4000 CSU */ 429 /* 430 * 27 CSU Interrupt Request 1. Indicates to the 431 * processor that one or more alarm inputs were. 432 */ 433 434 /* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ 435 /* irq76 Neon Monitor Interrupt */ 436 /* irq77 Performance Unit Interrupt */ 437 /* irq78 CTI IRQ */ 438 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ 439 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ 440 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ 441 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ 442 443 /* 83FA4000 0x4000 OWIRE irq88 */ 444 /* 83FA8000 0x4000 FIRI irq93 */ 445 /* 83FAC000 0x4000 eCSPI2 */ 446 ecspi@83fac000 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "fsl,imx51-ecspi"; 450 reg = <0x83fac000 0x4000>; 451 interrupt-parent = <&tzic>; interrupts = <37>; 452 status = "disabled"; 453 }; 454 455 /* 83FB0000 0x4000 SDMA */ 456 sdma@83fb0000 { 457 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 458 reg = <0x83fb0000 0x4000>; 459 interrupt-parent = <&tzic>; interrupts = <6>; 460 }; 461 462 /* 83FB4000 0x4000 SCC */ 463 /* 21 SCC Security Monitor High Priority Interrupt. */ 464 /* 22 SCC Secure (TrustZone) Interrupt. */ 465 /* 23 SCC Regular (Non-Secure) Interrupt. */ 466 467 /* 83FB8000 0x4000 ROMCP */ 468 /* 83FBC000 0x4000 RTIC */ 469 /* 470 * 26 RTIC RTIC (Trust Zone) Interrupt Request. 471 * Indicates that the RTIC has completed hashing the 472 */ 473 474 /* 83FC0000 0x4000 CSPI */ 475 cspi@83fc0000 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 479 reg = <0x83fc0000 0x4000>; 480 interrupt-parent = <&tzic>; interrupts = <38>; 481 status = "disabled"; 482 }; 483 484 /* 83FC4000 0x4000 I2C2 */ 485 i2c@83fc4000 { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 489 reg = <0x83fc4000 0x4000>; 490 interrupt-parent = <&tzic>; interrupts = <63>; 491 status = "disabled"; 492 }; 493 494 /* 83FC8000 0x4000 I2C1 */ 495 i2c@83fc8000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 499 reg = <0x83fc8000 0x4000>; 500 interrupt-parent = <&tzic>; interrupts = <62>; 501 status = "disabled"; 502 }; 503 504 /* 83FCC000 0x4000 SSI1 */ 505 /* 29 SSI1 SSI-1 Interrupt Request */ 506 SSI1: ssi@83fcc000 { 507 compatible = "fsl,imx51-ssi"; 508 reg = <0x83fcc000 0x4000>; 509 interrupt-parent = <&tzic>; interrupts = <29>; 510 status = "disabled"; 511 }; 512 513 /* 83FD0000 0x4000 AUDMUX */ 514 audmux@83fd4000 { 515 compatible = "fsl,imx51-audmux"; 516 reg = <0x83fd4000 0x4000>; 517 status = "disabled"; 518 }; 519 520 /* 83FD8000 0x4000 EMI1 */ 521 /* 8 EMI (NFC) */ 522 /* 15 EMI */ 523 /* 97 EMI Boot sequence completed interrupt */ 524 /* 525 * 101 EMI Indicates all pages have been transferred 526 * to NFC during an auto program operation. 527 */ 528 529 /* 83FE0000 0x4000 PATA (PORT PIO) */ 530 /* 70 PATA Parallel ATA host controller interrupt */ 531 ide@83fe0000 { 532 compatible = "fsl,imx51-ata"; 533 reg = <0x83fe0000 0x4000>; 534 interrupt-parent = <&tzic>; 535 interrupts = <70>; 536 status = "disabled"; 537 }; 538 539 /* 83FE4000 0x4000 SIM */ 540 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ 541 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ 542 543 /* 83FE8000 0x4000 SSI3 */ 544 /* 96 SSI3 SSI-3 Interrupt Request */ 545 SSI3: ssi@83fe8000 { 546 compatible = "fsl,imx51-ssi"; 547 reg = <0x83fe8000 0x4000>; 548 interrupt-parent = <&tzic>; interrupts = <96>; 549 status = "disabled"; 550 }; 551 552 /* 83FEC000 0x4000 FEC */ 553 ethernet@83fec000 { 554 compatible = "fsl,imx51-fec"; 555 reg = <0x83fec000 0x4000>; 556 interrupt-parent = <&tzic>; interrupts = <87>; 557 status = "disabled"; 558 }; 559 560 /* 83FF0000 0x4000 TVE */ 561 /* 92 TVE */ 562 /* 83FF4000 0x4000 VPU */ 563 /* 9 VPU */ 564 /* 100 VPU Idle interrupt from VPU */ 565 566 /* 83FF8000 0x4000 SAHARA Lite */ 567 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */ 568 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */ 569 }; 570 }; 571 572 localbus@5e000000 { 573 compatible = "simple-bus"; 574 #address-cells = <1>; 575 #size-cells = <1>; 576 577 ranges; 578 579 vga: ipu3@5e000000 { 580 compatible = "fsl,ipu3"; 581 reg = < 582 0x5e000000 0x08000 /* CM */ 583 0x5e008000 0x08000 /* IDMAC */ 584 0x5e018000 0x08000 /* DP */ 585 0x5e020000 0x08000 /* IC */ 586 0x5e028000 0x08000 /* IRT */ 587 0x5e030000 0x08000 /* CSI0 */ 588 0x5e038000 0x08000 /* CSI1 */ 589 0x5e040000 0x08000 /* DI0 */ 590 0x5e048000 0x08000 /* DI1 */ 591 0x5e050000 0x08000 /* SMFC */ 592 0x5e058000 0x08000 /* DC */ 593 0x5e060000 0x08000 /* DMFC */ 594 0x5e068000 0x08000 /* VDI */ 595 0x5f000000 0x20000 /* CPMEM */ 596 0x5f020000 0x20000 /* LUT */ 597 0x5f040000 0x20000 /* SRM */ 598 0x5f060000 0x20000 /* TPM */ 599 0x5f080000 0x20000 /* DCTMPL */ 600 >; 601 interrupt-parent = <&tzic>; 602 interrupts = < 603 10 /* IPUEX Error */ 604 11 /* IPUEX Sync */ 605 >; 606 status = "disabled"; 607 }; 608 }; 609 }; 610 611 /* 612 613 TODO: Not mapped interrupts 614 615 5 DAP 616 84 GPU2D (OpenVG) general interrupt 617 85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 618 12 GPU3D 619 102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 620 90 SJC 621 */
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