The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts

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    1 /*-
    2  * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * This software was developed by SRI International and the University of
    6  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
    7  * ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * $FreeBSD: stable/12/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts 339422 2018-10-18 15:17:58Z br $
   31  */
   32 
   33 /dts-v1/;
   34 #include "socfpga_arria10_socdk.dtsi"
   35 
   36 / {
   37         model = "Altera SOCFPGA Arria 10";
   38         compatible = "altr,socfpga-arria10", "altr,socfpga";
   39 
   40         /* Reserve first page for secondary CPU trampoline code */
   41         memreserve = < 0x00000000 0x1000 >;
   42 
   43         soc {
   44                 /* Local timer */
   45                 timer@ffffc600 {
   46                         clock-frequency = <200000000>;
   47                 };
   48 
   49                 /* Global timer */
   50                 global_timer: timer@ffffc200 {
   51                         compatible = "arm,cortex-a9-global-timer";
   52                         reg = <0xffffc200 0x20>;
   53                         interrupts = <1 11 0x301>;
   54                         clock-frequency = <200000000>;
   55                 };
   56         };
   57 
   58         chosen {
   59                 stdin = "serial1";
   60                 stdout = "serial1";
   61         };
   62 };
   63 
   64 &uart1 {
   65         clock-frequency = < 50000000 >;
   66 };
   67 
   68 &mmc {
   69         status = "okay";
   70         num-slots = <1>;
   71         cap-sd-highspeed;
   72         broken-cd;
   73         bus-width = <4>;
   74         bus-frequency = <200000000>;
   75 };
   76 
   77 &i2c1 {
   78         lcd@28 {
   79                 compatible = "newhaven,nhd-0216k3z-nsw-bbw";
   80                 reg = <0x28>;
   81         };
   82 };
   83 
   84 &usb0 {
   85         dr_mode = "host";
   86 };
   87 
   88 &qspi {
   89         status = "okay";
   90 
   91         dmas = <&pdma 24>, <&pdma 25>;
   92         dma-names = "tx", "rx";
   93 
   94         flash0: n25q00@0 {
   95                 #address-cells = <1>;
   96                 #size-cells = <1>;
   97                 compatible = "n25q00aa";
   98                 reg = <0>;
   99                 spi-max-frequency = <100000000>;
  100 
  101                 m25p,fast-read;
  102                 cdns,page-size = <256>;
  103                 cdns,block-size = <16>;
  104                 cdns,read-delay = <4>;
  105                 cdns,tshsl-ns = <50>;
  106                 cdns,tsd2d-ns = <50>;
  107                 cdns,tchsh-ns = <4>;
  108                 cdns,tslch-ns = <4>;
  109 
  110                 partition@qspi-boot {
  111                         label = "boot";
  112                         reg = <0x0 0x2720000>;
  113                 };
  114 
  115                 partition@qspi-rootfs {
  116                         label = "rootfs";
  117                         reg = <0x2720000 0x58E0000>;
  118                 };
  119         };
  120 };

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