The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dts/arm/ts7800.dts

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    1 /*
    2  * Copyright (c) 2010 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * Technologic Systems TS-7800 Device Tree Source.
   27  *
   28  * $FreeBSD: head/sys/dts/arm/ts7800.dts 325826 2017-11-14 21:03:57Z imp $
   29  */
   30 
   31 /dts-v1/;
   32 
   33 / {
   34         model = "mrvl,TS-7800";
   35         compatible = "DB-88F5182-BP", "DB-88F5182-BP-A";
   36         #address-cells = <1>;
   37         #size-cells = <1>;
   38 
   39         aliases {
   40                 ethernet0 = &mge0;
   41                 serial0 = &serial0;
   42                 serial1 = &serial1;
   43                 mpp = &MPP;
   44         };
   45 
   46         cpus {
   47                 #address-cells = <1>;
   48                 #size-cells = <0>;
   49 
   50                 cpu@0 {
   51                         device_type = "cpu";
   52                         compatible = "ARM,88FR531";
   53                         reg = <0x0>;
   54                         d-cache-line-size = <32>;       // 32 bytes
   55                         i-cache-line-size = <32>;       // 32 bytes
   56                         d-cache-size = <0x8000>;        // L1, 32K
   57                         i-cache-size = <0x8000>;        // L1, 32K
   58                         timebase-frequency = <0>;
   59                         bus-frequency = <0>;
   60                         clock-frequency = <0>;
   61                 };
   62         };
   63 
   64         memory {
   65                 device_type = "memory";
   66                 reg = <0x0 0x08000000>;         // 128M at 0x0
   67         };
   68 
   69         localbus@f1000000 {
   70                 #address-cells = <2>;
   71                 #size-cells = <1>;
   72                 compatible = "mrvl,lbc";
   73 
   74                 /* This reflects CPU decode windows setup. */
   75                 ranges = <0x0 0x0f 0xf9300000 0x00100000
   76                           0x1 0x1e 0xfa000000 0x00100000
   77                           0x2 0x1d 0xfa100000 0x02000000>;
   78         };
   79 
   80         soc88f5182@f1000000 {
   81                 #address-cells = <1>;
   82                 #size-cells = <1>;
   83                 compatible = "simple-bus";
   84                 ranges = <0x0 0xf1000000 0x00100000>;
   85                 bus-frequency = <0>;
   86 
   87                 PIC: pic@20200 {
   88                         interrupt-controller;
   89                         #address-cells = <0>;
   90                         #interrupt-cells = <1>;
   91                         reg = <0x20200 0x3c>;
   92                         compatible = "mrvl,pic";
   93                 };
   94 
   95                 timer@20300 {
   96                         compatible = "mrvl,timer";
   97                         reg = <0x20300 0x30>;
   98                         interrupts = <0>;
   99                         interrupt-parent = <&PIC>;
  100                         mrvl,has-wdt;
  101                 };
  102 
  103                 MPP: mpp@10000 {
  104                         #pin-cells = <2>;
  105                         compatible = "mrvl,mpp";
  106                         reg = <0x10000 0x54>;
  107                         pin-count = <20>;
  108                         pin-map = <
  109                                 16 0            /* MPP[16]: UA1_RXD */
  110                                 17 0            /* MPP[17]: UA1_TXD */
  111                                 19 0 >;         /* MPP[19]: UA1_RTS */
  112                 };
  113 
  114                 mge0: ethernet@72000 {
  115                         #address-cells = <1>;
  116                         #size-cells = <1>;
  117                         model = "V1";
  118                         compatible = "mrvl,ge";
  119                         reg = <0x72000 0x2000>;
  120                         ranges = <0x0 0x72000 0x2000>;
  121                         local-mac-address = [ 00 00 00 00 00 00 ];
  122                         interrupts = <18 19 20 21 22>;
  123                         interrupt-parent = <&PIC>;
  124 
  125                         phy-handle = <&phy0>;
  126 
  127                         mdio@0 {
  128                                 #address-cells = <1>;
  129                                 #size-cells = <0>;
  130                                 compatible = "mrvl,mdio";
  131 
  132                                 phy0: ethernet-phy@0 {
  133                                         reg = <0x0>;
  134                                 };
  135                         };
  136                 };
  137 
  138                 serial0: serial@12000 {
  139                         compatible = "ns16550";
  140                         reg = <0x12000 0x20>;
  141                         reg-shift = <2>;
  142                         clock-frequency = <0>;
  143                         interrupts = <3>;
  144                         interrupt-parent = <&PIC>;
  145                 };
  146 
  147                 serial1: serial@12100 {
  148                         compatible = "ns16550";
  149                         reg = <0x12100 0x20>;
  150                         reg-shift = <2>;
  151                         clock-frequency = <0>;
  152                         interrupts = <4>;
  153                         interrupt-parent = <&PIC>;
  154                 };
  155         };
  156 
  157         chosen {
  158                 stdin = "serial0";
  159                 stdout = "serial0";
  160         };
  161 };

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