Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dts/arm/zynq-7000.dtsi
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2016 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 / { 30 compatible = "xlnx,zynq-7000"; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 interrupt-parent = <&GIC>; 34 35 // Reserve first half megabyte because it is not accessible to all 36 // bus masters. 37 memreserve = <0x00000000 0x00080000>; 38 39 // Zynq PS System registers. 40 // 41 ps7sys@f8000000 { 42 device_type = "soc"; 43 compatible = "simple-bus"; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0xf8000000 0xf10000>; 47 48 // SLCR block 49 slcr: slcr@7000 { 50 compatible = "xlnx,zy7_slcr"; 51 reg = <0x0 0x1000>; 52 }; 53 54 // Interrupt controller 55 GIC: gic { 56 compatible = "arm,gic"; 57 interrupt-controller; 58 #address-cells = <0>; 59 #interrupt-cells = <3>; 60 reg = <0xf01000 0x1000>, // distributer registers 61 <0xf00100 0x0100>; // CPU if registers 62 }; 63 64 // L2 cache controller 65 pl310@f02000 { 66 compatible = "arm,pl310"; 67 reg = <0xf02000 0x1000>; 68 interrupts = <0 2 4>; 69 interrupt-parent = <&GIC>; 70 }; 71 72 // Device Config 73 devcfg: devcfg@7000 { 74 compatible = "xlnx,zy7_devcfg"; 75 reg = <0x7000 0x1000>; 76 interrupts = <0 8 4>; 77 interrupt-parent = <&GIC>; 78 }; 79 80 // triple timer counters0,1 81 ttc0: ttc@1000 { 82 compatible = "xlnx,ttc"; 83 reg = <0x1000 0x1000>; 84 }; 85 86 ttc1: ttc@2000 { 87 compatible = "xlnx,ttc"; 88 reg = <0x2000 0x1000>; 89 }; 90 91 // ARM Cortex A9 TWD Timer 92 global_timer: timer@f00600 { 93 compatible = "arm,mpcore-timers"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 reg = <0xf00200 0x100>, // Global Timer Regs 97 <0xf00600 0x20>; // Private Timer Regs 98 interrupts = <1 11 1>, <1 13 1>; 99 interrupt-parent = <&GIC>; 100 }; 101 102 // system watch-dog timer 103 swdt@5000 { 104 device_type = "watchdog"; 105 compatible = "xlnx,zy7_wdt"; 106 reg = <0x5000 0x1000>; 107 interrupts = <0 9 1>; 108 interrupt-parent = <&GIC>; 109 }; 110 111 scuwdt@f00620 { 112 device_type = "watchdog"; 113 compatible = "arm,mpcore_wdt"; 114 reg = <0xf00620 0x20>; 115 interrupts = <1 14 1>; 116 interrupt-parent = <&GIC>; 117 reset = <1>; 118 }; 119 120 }; // pssys@f8000000 121 122 // Zynq PS I/O Peripheral registers. 123 // 124 ps7io@e0000000 { 125 device_type = "soc"; 126 compatible = "simple-bus"; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0x0 0xe0000000 0x300000>; 130 131 // UART controllers 132 uart0: uart@0000 { 133 device_type = "serial"; 134 compatible = "cadence,uart"; 135 status = "disabled"; 136 reg = <0x0000 0x1000>; 137 interrupts = <0 27 4>; 138 interrupt-parent = <&GIC>; 139 clock-frequency = <50000000>; 140 }; 141 142 uart1: uart@1000 { 143 device_type = "serial"; 144 compatible = "cadence,uart"; 145 status = "disabled"; 146 reg = <0x1000 0x1000>; 147 interrupts = <0 50 4>; 148 interrupt-parent = <&GIC>; 149 clock-frequency = <50000000>; 150 }; 151 152 // USB controllers 153 ehci0: ehci@2000 { 154 compatible = "xlnx,zy7_ehci"; 155 status = "disabled"; 156 reg = <0x2000 0x1000>; 157 interrupts = <0 21 4>; 158 interrupt-parent = <&GIC>; 159 }; 160 161 ehci1: ehci@3000 { 162 compatible = "xlnx,zy7_ehci"; 163 status = "disabled"; 164 reg = <0x3000 0x1000>; 165 interrupts = <0 44 4>; 166 interrupt-parent = <&GIC>; 167 }; 168 169 // GPIO controller 170 gpio: gpio@a000 { 171 compatible = "xlnx,zy7_gpio"; 172 reg = <0xa000 0x1000>; 173 interrupts = <0 20 4>; 174 interrupt-parent = <&GIC>; 175 }; 176 177 // Gigabit Ethernet controllers 178 eth0: eth@b000 { 179 device_type = "network"; 180 compatible = "cdns,zynq-gem", "cadence,gem"; 181 status = "disabled"; 182 reg = <0xb000 0x1000>; 183 interrupts = <0 22 4>; 184 interrupt-parent = <&GIC>; 185 ref-clock-num = <0>; 186 }; 187 188 eth1: eth@c000 { 189 device_type = "network"; 190 compatible = "cdns,zynq-gem", "cadence,gem"; 191 status = "disabled"; 192 reg = <0xc000 0x1000>; 193 interrupts = <0 45 4>; 194 interrupt-parent = <&GIC>; 195 ref-clock-num = <1>; 196 }; 197 198 // Quad-SPI controller 199 qspi0: qspi@d000 { 200 compatible = "xlnx,zy7_qspi"; 201 status = "disabled"; 202 reg = <0xd000 0x1000>; 203 interrupts = <0 19 4>; 204 interrupt-parent = <&GIC>; 205 ref-clock = <200000000>; // 200 Mhz 206 spi-clock = <50000000>; // 50 Mhz 207 }; 208 209 // SPI controllers 210 spi0: spi0@6000 { 211 compatible = "xlnx,zy7_spi"; 212 status = "disabled"; 213 reg = <0x6000 0x100>; 214 interrupts = <0 26 4>; 215 interrupt-parent = <&GIC>; 216 }; 217 218 spi1: spi0@7000 { 219 compatible = "xlnx,zy7_spi"; 220 status = "disabled"; 221 reg = <0x7000 0x100>; 222 interrupts = <0 49 4>; 223 interrupt-parent = <&GIC>; 224 }; 225 226 // SDIO controllers 227 sdhci0: sdhci@100000 { 228 compatible = "xlnx,zy7_sdhci"; 229 status = "disabled"; 230 reg = <0x100000 0x1000>; 231 interrupts = <0 24 4>; 232 interrupt-parent = <&GIC>; 233 max-frequency = <50000000>; 234 }; 235 236 sdhci1: sdhci@101000 { 237 compatible = "xlnx,zy7_sdhci"; 238 status = "disabled"; 239 reg = <0x101000 0x1000>; 240 interrupts = <0 47 4>; 241 interrupt-parent = <&GIC>; 242 max-frequency = <50000000>; 243 }; 244 245 }; // ps7io@e0000000 246 }; 247
Cache object: 906dc6ed54c902dd179f675d8e23e2a4
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]