The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dts/mips/beri-sim.dts

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2012-2013 Robert N. M. Watson
    3  * Copyright (c) 2013 SRI International
    4  * All rights reserved.
    5  *
    6  * This software was developed by SRI International and the University of
    7  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
    8  * ("CTSRD"), as part of the DARPA CRASH research programme.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  * $FreeBSD$
   32  */
   33 
   34 /dts-v1/;
   35 
   36 /*
   37  * Device names here have been largely made up on the spot, especially for the
   38  * "compatible" strings, and might want to be revised.
   39  *
   40  * For now, use 32-bit addressing as our Avalon bus is 32-bit.  However, in
   41  * the future, we should likely change to 64-bit.
   42  */
   43 
   44 / {
   45         model = "SRI/Cambridge BERI simulation";
   46         compatible = "sri-cambridge,beri-sim";
   47         #address-cells = <1>;
   48         #size-cells = <1>;
   49 
   50         cpus {
   51                 #address-cells = <1>;
   52                 #size-cells = <1>;
   53 
   54                 /*
   55                  * Secondary CPUs all start disabled and use the
   56                  * spin-table enable method.  cpu-release-addr must be
   57                  * specified for each cpu other than cpu@0.  Values of
   58                  * cpu-release-addr grow down from 0x100000 (kernel).
   59                  */
   60                 status = "disabled";
   61                 enable-method = "spin-table";
   62 
   63                 cpu@0 {
   64                         device-type = "cpu";
   65                         compatible = "sri-cambridge,beri";
   66 
   67                         reg = <0 1>;
   68                         status = "okay";
   69                 };
   70 
   71 /*
   72                 cpu@1 {
   73                         device-type = "cpu";
   74                         compatible = "sri-cambridge,beri";
   75 
   76                         reg = <1 1>;
   77                         // XXX: should we need cached prefix?
   78                         cpu-release-addr = <0xffffffff 0x800fffe0>;
   79                 };
   80 */
   81         };
   82 
   83         memory {
   84                 device_type = "memory";
   85                 reg = <0x0 0x4000000>;          // 64M at 0x0
   86         };
   87 
   88         cpuintc: cpuintc@0 {
   89                 #address-cells = <0>;
   90                 #interrupt-cells = <1>;
   91                 interrupt-controller;
   92                 compatible = "mti,cpu-interrupt-controller";
   93         };
   94 
   95         beripic0: beripic@7f804000 {
   96                 compatible = "sri-cambridge,beri-pic";
   97                 interrupt-controller;
   98                 #address-cells = <0>;
   99                 #interrupt-cells = <1>;
  100                 reg = <0x7f804000 0x400
  101                        0x7f806000 0x10
  102                        0x7f806080 0x10
  103                        0x7f806100 0x10>;
  104                 interrupts = < 2 3 4 5 6 >;
  105                 hard-interrupt-sources = <64>;
  106                 soft-interrupt-sources = <64>;
  107                 interrupt-parent = <&cpuintc>;
  108         };
  109 
  110         soc {
  111                 #address-cells = <1>;
  112                 #size-cells = <1>;
  113                 #interrupt-cells = <1>;
  114 
  115                 compatible = "simple-bus", "mips,mips4k";
  116                 ranges;
  117 
  118                 serial@7f000000 {
  119                         compatible = "altera,jtag_uart-11_0";
  120                         reg = <0x7f000000 0x40>;
  121                         interrupts = <0>;
  122                         interrupt-parent = <&beripic0>;
  123                 };
  124 
  125                 serial@7f001000 {
  126                         compatible = "altera,jtag_uart-11_0";
  127                         reg = <0x7f001000 0x40>;
  128                 };
  129 
  130                 serial@7f002000 {
  131                         compatible = "altera,jtag_uart-11_0";
  132                         reg = <0x7f002000 0x40>;
  133                 };
  134 
  135                 virtio_mmio_platform0: virtio_mmio_platform@0 {
  136                         compatible = "beri,virtio_mmio_platform";
  137                         interrupts = <1>;
  138                         interrupt-parent = <&beripic0>;
  139                 };
  140 
  141                 virtio_block@7f020000 {
  142                         compatible = "virtio,mmio";
  143                         reg = <0x7f020000 0x1000>;
  144                         platform = <&virtio_mmio_platform0>;
  145                 };
  146 
  147                 sdcard@7f008000 {
  148                         compatible = "altera,sdcard_11_2011";
  149                         reg = <0x7f008000 0x400>;
  150                 };
  151 
  152                 avgen@0x7f00a000 {
  153                         compatible = "sri-cambridge,avgen";
  154                         reg = <0x7f00a000 0x14>;
  155                         sri-cambridge,width = <4>;
  156                         sri-cambridge,fileio = "rw";
  157                         sri-cambridge,devname = "berirom";
  158                 };
  159         };
  160 };

Cache object: eed182230edeb104fc752130c20d9582


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.