1 /*
2 * MPC8555 CDS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc. All rights reserved
5 *
6 * Neither the name of Freescale Semiconductor, Inc nor the names of
7 * its contributors may be used to endorse or promote products derived
8 * from this software without specific prior written permission.
9 *
10 * Freescale hereby publishes it under the following licenses:
11 *
12 * BSD License
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in
23 * the documentation and/or other materials provided with the
24 * distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * GNU General Public License, version 2
41 *
42 * This program is free software; you can redistribute it and/or
43 * modify it under the terms of the GNU General Public License
44 * as published by the Free Software Foundation; either version 2
45 * of the License, or (at your option) any later version.
46 *
47 * This program is distributed in the hope that it will be useful,
48 * but WITHOUT ANY WARRANTY; without even the implied warranty of
49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50 * GNU General Public License for more details.
51 *
52 * You should have received a copy of the GNU General Public License
53 * along with this program; if not, write to the Free Software
54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
55 * MA 02110-1301, USA.
56 *
57 * You may select the license of your choice.
58 *------------------------------------------------------------------
59 *
60 * $FreeBSD$
61 */
62
63 /dts-v1/;
64
65 / {
66 model = "MPC8555CDS";
67 compatible = "MPC8555CDS", "MPC85xxCDS";
68 #address-cells = <1>;
69 #size-cells = <1>;
70
71 aliases {
72 ethernet0 = &enet0;
73 ethernet1 = &enet1;
74 serial0 = &serial0;
75 serial1 = &serial1;
76 pci0 = &pci0;
77 pci1 = &pci1;
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 PowerPC,8555@0 {
85 device_type = "cpu";
86 reg = <0x0>;
87 d-cache-line-size = <32>; // 32 bytes
88 i-cache-line-size = <32>; // 32 bytes
89 d-cache-size = <0x8000>; // L1, 32K
90 i-cache-size = <0x8000>; // L1, 32K
91 timebase-frequency = <0>; // 33 MHz, from uboot
92 bus-frequency = <0>; // 166 MHz
93 clock-frequency = <0>; // 825 MHz, from uboot
94 next-level-cache = <&L2>;
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 reg = <0x0 0x10000000>; // 256M at 0x0
101 };
102
103 localbus@e0005000 {
104 #address-cells = <2>;
105 #size-cells = <1>;
106 compatible = "fsl,lbc", "fsl,elbc";
107 reg = <0xe0005000 0x1000>;
108 interrupts = <19 2>;
109 interrupt-parent = <&mpic>;
110
111 ranges = <0x0 0x0 0xff800000 0x00800000
112 0x1 0x0 0xff000000 0x00800000
113 0x2 0x0 0xf8000000 0x00008000>;
114
115 nor@0,0 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 compatible = "cfi-flash";
119 reg = <0x0 0x0 0x00800000>;
120 bank-width = <2>;
121 device-width = <1>;
122 };
123
124 nor@1,0 {
125 #address-cells = <1>;
126 #size-cells = <1>;
127 compatible = "cfi-flash";
128 reg = <0x1 0x0 0x00800000>;
129 bank-width = <2>;
130 device-width = <1>;
131 };
132
133 rtc@2,0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "dallas,ds1553";
137 reg = <0x2 0x0 0x00008000>;
138 bank-width = <1>;
139 device-width = <1>;
140 };
141 };
142
143 soc8555@e0000000 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 device_type = "soc";
147 compatible = "simple-bus";
148 ranges = <0x0 0xe0000000 0x100000>;
149 bus-frequency = <0>;
150
151 ecm-law@0 {
152 compatible = "fsl,ecm-law";
153 reg = <0x0 0x1000>;
154 fsl,num-laws = <8>;
155 };
156
157 ecm@1000 {
158 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
159 reg = <0x1000 0x1000>;
160 interrupts = <17 2>;
161 interrupt-parent = <&mpic>;
162 };
163
164 memory-controller@2000 {
165 compatible = "fsl,8555-memory-controller";
166 reg = <0x2000 0x1000>;
167 interrupt-parent = <&mpic>;
168 interrupts = <18 2>;
169 };
170
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,8555-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x40000>; // L2, 256K
176 interrupt-parent = <&mpic>;
177 interrupts = <16 2>;
178 };
179
180 i2c@3000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 cell-index = <0>;
184 compatible = "fsl-i2c";
185 reg = <0x3000 0x100>;
186 interrupts = <43 2>;
187 interrupt-parent = <&mpic>;
188 dfsrr;
189 };
190
191 dma@21300 {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
195 reg = <0x21300 0x4>;
196 ranges = <0x0 0x21100 0x200>;
197 cell-index = <0>;
198 dma-channel@0 {
199 compatible = "fsl,mpc8555-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x0 0x80>;
202 cell-index = <0>;
203 interrupt-parent = <&mpic>;
204 interrupts = <20 2>;
205 };
206 dma-channel@80 {
207 compatible = "fsl,mpc8555-dma-channel",
208 "fsl,eloplus-dma-channel";
209 reg = <0x80 0x80>;
210 cell-index = <1>;
211 interrupt-parent = <&mpic>;
212 interrupts = <21 2>;
213 };
214 dma-channel@100 {
215 compatible = "fsl,mpc8555-dma-channel",
216 "fsl,eloplus-dma-channel";
217 reg = <0x100 0x80>;
218 cell-index = <2>;
219 interrupt-parent = <&mpic>;
220 interrupts = <22 2>;
221 };
222 dma-channel@180 {
223 compatible = "fsl,mpc8555-dma-channel",
224 "fsl,eloplus-dma-channel";
225 reg = <0x180 0x80>;
226 cell-index = <3>;
227 interrupt-parent = <&mpic>;
228 interrupts = <23 2>;
229 };
230 };
231
232 enet0: ethernet@24000 {
233 #address-cells = <1>;
234 #size-cells = <1>;
235 cell-index = <0>;
236 device_type = "network";
237 model = "TSEC";
238 compatible = "gianfar";
239 reg = <0x24000 0x1000>;
240 ranges = <0x0 0x24000 0x1000>;
241 local-mac-address = [ 00 00 00 00 00 00 ];
242 interrupts = <29 2 30 2 34 2>;
243 interrupt-parent = <&mpic>;
244 tbi-handle = <&tbi0>;
245 phy-handle = <&phy0>;
246
247 mdio@520 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,gianfar-mdio";
251 reg = <0x520 0x20>;
252
253 phy0: ethernet-phy@0 {
254 interrupt-parent = <&mpic>;
255 interrupts = <5 1>;
256 reg = <0x0>;
257 device_type = "ethernet-phy";
258 };
259 phy1: ethernet-phy@1 {
260 interrupt-parent = <&mpic>;
261 interrupts = <5 1>;
262 reg = <0x1>;
263 device_type = "ethernet-phy";
264 };
265 tbi0: tbi-phy@11 {
266 reg = <0x11>;
267 device_type = "tbi-phy";
268 };
269 };
270 };
271
272 enet1: ethernet@25000 {
273 #address-cells = <1>;
274 #size-cells = <1>;
275 cell-index = <1>;
276 device_type = "network";
277 model = "TSEC";
278 compatible = "gianfar";
279 reg = <0x25000 0x1000>;
280 ranges = <0x0 0x25000 0x1000>;
281 local-mac-address = [ 00 00 00 00 00 00 ];
282 interrupts = <35 2 36 2 40 2>;
283 interrupt-parent = <&mpic>;
284 tbi-handle = <&tbi1>;
285 phy-handle = <&phy1>;
286
287 mdio@520 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "fsl,gianfar-tbi";
291 reg = <0x520 0x20>;
292
293 tbi1: tbi-phy@11 {
294 reg = <0x11>;
295 device_type = "tbi-phy";
296 };
297 };
298 };
299
300 serial0: serial@4500 {
301 cell-index = <0>;
302 device_type = "serial";
303 compatible = "ns16550";
304 reg = <0x4500 0x100>; // reg base, size
305 clock-frequency = <0>; // should we fill in in uboot?
306 interrupts = <42 2>;
307 interrupt-parent = <&mpic>;
308 };
309
310 serial1: serial@4600 {
311 cell-index = <1>;
312 device_type = "serial";
313 compatible = "ns16550";
314 reg = <0x4600 0x100>; // reg base, size
315 clock-frequency = <0>; // should we fill in in uboot?
316 interrupts = <42 2>;
317 interrupt-parent = <&mpic>;
318 };
319
320 crypto@30000 {
321 compatible = "fsl,sec2.0";
322 reg = <0x30000 0x10000>;
323 interrupts = <45 2>;
324 interrupt-parent = <&mpic>;
325 fsl,num-channels = <4>;
326 fsl,channel-fifo-len = <24>;
327 fsl,exec-units-mask = <0x7e>;
328 fsl,descriptor-types-mask = <0x01010ebf>;
329 };
330
331 mpic: pic@40000 {
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <2>;
335 reg = <0x40000 0x40000>;
336 compatible = "chrp,open-pic";
337 device_type = "open-pic";
338 };
339
340 cpm@80000 {
341 #address-cells = <1>;
342 #size-cells = <1>;
343 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
344 reg = <0x80000 0x20000>;
345 interrupts = <46 2>;
346 interrupt-parent = <&mpic>;
347 };
348 };
349
350 pci0: pci@e0008000 {
351 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
352 interrupt-map = <
353
354 /* IDSEL 0x10 */
355 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
356 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
357 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
358 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
359
360 /* IDSEL 0x11 */
361 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
362 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
363 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
364 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
365
366 /* IDSEL 0x12 (Slot 1) */
367 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
368 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
369 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
370 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
371
372 /* IDSEL 0x13 (Slot 2) */
373 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
374 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
375 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
376 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
377
378 /* IDSEL 0x14 (Slot 3) */
379 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
380 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
381 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
382 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
383
384 /* IDSEL 0x15 (Slot 4) */
385 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
386 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
387 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
388 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
389
390 /* Bus 1 (Tundra Bridge) */
391 /* IDSEL 0x12 (ISA bridge) */
392 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
393 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
394 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
395 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
396 interrupt-parent = <&mpic>;
397 interrupts = <24 2>;
398 bus-range = <0 0>;
399 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
400 0x1000000 0x0 0x0 0xfee00000 0x0 0x00010000>;
401 clock-frequency = <66666666>;
402 #interrupt-cells = <1>;
403 #size-cells = <2>;
404 #address-cells = <3>;
405 reg = <0xe0008000 0x1000>;
406 compatible = "fsl,mpc8540-pci";
407 device_type = "pci";
408
409 i8259@19000 {
410 interrupt-controller;
411 device_type = "interrupt-controller";
412 reg = <0x19000 0x0 0x0 0x0 0x1>;
413 #address-cells = <0>;
414 #interrupt-cells = <2>;
415 compatible = "chrp,iic";
416 interrupts = <1>;
417 interrupt-parent = <&pci0>;
418 };
419 };
420
421 pci1: pci@e0009000 {
422 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
423 interrupt-map = <
424
425 /* IDSEL 0x15 */
426 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
427 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
428 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
429 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
430 interrupt-parent = <&mpic>;
431 interrupts = <25 2>;
432 bus-range = <0 0>;
433 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
434 0x1000000 0x0 0x0 0xfee10000 0x0 0x00010000>;
435 clock-frequency = <66666666>;
436 #interrupt-cells = <1>;
437 #size-cells = <2>;
438 #address-cells = <3>;
439 reg = <0xe0009000 0x1000>;
440 compatible = "fsl,mpc8540-pci";
441 device_type = "pci";
442 };
443 };
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