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sys/dts/powerpc/mpc8572ds.dts
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1 /* 2 * MPC8572 DS Device Tree Source 3 * 4 * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved 5 * 6 * Neither the name of Freescale Semiconductor, Inc nor the names of 7 * its contributors may be used to endorse or promote products derived 8 * from this software without specific prior written permission. 9 * 10 * Freescale hereby publishes it under the following licenses: 11 * 12 * BSD License 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in 23 * the documentation and/or other materials provided with the 24 * distribution. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * GNU General Public License, version 2 41 * 42 * This program is free software; you can redistribute it and/or 43 * modify it under the terms of the GNU General Public License 44 * as published by the Free Software Foundation; either version 2 45 * of the License, or (at your option) any later version. 46 * 47 * This program is distributed in the hope that it will be useful, 48 * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 * GNU General Public License for more details. 51 * 52 * You should have received a copy of the GNU General Public License 53 * along with this program; if not, write to the Free Software 54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 55 * MA 02110-1301, USA. 56 * 57 * You may select the license of your choice. 58 *------------------------------------------------------------------ 59 * 60 * $FreeBSD: releng/12.0/sys/dts/powerpc/mpc8572ds.dts 325826 2017-11-14 21:03:57Z imp $ 61 */ 62 63 /dts-v1/; 64 / { 65 model = "fsl,MPC8572DS"; 66 compatible = "fsl,MPC8572DS"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 70 aliases { 71 ethernet0 = &enet0; 72 ethernet1 = &enet1; 73 ethernet2 = &enet2; 74 ethernet3 = &enet3; 75 serial0 = &serial0; 76 serial1 = &serial1; 77 pci0 = &pci0; 78 pci1 = &pci1; 79 pci2 = &pci2; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 PowerPC,8572@0 { 87 device_type = "cpu"; 88 reg = <0x0>; 89 d-cache-line-size = <32>; // 32 bytes 90 i-cache-line-size = <32>; // 32 bytes 91 d-cache-size = <0x8000>; // L1, 32K 92 i-cache-size = <0x8000>; // L1, 32K 93 timebase-frequency = <0>; 94 bus-frequency = <0>; 95 clock-frequency = <0>; 96 next-level-cache = <&L2>; 97 }; 98 99 PowerPC,8572@1 { 100 device_type = "cpu"; 101 reg = <0x1>; 102 d-cache-line-size = <32>; // 32 bytes 103 i-cache-line-size = <32>; // 32 bytes 104 d-cache-size = <0x8000>; // L1, 32K 105 i-cache-size = <0x8000>; // L1, 32K 106 timebase-frequency = <0>; 107 bus-frequency = <0>; 108 clock-frequency = <0>; 109 next-level-cache = <&L2>; 110 }; 111 }; 112 113 memory { 114 device_type = "memory"; 115 }; 116 117 localbus@ffe05000 { 118 #address-cells = <2>; 119 #size-cells = <1>; 120 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 121 reg = <0 0xffe05000 0 0x1000>; 122 interrupts = <19 2>; 123 interrupt-parent = <&mpic>; 124 125 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000>; 126 127 nor@0,0 { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 compatible = "cfi-flash"; 131 reg = <0x0 0x0 0x8000000>; 132 bank-width = <2>; 133 device-width = <1>; 134 135 partition@0 { 136 reg = <0x0 0x03000000>; 137 label = "ramdisk-nor"; 138 read-only; 139 }; 140 141 partition@3000000 { 142 reg = <0x03000000 0x00e00000>; 143 label = "diagnostic-nor"; 144 read-only; 145 }; 146 147 partition@3e00000 { 148 reg = <0x03e00000 0x00200000>; 149 label = "dink-nor"; 150 read-only; 151 }; 152 153 partition@4000000 { 154 reg = <0x04000000 0x00400000>; 155 label = "kernel-nor"; 156 read-only; 157 }; 158 159 partition@4400000 { 160 reg = <0x04400000 0x03b00000>; 161 label = "jffs2-nor"; 162 }; 163 164 partition@7f00000 { 165 reg = <0x07f00000 0x00080000>; 166 label = "dtb-nor"; 167 read-only; 168 }; 169 170 partition@7f80000 { 171 reg = <0x07f80000 0x00080000>; 172 label = "u-boot-nor"; 173 read-only; 174 }; 175 }; 176 177 nand@2,0 { 178 #address-cells = <1>; 179 #size-cells = <1>; 180 compatible = "fsl,mpc8572-fcm-nand", 181 "fsl,elbc-fcm-nand"; 182 reg = <0x2 0x0 0x40000>; 183 184 partition@0 { 185 reg = <0x0 0x02000000>; 186 label = "u-boot-nand"; 187 read-only; 188 }; 189 190 partition@2000000 { 191 reg = <0x02000000 0x10000000>; 192 label = "jffs2-nand"; 193 }; 194 195 partition@12000000 { 196 reg = <0x12000000 0x08000000>; 197 label = "ramdisk-nand"; 198 read-only; 199 }; 200 201 partition@1a000000 { 202 reg = <0x1a000000 0x04000000>; 203 label = "kernel-nand"; 204 }; 205 206 partition@1e000000 { 207 reg = <0x1e000000 0x01000000>; 208 label = "dtb-nand"; 209 read-only; 210 }; 211 212 partition@1f000000 { 213 reg = <0x1f000000 0x21000000>; 214 label = "reserved-nand"; 215 }; 216 }; 217 218 nand@4,0 { 219 compatible = "fsl,mpc8572-fcm-nand", 220 "fsl,elbc-fcm-nand"; 221 reg = <0x4 0x0 0x40000>; 222 }; 223 224 nand@5,0 { 225 compatible = "fsl,mpc8572-fcm-nand", 226 "fsl,elbc-fcm-nand"; 227 reg = <0x5 0x0 0x40000>; 228 }; 229 230 nand@6,0 { 231 compatible = "fsl,mpc8572-fcm-nand", 232 "fsl,elbc-fcm-nand"; 233 reg = <0x6 0x0 0x40000>; 234 }; 235 }; 236 237 soc8572@ffe00000 { 238 #address-cells = <1>; 239 #size-cells = <1>; 240 device_type = "soc"; 241 compatible = "simple-bus"; 242 ranges = <0x0 0 0xffe00000 0x100000>; 243 bus-frequency = <0>; // Filled out by uboot. 244 245 ecm-law@0 { 246 compatible = "fsl,ecm-law"; 247 reg = <0x0 0x1000>; 248 fsl,num-laws = <12>; 249 }; 250 251 ecm@1000 { 252 compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 253 reg = <0x1000 0x1000>; 254 interrupts = <17 2>; 255 interrupt-parent = <&mpic>; 256 }; 257 258 memory-controller@2000 { 259 compatible = "fsl,mpc8572-memory-controller"; 260 reg = <0x2000 0x1000>; 261 interrupt-parent = <&mpic>; 262 interrupts = <18 2>; 263 }; 264 265 memory-controller@6000 { 266 compatible = "fsl,mpc8572-memory-controller"; 267 reg = <0x6000 0x1000>; 268 interrupt-parent = <&mpic>; 269 interrupts = <18 2>; 270 }; 271 272 L2: l2-cache-controller@20000 { 273 compatible = "fsl,mpc8572-l2-cache-controller"; 274 reg = <0x20000 0x1000>; 275 cache-line-size = <32>; // 32 bytes 276 cache-size = <0x100000>; // L2, 1M 277 interrupt-parent = <&mpic>; 278 interrupts = <16 2>; 279 }; 280 281 i2c@3000 { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 cell-index = <0>; 285 compatible = "fsl-i2c"; 286 reg = <0x3000 0x100>; 287 interrupts = <43 2>; 288 interrupt-parent = <&mpic>; 289 dfsrr; 290 }; 291 292 i2c@3100 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 cell-index = <1>; 296 compatible = "fsl-i2c"; 297 reg = <0x3100 0x100>; 298 interrupts = <43 2>; 299 interrupt-parent = <&mpic>; 300 dfsrr; 301 }; 302 303 dma@c300 { 304 #address-cells = <1>; 305 #size-cells = <1>; 306 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 307 reg = <0xc300 0x4>; 308 ranges = <0x0 0xc100 0x200>; 309 cell-index = <1>; 310 dma-channel@0 { 311 compatible = "fsl,mpc8572-dma-channel", 312 "fsl,eloplus-dma-channel"; 313 reg = <0x0 0x80>; 314 cell-index = <0>; 315 interrupt-parent = <&mpic>; 316 interrupts = <76 2>; 317 }; 318 dma-channel@80 { 319 compatible = "fsl,mpc8572-dma-channel", 320 "fsl,eloplus-dma-channel"; 321 reg = <0x80 0x80>; 322 cell-index = <1>; 323 interrupt-parent = <&mpic>; 324 interrupts = <77 2>; 325 }; 326 dma-channel@100 { 327 compatible = "fsl,mpc8572-dma-channel", 328 "fsl,eloplus-dma-channel"; 329 reg = <0x100 0x80>; 330 cell-index = <2>; 331 interrupt-parent = <&mpic>; 332 interrupts = <78 2>; 333 }; 334 dma-channel@180 { 335 compatible = "fsl,mpc8572-dma-channel", 336 "fsl,eloplus-dma-channel"; 337 reg = <0x180 0x80>; 338 cell-index = <3>; 339 interrupt-parent = <&mpic>; 340 interrupts = <79 2>; 341 }; 342 }; 343 344 dma@21300 { 345 #address-cells = <1>; 346 #size-cells = <1>; 347 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 348 reg = <0x21300 0x4>; 349 ranges = <0x0 0x21100 0x200>; 350 cell-index = <0>; 351 dma-channel@0 { 352 compatible = "fsl,mpc8572-dma-channel", 353 "fsl,eloplus-dma-channel"; 354 reg = <0x0 0x80>; 355 cell-index = <0>; 356 interrupt-parent = <&mpic>; 357 interrupts = <20 2>; 358 }; 359 dma-channel@80 { 360 compatible = "fsl,mpc8572-dma-channel", 361 "fsl,eloplus-dma-channel"; 362 reg = <0x80 0x80>; 363 cell-index = <1>; 364 interrupt-parent = <&mpic>; 365 interrupts = <21 2>; 366 }; 367 dma-channel@100 { 368 compatible = "fsl,mpc8572-dma-channel", 369 "fsl,eloplus-dma-channel"; 370 reg = <0x100 0x80>; 371 cell-index = <2>; 372 interrupt-parent = <&mpic>; 373 interrupts = <22 2>; 374 }; 375 dma-channel@180 { 376 compatible = "fsl,mpc8572-dma-channel", 377 "fsl,eloplus-dma-channel"; 378 reg = <0x180 0x80>; 379 cell-index = <3>; 380 interrupt-parent = <&mpic>; 381 interrupts = <23 2>; 382 }; 383 }; 384 385 ptp_timer: ptimer@24e00 { 386 compatible = "fsl,gianfar-ptp-timer"; 387 reg = <0x24e00 0xb0>; 388 }; 389 390 enet0: ethernet@24000 { 391 #address-cells = <1>; 392 #size-cells = <1>; 393 cell-index = <0>; 394 device_type = "network"; 395 model = "eTSEC"; 396 compatible = "gianfar"; 397 reg = <0x24000 0x1000>; 398 ranges = <0x0 0x24000 0x1000>; 399 local-mac-address = [ 00 00 00 00 00 00 ]; 400 interrupts = <29 2 30 2 34 2>; 401 interrupt-parent = <&mpic>; 402 tbi-handle = <&tbi0>; 403 phy-handle = <&phy0>; 404 ptimer-handle = < &ptp_timer >; 405 phy-connection-type = "rgmii-id"; 406 407 mdio@520 { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 compatible = "fsl,gianfar-mdio"; 411 reg = <0x520 0x20>; 412 413 phy0: ethernet-phy@0 { 414 interrupt-parent = <&mpic>; 415 interrupts = <10 1>; 416 reg = <0x0>; 417 }; 418 phy1: ethernet-phy@1 { 419 interrupt-parent = <&mpic>; 420 interrupts = <10 1>; 421 reg = <0x1>; 422 }; 423 phy2: ethernet-phy@2 { 424 interrupt-parent = <&mpic>; 425 interrupts = <10 1>; 426 reg = <0x2>; 427 }; 428 phy3: ethernet-phy@3 { 429 interrupt-parent = <&mpic>; 430 interrupts = <10 1>; 431 reg = <0x3>; 432 }; 433 434 tbi0: tbi-phy@11 { 435 reg = <0x11>; 436 device_type = "tbi-phy"; 437 }; 438 }; 439 }; 440 441 enet1: ethernet@25000 { 442 #address-cells = <1>; 443 #size-cells = <1>; 444 cell-index = <1>; 445 device_type = "network"; 446 model = "eTSEC"; 447 compatible = "gianfar"; 448 reg = <0x25000 0x1000>; 449 ranges = <0x0 0x25000 0x1000>; 450 local-mac-address = [ 00 00 00 00 00 00 ]; 451 interrupts = <35 2 36 2 40 2>; 452 interrupt-parent = <&mpic>; 453 tbi-handle = <&tbi1>; 454 phy-handle = <&phy1>; 455 ptimer-handle = < &ptp_timer >; 456 phy-connection-type = "rgmii-id"; 457 458 mdio@520 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "fsl,gianfar-tbi"; 462 reg = <0x520 0x20>; 463 464 tbi1: tbi-phy@11 { 465 reg = <0x11>; 466 device_type = "tbi-phy"; 467 }; 468 }; 469 }; 470 471 enet2: ethernet@26000 { 472 #address-cells = <1>; 473 #size-cells = <1>; 474 cell-index = <2>; 475 device_type = "network"; 476 model = "eTSEC"; 477 compatible = "gianfar"; 478 reg = <0x26000 0x1000>; 479 ranges = <0x0 0x26000 0x1000>; 480 local-mac-address = [ 00 00 00 00 00 00 ]; 481 interrupts = <31 2 32 2 33 2>; 482 interrupt-parent = <&mpic>; 483 tbi-handle = <&tbi2>; 484 phy-handle = <&phy2>; 485 ptimer-handle = < &ptp_timer >; 486 phy-connection-type = "rgmii-id"; 487 488 mdio@520 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 compatible = "fsl,gianfar-tbi"; 492 reg = <0x520 0x20>; 493 494 tbi2: tbi-phy@11 { 495 reg = <0x11>; 496 device_type = "tbi-phy"; 497 }; 498 }; 499 }; 500 501 enet3: ethernet@27000 { 502 #address-cells = <1>; 503 #size-cells = <1>; 504 cell-index = <3>; 505 device_type = "network"; 506 model = "eTSEC"; 507 compatible = "gianfar"; 508 reg = <0x27000 0x1000>; 509 ranges = <0x0 0x27000 0x1000>; 510 local-mac-address = [ 00 00 00 00 00 00 ]; 511 interrupts = <37 2 38 2 39 2>; 512 interrupt-parent = <&mpic>; 513 tbi-handle = <&tbi3>; 514 phy-handle = <&phy3>; 515 phy-connection-type = "rgmii-id"; 516 517 mdio@520 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "fsl,gianfar-tbi"; 521 reg = <0x520 0x20>; 522 523 tbi3: tbi-phy@11 { 524 reg = <0x11>; 525 device_type = "tbi-phy"; 526 }; 527 }; 528 }; 529 530 serial0: serial@4500 { 531 cell-index = <0>; 532 device_type = "serial"; 533 compatible = "ns16550"; 534 reg = <0x4500 0x100>; 535 clock-frequency = <0>; 536 interrupts = <42 2>; 537 interrupt-parent = <&mpic>; 538 }; 539 540 serial1: serial@4600 { 541 cell-index = <1>; 542 device_type = "serial"; 543 compatible = "ns16550"; 544 reg = <0x4600 0x100>; 545 clock-frequency = <0>; 546 interrupts = <42 2>; 547 interrupt-parent = <&mpic>; 548 }; 549 550 global-utilities@e0000 { //global utilities block 551 compatible = "fsl,mpc8572-guts"; 552 reg = <0xe0000 0x1000>; 553 fsl,has-rstcr; 554 }; 555 556 power@e0070{ 557 compatible = "fsl,mpc8548-pmc"; 558 reg = <0xe0070 0x14>; 559 }; 560 561 timer@41100 { 562 compatible = "fsl,mpic-global-timer"; 563 reg = <0x41100 0x204>; 564 interrupts = <0xf7 0x2>; 565 interrupt-parent = <&mpic>; 566 }; 567 568 msi@41600 { 569 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 570 reg = <0x41600 0x80>; 571 msi-available-ranges = <0 0x100>; 572 interrupts = < 573 0xe0 0 574 0xe1 0 575 0xe2 0 576 0xe3 0 577 0xe4 0 578 0xe5 0 579 0xe6 0 580 0xe7 0>; 581 interrupt-parent = <&mpic>; 582 }; 583 584 crypto@30000 { 585 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 586 "fsl,sec2.1", "fsl,sec2.0"; 587 reg = <0x30000 0x10000>; 588 interrupts = <45 2 58 2>; 589 interrupt-parent = <&mpic>; 590 fsl,num-channels = <4>; 591 fsl,channel-fifo-len = <24>; 592 fsl,exec-units-mask = <0x9fe>; 593 fsl,descriptor-types-mask = <0x3ab0ebf>; 594 }; 595 596 /* PME (pattern-matcher) */ 597 pme@10000 { 598 device_type = "pme"; 599 compatible = "pme8572"; 600 reg = <0x10000 0x5000>; 601 interrupts = <0x39 0x2 0x40 0x2 0x41 0x2 0x42 0x2 0x43 0x2>; 602 interrupt-parent = <&mpic>; 603 }; 604 605 mpic: pic@40000 { 606 interrupt-controller; 607 #address-cells = <0>; 608 #interrupt-cells = <2>; 609 reg = <0x40000 0x40000>; 610 compatible = "chrp,open-pic"; 611 device_type = "open-pic"; 612 }; 613 }; 614 615 pci0: pcie@ffe08000 { 616 compatible = "fsl,mpc8548-pcie"; 617 device_type = "pci"; 618 #interrupt-cells = <1>; 619 #size-cells = <2>; 620 #address-cells = <3>; 621 reg = <0 0xffe08000 0 0x1000>; 622 bus-range = <0 255>; 623 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 624 0x1000000 0x0 0x00000000 0 0xfee20000 0x0 0x00010000>; 625 clock-frequency = <33333333>; 626 interrupt-parent = <&mpic>; 627 interrupts = <24 2>; 628 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 629 interrupt-map = < 630 /* IDSEL 0x11 func 0 - PCI slot 1 */ 631 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 632 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 633 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 634 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 635 636 /* IDSEL 0x11 func 1 - PCI slot 1 */ 637 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 638 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 639 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 640 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 641 642 /* IDSEL 0x11 func 2 - PCI slot 1 */ 643 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 644 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 645 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 646 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 647 648 /* IDSEL 0x11 func 3 - PCI slot 1 */ 649 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 650 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 651 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 652 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 653 654 /* IDSEL 0x11 func 4 - PCI slot 1 */ 655 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 656 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 657 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 658 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 659 660 /* IDSEL 0x11 func 5 - PCI slot 1 */ 661 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 662 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 663 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 664 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 665 666 /* IDSEL 0x11 func 6 - PCI slot 1 */ 667 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 668 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 669 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 670 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 671 672 /* IDSEL 0x11 func 7 - PCI slot 1 */ 673 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 674 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 675 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 676 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 677 678 /* IDSEL 0x12 func 0 - PCI slot 2 */ 679 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 680 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 681 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 682 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 683 684 /* IDSEL 0x12 func 1 - PCI slot 2 */ 685 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 686 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 687 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 688 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 689 690 /* IDSEL 0x12 func 2 - PCI slot 2 */ 691 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 692 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 693 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 694 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 695 696 /* IDSEL 0x12 func 3 - PCI slot 2 */ 697 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 698 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 699 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 700 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 701 702 /* IDSEL 0x12 func 4 - PCI slot 2 */ 703 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 704 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 705 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 706 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 707 708 /* IDSEL 0x12 func 5 - PCI slot 2 */ 709 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 710 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 711 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 712 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 713 714 /* IDSEL 0x12 func 6 - PCI slot 2 */ 715 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 716 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 717 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 718 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 719 720 /* IDSEL 0x12 func 7 - PCI slot 2 */ 721 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 722 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 723 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 724 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 725 726 // IDSEL 0x1c USB 727 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 728 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 729 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 730 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 731 732 // IDSEL 0x1d Audio 733 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 734 735 // IDSEL 0x1e Legacy 736 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 737 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 738 739 // IDSEL 0x1f IDE/SATA 740 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 741 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 742 743 >; 744 745 pcie@0 { 746 reg = <0x0 0x0 0x0 0x0 0x0>; 747 #size-cells = <2>; 748 #address-cells = <3>; 749 device_type = "pci"; 750 ranges = <0x2000000 0x0 0xa0000000 751 0x2000000 0x0 0xa0000000 752 0x0 0x10000000 753 754 0x1000000 0x0 0x0 755 0x1000000 0x0 0x0 756 0x0 0x10000>; 757 uli1575@0 { 758 reg = <0x0 0x0 0x0 0x0 0x0>; 759 #size-cells = <2>; 760 #address-cells = <3>; 761 ranges = <0x2000000 0x0 0xa0000000 762 0x2000000 0x0 0xa0000000 763 0x0 0x10000000 764 765 0x1000000 0x0 0x0 766 0x1000000 0x0 0x0 767 0x0 0x10000>; 768 isa@1e { 769 device_type = "isa"; 770 #interrupt-cells = <2>; 771 #size-cells = <1>; 772 #address-cells = <2>; 773 reg = <0xf000 0x0 0x0 0x0 0x0>; 774 ranges = <0x1 0x0 0x1000000 0x0 0x0 775 0x1000>; 776 interrupt-parent = <&i8259>; 777 778 i8259: interrupt-controller@20 { 779 reg = <0x1 0x20 0x2 780 0x1 0xa0 0x2 781 0x1 0x4d0 0x2>; 782 interrupt-controller; 783 device_type = "interrupt-controller"; 784 #address-cells = <0>; 785 #interrupt-cells = <2>; 786 compatible = "chrp,iic"; 787 interrupts = <9 2>; 788 interrupt-parent = <&mpic>; 789 }; 790 791 i8042@60 { 792 #size-cells = <0>; 793 #address-cells = <1>; 794 reg = <0x1 0x60 0x1 0x1 0x64 0x1>; 795 interrupts = <1 3 12 3>; 796 interrupt-parent = 797 <&i8259>; 798 799 keyboard@0 { 800 reg = <0x0>; 801 compatible = "pnpPNP,303"; 802 }; 803 804 mouse@1 { 805 reg = <0x1>; 806 compatible = "pnpPNP,f03"; 807 }; 808 }; 809 810 rtc@70 { 811 compatible = "pnpPNP,b00"; 812 reg = <0x1 0x70 0x2>; 813 }; 814 815 gpio@400 { 816 reg = <0x1 0x400 0x80>; 817 }; 818 }; 819 }; 820 }; 821 822 }; 823 824 pci1: pcie@ffe09000 { 825 compatible = "fsl,mpc8548-pcie"; 826 device_type = "pci"; 827 #interrupt-cells = <1>; 828 #size-cells = <2>; 829 #address-cells = <3>; 830 reg = <0 0xffe09000 0 0x1000>; 831 bus-range = <0 255>; 832 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 833 0x1000000 0x0 0x00000000 0 0xfee10000 0x0 0x00010000>; 834 clock-frequency = <33333333>; 835 interrupt-parent = <&mpic>; 836 interrupts = <25 2>; 837 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 838 interrupt-map = < 839 /* IDSEL 0x0 */ 840 0000 0x0 0x0 0x1 &mpic 0x4 0x1 841 0000 0x0 0x0 0x2 &mpic 0x5 0x1 842 0000 0x0 0x0 0x3 &mpic 0x6 0x1 843 0000 0x0 0x0 0x4 &mpic 0x7 0x1 844 >; 845 pcie@0 { 846 reg = <0x0 0x0 0x0 0x0 0x0>; 847 #size-cells = <2>; 848 #address-cells = <3>; 849 device_type = "pci"; 850 ranges = <0x2000000 0x0 0x90000000 851 0x2000000 0x0 0x90000000 852 0x0 0x10000000 853 854 0x1000000 0x0 0x0 855 0x1000000 0x0 0x0 856 0x0 0x10000>; 857 }; 858 }; 859 860 pci2: pcie@ffe0a000 { 861 compatible = "fsl,mpc8548-pcie"; 862 device_type = "pci"; 863 #interrupt-cells = <1>; 864 #size-cells = <2>; 865 #address-cells = <3>; 866 reg = <0 0xffe0a000 0 0x1000>; 867 bus-range = <0 255>; 868 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 869 0x1000000 0x0 0x00000000 0 0xfee00000 0x0 0x00010000>; 870 clock-frequency = <33333333>; 871 interrupt-parent = <&mpic>; 872 interrupts = <26 2>; 873 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 874 interrupt-map = < 875 /* IDSEL 0x0 */ 876 0000 0x0 0x0 0x1 &mpic 0x0 0x1 877 0000 0x0 0x0 0x2 &mpic 0x1 0x1 878 0000 0x0 0x0 0x3 &mpic 0x2 0x1 879 0000 0x0 0x0 0x4 &mpic 0x3 0x1 880 >; 881 pcie@0 { 882 reg = <0x0 0x0 0x0 0x0 0x0>; 883 #size-cells = <2>; 884 #address-cells = <3>; 885 device_type = "pci"; 886 ranges = <0x2000000 0x0 0x80000000 887 0x2000000 0x0 0x80000000 888 0x0 0x10000000 889 890 0x1000000 0x0 0x0 891 0x1000000 0x0 0x0 892 0x0 0x10000>; 893 }; 894 }; 895 };
Cache object: cd1bb6f1f4a61211124fbb9db6e88ecd
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