1 /*
2 * P2041 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 /* $FreeBSD: releng/12.0/sys/dts/powerpc/p2041si.dtsi 325826 2017-11-14 21:03:57Z imp $ */
35
36 /dts-v1/;
37
38 / {
39 compatible = "fsl,P2041";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46 dcsr = &dcsr;
47
48 ethernet0 = &enet0;
49 ethernet1 = &enet1;
50 ethernet2 = &enet2;
51 ethernet3 = &enet3;
52 ethernet4 = &enet4;
53 ethernet5 = &enet5;
54 serial0 = &serial0;
55 serial1 = &serial1;
56 serial2 = &serial2;
57 serial3 = &serial3;
58 pci0 = &pci0;
59 pci1 = &pci1;
60 pci2 = &pci2;
61 usb0 = &usb0;
62 usb1 = &usb1;
63 dma0 = &dma0;
64 dma1 = &dma1;
65 bman = &bman;
66 qman = &qman;
67 pme = &pme;
68 rman = &rman;
69 sdhc = &sdhc;
70 msi0 = &msi0;
71 msi1 = &msi1;
72 msi2 = &msi2;
73
74 crypto = &crypto;
75 sec_jr0 = &sec_jr0;
76 sec_jr1 = &sec_jr1;
77 sec_jr2 = &sec_jr2;
78 sec_jr3 = &sec_jr3;
79 rtic_a = &rtic_a;
80 rtic_b = &rtic_b;
81 rtic_c = &rtic_c;
82 rtic_d = &rtic_d;
83 sec_mon = &sec_mon;
84
85 fman0 = &fman0;
86 fman0_oh0 = &fman0_oh0;
87 fman0_oh1 = &fman0_oh1;
88 fman0_oh2 = &fman0_oh2;
89 fman0_oh3 = &fman0_oh3;
90 fman0_oh4 = &fman0_oh4;
91 fman0_oh5 = &fman0_oh5;
92 fman0_oh6 = &fman0_oh6;
93 fman0_rx0 = &fman0_rx0;
94 fman0_rx1 = &fman0_rx1;
95 fman0_rx2 = &fman0_rx2;
96 fman0_rx3 = &fman0_rx3;
97 fman0_rx4 = &fman0_rx4;
98 fman0_rx5 = &fman0_rx5;
99 };
100
101 cpus {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 cpu0: PowerPC,e500mc@0 {
106 device_type = "cpu";
107 reg = <0>;
108 bus-frequency = <749999996>;
109 next-level-cache = <&L2_0>;
110 L2_0: l2-cache {
111 next-level-cache = <&cpc>;
112 };
113 };
114 cpu1: PowerPC,e500mc@1 {
115 device_type = "cpu";
116 reg = <1>;
117 next-level-cache = <&L2_1>;
118 L2_1: l2-cache {
119 next-level-cache = <&cpc>;
120 };
121 };
122 cpu2: PowerPC,e500mc@2 {
123 device_type = "cpu";
124 reg = <2>;
125 next-level-cache = <&L2_2>;
126 L2_2: l2-cache {
127 next-level-cache = <&cpc>;
128 };
129 };
130 cpu3: PowerPC,e500mc@3 {
131 device_type = "cpu";
132 reg = <3>;
133 next-level-cache = <&L2_3>;
134 L2_3: l2-cache {
135 next-level-cache = <&cpc>;
136 };
137 };
138 };
139
140 dcsr: dcsr@f00000000 {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "fsl,dcsr", "simple-bus";
144
145 dcsr-epu@0 {
146 compatible = "fsl,dcsr-epu";
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
150 interrupt-parent = <&mpic>;
151 reg = <0x0 0x1000>;
152 };
153 dcsr-npc {
154 compatible = "fsl,dcsr-npc";
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
156 };
157 dcsr-nxc@2000 {
158 compatible = "fsl,dcsr-nxc";
159 reg = <0x2000 0x1000>;
160 };
161 dcsr-corenet {
162 compatible = "fsl,dcsr-corenet";
163 reg = <0x8000 0x1000 0xB0000 0x1000>;
164 };
165 dcsr-dpaa@9000 {
166 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
167 reg = <0x9000 0x1000>;
168 };
169 dcsr-ocn@11000 {
170 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
171 reg = <0x11000 0x1000>;
172 };
173 dcsr-ddr@12000 {
174 compatible = "fsl,dcsr-ddr";
175 dev-handle = <&ddr>;
176 reg = <0x12000 0x1000>;
177 };
178 dcsr-nal@18000 {
179 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
180 reg = <0x18000 0x1000>;
181 };
182 dcsr-rcpm@22000 {
183 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
184 reg = <0x22000 0x1000>;
185 };
186 dcsr-cpu-sb-proxy@40000 {
187 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
188 cpu-handle = <&cpu0>;
189 reg = <0x40000 0x1000>;
190 };
191 dcsr-cpu-sb-proxy@41000 {
192 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
193 cpu-handle = <&cpu1>;
194 reg = <0x41000 0x1000>;
195 };
196 dcsr-cpu-sb-proxy@42000 {
197 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
198 cpu-handle = <&cpu2>;
199 reg = <0x42000 0x1000>;
200 };
201 dcsr-cpu-sb-proxy@43000 {
202 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
203 cpu-handle = <&cpu3>;
204 reg = <0x43000 0x1000>;
205 };
206 };
207
208 bman-portals@ff4000000 {
209 #address-cells = <0x1>;
210 #size-cells = <0x1>;
211 compatible = "fsl,bman-portals";
212 ranges = <0x0 0xf 0xfde00000 0x200000>;
213 bman-portal@0 {
214 cell-index = <0x0>;
215 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
216 reg = <0x0 0x4000 0x100000 0x1000>;
217 interrupts = <105 2 0 0>;
218 };
219 bman-portal@4000 {
220 cell-index = <0x1>;
221 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
222 reg = <0x4000 0x4000 0x101000 0x1000>;
223 interrupts = <107 2 0 0>;
224 };
225 bman-portal@8000 {
226 cell-index = <2>;
227 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
228 reg = <0x8000 0x4000 0x102000 0x1000>;
229 interrupts = <109 2 0 0>;
230 };
231 bman-portal@c000 {
232 cell-index = <0x3>;
233 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
234 reg = <0xc000 0x4000 0x103000 0x1000>;
235 interrupts = <111 2 0 0>;
236 };
237 bman-portal@10000 {
238 cell-index = <0x4>;
239 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
240 reg = <0x10000 0x4000 0x104000 0x1000>;
241 interrupts = <113 2 0 0>;
242 };
243 bman-portal@14000 {
244 cell-index = <0x5>;
245 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
246 reg = <0x14000 0x4000 0x105000 0x1000>;
247 interrupts = <115 2 0 0>;
248 };
249 bman-portal@18000 {
250 cell-index = <0x6>;
251 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
252 reg = <0x18000 0x4000 0x106000 0x1000>;
253 interrupts = <117 2 0 0>;
254 };
255 bman-portal@1c000 {
256 cell-index = <0x7>;
257 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
258 reg = <0x1c000 0x4000 0x107000 0x1000>;
259 interrupts = <119 2 0 0>;
260 };
261 bman-portal@20000 {
262 cell-index = <0x8>;
263 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
264 reg = <0x20000 0x4000 0x108000 0x1000>;
265 interrupts = <121 2 0 0>;
266 };
267 bman-portal@24000 {
268 cell-index = <0x9>;
269 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
270 reg = <0x24000 0x4000 0x109000 0x1000>;
271 interrupts = <123 2 0 0>;
272 };
273
274 buffer-pool@0 {
275 compatible = "fsl,p2041-bpool", "fsl,bpool";
276 fsl,bpid = <0>;
277 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
278 };
279 };
280
281 qman-portals@ff4200000 {
282 #address-cells = <0x1>;
283 #size-cells = <0x1>;
284 compatible = "fsl,qman-portals";
285 ranges = <0x0 0xf 0xfdc00000 0x200000>;
286 qportal0: qman-portal@0 {
287 cell-index = <0x0>;
288 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
289 reg = <0x0 0x4000 0x100000 0x1000>;
290 interrupts = <104 0x2 0 0>;
291 fsl,qman-channel-id = <0x0>;
292 };
293
294 qportal1: qman-portal@4000 {
295 cell-index = <0x1>;
296 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
297 reg = <0x4000 0x4000 0x101000 0x1000>;
298 interrupts = <106 0x2 0 0>;
299 fsl,qman-channel-id = <0x1>;
300 };
301
302 qportal2: qman-portal@8000 {
303 cell-index = <0x2>;
304 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
305 reg = <0x8000 0x4000 0x102000 0x1000>;
306 interrupts = <108 0x2 0 0>;
307 fsl,qman-channel-id = <0x2>;
308 };
309
310 qportal3: qman-portal@c000 {
311 cell-index = <0x3>;
312 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
313 reg = <0xc000 0x4000 0x103000 0x1000>;
314 interrupts = <110 0x2 0 0>;
315 fsl,qman-channel-id = <0x3>;
316 };
317
318 qportal4: qman-portal@10000 {
319 cell-index = <0x4>;
320 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
321 reg = <0x10000 0x4000 0x104000 0x1000>;
322 interrupts = <112 0x2 0 0>;
323 fsl,qman-channel-id = <0x4>;
324 };
325
326 qportal5: qman-portal@14000 {
327 cell-index = <0x5>;
328 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
329 reg = <0x14000 0x4000 0x105000 0x1000>;
330 interrupts = <114 0x2 0 0>;
331 fsl,qman-channel-id = <0x5>;
332 };
333
334 qportal6: qman-portal@18000 {
335 cell-index = <0x6>;
336 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
337 reg = <0x18000 0x4000 0x106000 0x1000>;
338 interrupts = <116 0x2 0 0>;
339 fsl,qman-channel-id = <0x6>;
340 };
341
342 qportal7: qman-portal@1c000 {
343 cell-index = <0x7>;
344 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
345 reg = <0x1c000 0x4000 0x107000 0x1000>;
346 interrupts = <118 0x2 0 0>;
347 fsl,qman-channel-id = <0x7>;
348 };
349
350 qportal8: qman-portal@20000 {
351 cell-index = <0x8>;
352 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
353 reg = <0x20000 0x4000 0x108000 0x1000>;
354 interrupts = <120 0x2 0 0>;
355 fsl,qman-channel-id = <0x8>;
356 };
357
358 qportal9: qman-portal@24000 {
359 cell-index = <0x9>;
360 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
361 reg = <0x24000 0x4000 0x109000 0x1000>;
362 interrupts = <122 0x2 0 0>;
363 fsl,qman-channel-id = <0x9>;
364 };
365
366 qpool1: qman-pool@1 {
367 cell-index = <1>;
368 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
369 fsl,qman-channel-id = <0x21>;
370 };
371
372 qpool2: qman-pool@2 {
373 cell-index = <2>;
374 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
375 fsl,qman-channel-id = <0x22>;
376 };
377
378 qpool3: qman-pool@3 {
379 cell-index = <3>;
380 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
381 fsl,qman-channel-id = <0x23>;
382 };
383
384 qpool4: qman-pool@4 {
385 cell-index = <4>;
386 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
387 fsl,qman-channel-id = <0x24>;
388 };
389
390 qpool5: qman-pool@5 {
391 cell-index = <5>;
392 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
393 fsl,qman-channel-id = <0x25>;
394 };
395
396 qpool6: qman-pool@6 {
397 cell-index = <6>;
398 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
399 fsl,qman-channel-id = <0x26>;
400 };
401
402 qpool7: qman-pool@7 {
403 cell-index = <7>;
404 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
405 fsl,qman-channel-id = <0x27>;
406 };
407
408 qpool8: qman-pool@8 {
409 cell-index = <8>;
410 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
411 fsl,qman-channel-id = <0x28>;
412 };
413
414 qpool9: qman-pool@9 {
415 cell-index = <9>;
416 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
417 fsl,qman-channel-id = <0x29>;
418 };
419
420 qpool10: qman-pool@10 {
421 cell-index = <10>;
422 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
423 fsl,qman-channel-id = <0x2a>;
424 };
425
426 qpool11: qman-pool@11 {
427 cell-index = <11>;
428 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
429 fsl,qman-channel-id = <0x2b>;
430 };
431
432 qpool12: qman-pool@12 {
433 cell-index = <12>;
434 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
435 fsl,qman-channel-id = <0x2c>;
436 };
437
438 qpool13: qman-pool@13 {
439 cell-index = <13>;
440 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
441 fsl,qman-channel-id = <0x2d>;
442 };
443
444 qpool14: qman-pool@14 {
445 cell-index = <14>;
446 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
447 fsl,qman-channel-id = <0x2e>;
448 };
449
450 qpool15: qman-pool@15 {
451 cell-index = <15>;
452 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
453 fsl,qman-channel-id = <0x2f>;
454 };
455 };
456
457 soc: soc@ffe000000 {
458 #address-cells = <1>;
459 #size-cells = <1>;
460 device_type = "soc";
461 compatible = "simple-bus";
462
463 bus-frequency = <0>; // Filled out by kernel.
464
465 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
466 reg = <0xf 0xfe000000 0 0x00001000>;
467
468 soc-sram-error {
469 compatible = "fsl,soc-sram-error";
470 interrupts = <16 2 1 29>;
471 };
472
473 corenet-law@0 {
474 compatible = "fsl,corenet-law";
475 reg = <0x0 0x1000>;
476 fsl,num-laws = <32>;
477 };
478
479 ddr: memory-controller@8000 {
480 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
481 reg = <0x8000 0x1000>;
482 interrupts = <16 2 1 23>;
483 };
484
485 cpc: l3-cache-controller@10000 {
486 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
487 reg = <0x10000 0x1000>;
488 interrupts = <16 2 1 27>;
489 };
490
491 corenet-cf@18000 {
492 compatible = "fsl,corenet-cf";
493 reg = <0x18000 0x1000>;
494 interrupts = <16 2 1 31>;
495 fsl,ccf-num-csdids = <32>;
496 fsl,ccf-num-snoopids = <32>;
497 };
498
499 iommu@20000 {
500 compatible = "fsl,pamu-v1.0", "fsl,pamu";
501 reg = <0x20000 0x4000>;
502 interrupts = <
503 24 2 0 0
504 16 2 1 30>;
505 };
506
507 mpic: pic@40000 {
508 clock-frequency = <0>;
509 interrupt-controller;
510 #address-cells = <0>;
511 #interrupt-cells = <4>;
512 reg = <0x40000 0x40000>;
513 compatible = "fsl,mpic", "chrp,open-pic";
514 device_type = "open-pic";
515 };
516
517 msi0: msi@41600 {
518 compatible = "fsl,mpic-msi";
519 reg = <0x41600 0x200>;
520 msi-available-ranges = <0 0x100>;
521 interrupts = <
522 0xe0 0 0 0
523 0xe1 0 0 0
524 0xe2 0 0 0
525 0xe3 0 0 0
526 0xe4 0 0 0
527 0xe5 0 0 0
528 0xe6 0 0 0
529 0xe7 0 0 0>;
530 };
531
532 msi1: msi@41800 {
533 compatible = "fsl,mpic-msi";
534 reg = <0x41800 0x200>;
535 msi-available-ranges = <0 0x100>;
536 interrupts = <
537 0xe8 0 0 0
538 0xe9 0 0 0
539 0xea 0 0 0
540 0xeb 0 0 0
541 0xec 0 0 0
542 0xed 0 0 0
543 0xee 0 0 0
544 0xef 0 0 0>;
545 };
546
547 msi2: msi@41a00 {
548 compatible = "fsl,mpic-msi";
549 reg = <0x41a00 0x200>;
550 msi-available-ranges = <0 0x100>;
551 interrupts = <
552 0xf0 0 0 0
553 0xf1 0 0 0
554 0xf2 0 0 0
555 0xf3 0 0 0
556 0xf4 0 0 0
557 0xf5 0 0 0
558 0xf6 0 0 0
559 0xf7 0 0 0>;
560 };
561
562 guts: global-utilities@e0000 {
563 compatible = "fsl,qoriq-device-config-1.0";
564 reg = <0xe0000 0xe00>;
565 fsl,has-rstcr;
566 #sleep-cells = <1>;
567 fsl,liodn-bits = <12>;
568 };
569
570 pins: global-utilities@e0e00 {
571 compatible = "fsl,qoriq-pin-control-1.0";
572 reg = <0xe0e00 0x200>;
573 #sleep-cells = <2>;
574 };
575
576 clockgen: global-utilities@e1000 {
577 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
578 reg = <0xe1000 0x1000>;
579 clock-frequency = <0>;
580 };
581
582 rcpm: global-utilities@e2000 {
583 compatible = "fsl,qoriq-rcpm-1.0";
584 reg = <0xe2000 0x1000>;
585 #sleep-cells = <1>;
586 };
587
588 sfp: sfp@e8000 {
589 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
590 reg = <0xe8000 0x1000>;
591 };
592
593 serdes: serdes@ea000 {
594 compatible = "fsl,p2041-serdes";
595 reg = <0xea000 0x1000>;
596 };
597
598 dma0: dma@100300 {
599 #address-cells = <1>;
600 #size-cells = <1>;
601 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
602 reg = <0x100300 0x4>;
603 ranges = <0x0 0x100100 0x200>;
604 cell-index = <0>;
605 dma-channel@0 {
606 compatible = "fsl,p2041-dma-channel",
607 "fsl,eloplus-dma-channel";
608 reg = <0x0 0x80>;
609 cell-index = <0>;
610 interrupts = <28 2 0 0>;
611 };
612 dma-channel@80 {
613 compatible = "fsl,p2041-dma-channel",
614 "fsl,eloplus-dma-channel";
615 reg = <0x80 0x80>;
616 cell-index = <1>;
617 interrupts = <29 2 0 0>;
618 };
619 dma-channel@100 {
620 compatible = "fsl,p2041-dma-channel",
621 "fsl,eloplus-dma-channel";
622 reg = <0x100 0x80>;
623 cell-index = <2>;
624 interrupts = <30 2 0 0>;
625 };
626 dma-channel@180 {
627 compatible = "fsl,p2041-dma-channel",
628 "fsl,eloplus-dma-channel";
629 reg = <0x180 0x80>;
630 cell-index = <3>;
631 interrupts = <31 2 0 0>;
632 };
633 };
634
635 dma1: dma@101300 {
636 #address-cells = <1>;
637 #size-cells = <1>;
638 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
639 reg = <0x101300 0x4>;
640 ranges = <0x0 0x101100 0x200>;
641 cell-index = <1>;
642 dma-channel@0 {
643 compatible = "fsl,p2041-dma-channel",
644 "fsl,eloplus-dma-channel";
645 reg = <0x0 0x80>;
646 cell-index = <0>;
647 interrupts = <32 2 0 0>;
648 };
649 dma-channel@80 {
650 compatible = "fsl,p2041-dma-channel",
651 "fsl,eloplus-dma-channel";
652 reg = <0x80 0x80>;
653 cell-index = <1>;
654 interrupts = <33 2 0 0>;
655 };
656 dma-channel@100 {
657 compatible = "fsl,p2041-dma-channel",
658 "fsl,eloplus-dma-channel";
659 reg = <0x100 0x80>;
660 cell-index = <2>;
661 interrupts = <34 2 0 0>;
662 };
663 dma-channel@180 {
664 compatible = "fsl,p2041-dma-channel",
665 "fsl,eloplus-dma-channel";
666 reg = <0x180 0x80>;
667 cell-index = <3>;
668 interrupts = <35 2 0 0>;
669 };
670 };
671
672 spi@110000 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
676 reg = <0x110000 0x1000>;
677 interrupts = <53 0x2 0 0>;
678 fsl,espi-num-chipselects = <4>;
679 };
680
681 sdhc: sdhc@114000 {
682 compatible = "fsl,p2041-esdhc", "fsl,esdhc";
683 reg = <0x114000 0x1000>;
684 interrupts = <48 2 0 0>;
685 sdhci,auto-cmd12;
686 clock-frequency = <0>;
687 };
688
689 i2c@118000 {
690 #address-cells = <1>;
691 #size-cells = <0>;
692 cell-index = <0>;
693 compatible = "fsl-i2c";
694 reg = <0x118000 0x100>;
695 interrupts = <38 2 0 0>;
696 dfsrr;
697 };
698
699 i2c@118100 {
700 #address-cells = <1>;
701 #size-cells = <0>;
702 cell-index = <1>;
703 compatible = "fsl-i2c";
704 reg = <0x118100 0x100>;
705 interrupts = <38 2 0 0>;
706 dfsrr;
707 };
708
709 i2c@119000 {
710 #address-cells = <1>;
711 #size-cells = <0>;
712 cell-index = <2>;
713 compatible = "fsl-i2c";
714 reg = <0x119000 0x100>;
715 interrupts = <39 2 0 0>;
716 dfsrr;
717 };
718
719 i2c@119100 {
720 #address-cells = <1>;
721 #size-cells = <0>;
722 cell-index = <3>;
723 compatible = "fsl-i2c";
724 reg = <0x119100 0x100>;
725 interrupts = <39 2 0 0>;
726 dfsrr;
727 };
728
729 serial0: serial@11c500 {
730 cell-index = <0>;
731 device_type = "serial";
732 compatible = "ns16550";
733 reg = <0x11c500 0x100>;
734 clock-frequency = <0>;
735 interrupts = <36 2 0 0>;
736 };
737
738 serial1: serial@11c600 {
739 cell-index = <1>;
740 device_type = "serial";
741 compatible = "ns16550";
742 reg = <0x11c600 0x100>;
743 clock-frequency = <0>;
744 interrupts = <36 2 0 0>;
745 };
746
747 serial2: serial@11d500 {
748 cell-index = <2>;
749 device_type = "serial";
750 compatible = "ns16550";
751 reg = <0x11d500 0x100>;
752 clock-frequency = <0>;
753 interrupts = <37 2 0 0>;
754 };
755
756 serial3: serial@11d600 {
757 cell-index = <3>;
758 device_type = "serial";
759 compatible = "ns16550";
760 reg = <0x11d600 0x100>;
761 clock-frequency = <0>;
762 interrupts = <37 2 0 0>;
763 };
764
765 gpio0: gpio@130000 {
766 compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
767 reg = <0x130000 0x1000>;
768 interrupts = <55 2 0 0>;
769 #gpio-cells = <2>;
770 gpio-controller;
771 };
772
773 rman: rman@1e0000 {
774 compatible = "fsl,rman";
775 #address-cells = <1>;
776 #size-cells = <1>;
777 ranges = <0x0 0x1e0000 0x20000>;
778 reg = <0x1e0000 0x20000>;
779 interrupts = <16 2 1 11>; /* err_irq */
780 fsl,qman-channels-id = <0x62 0x63>;
781
782 inbound-block@0 {
783 compatible = "fsl,rman-inbound-block";
784 reg = <0x0 0x800>;
785 };
786 global-cfg@b00 {
787 compatible = "fsl,rman-global-cfg";
788 reg = <0xb00 0x500>;
789 };
790 inbound-block@1000 {
791 compatible = "fsl,rman-inbound-block";
792 reg = <0x1000 0x800>;
793 };
794 inbound-block@2000 {
795 compatible = "fsl,rman-inbound-block";
796 reg = <0x2000 0x800>;
797 };
798 inbound-block@3000 {
799 compatible = "fsl,rman-inbound-block";
800 reg = <0x3000 0x800>;
801 };
802 };
803
804 usb0: usb@210000 {
805 compatible = "fsl,p2041-usb2-mph",
806 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
807 reg = <0x210000 0x1000>;
808 #address-cells = <1>;
809 #size-cells = <0>;
810 interrupts = <44 0x2 0 0>;
811 phy_type = "utmi";
812 port0;
813 };
814
815 usb1: usb@211000 {
816 compatible = "fsl,p2041-usb2-dr",
817 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
818 reg = <0x211000 0x1000>;
819 #address-cells = <1>;
820 #size-cells = <0>;
821 interrupts = <45 0x2 0 0>;
822 phy_type = "utmi";
823 };
824
825 sata@220000 {
826 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
827 reg = <0x220000 0x1000>;
828 interrupts = <68 0x2 0 0>;
829 };
830
831 sata@221000 {
832 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
833 reg = <0x221000 0x1000>;
834 interrupts = <69 0x2 0 0>;
835 };
836
837 crypto: crypto@300000 {
838 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
839 #address-cells = <1>;
840 #size-cells = <1>;
841 reg = <0x300000 0x10000>;
842 ranges = <0 0x300000 0x10000>;
843 interrupts = <92 2 0 0>;
844
845 sec_jr0: jr@1000 {
846 compatible = "fsl,sec-v4.2-job-ring",
847 "fsl,sec-v4.0-job-ring";
848 reg = <0x1000 0x1000>;
849 interrupts = <88 2 0 0>;
850 };
851
852 sec_jr1: jr@2000 {
853 compatible = "fsl,sec-v4.2-job-ring",
854 "fsl,sec-v4.0-job-ring";
855 reg = <0x2000 0x1000>;
856 interrupts = <89 2 0 0>;
857 };
858
859 sec_jr2: jr@3000 {
860 compatible = "fsl,sec-v4.2-job-ring",
861 "fsl,sec-v4.0-job-ring";
862 reg = <0x3000 0x1000>;
863 interrupts = <90 2 0 0>;
864 };
865
866 sec_jr3: jr@4000 {
867 compatible = "fsl,sec-v4.2-job-ring",
868 "fsl,sec-v4.0-job-ring";
869 reg = <0x4000 0x1000>;
870 interrupts = <91 2 0 0>;
871 };
872
873 rtic@6000 {
874 compatible = "fsl,sec-v4.2-rtic",
875 "fsl,sec-v4.0-rtic";
876 #address-cells = <1>;
877 #size-cells = <1>;
878 reg = <0x6000 0x100>;
879 ranges = <0x0 0x6100 0xe00>;
880
881 rtic_a: rtic-a@0 {
882 compatible = "fsl,sec-v4.2-rtic-memory",
883 "fsl,sec-v4.0-rtic-memory";
884 reg = <0x00 0x20 0x100 0x80>;
885 };
886
887 rtic_b: rtic-b@20 {
888 compatible = "fsl,sec-v4.2-rtic-memory",
889 "fsl,sec-v4.0-rtic-memory";
890 reg = <0x20 0x20 0x200 0x80>;
891 };
892
893 rtic_c: rtic-c@40 {
894 compatible = "fsl,sec-v4.2-rtic-memory",
895 "fsl,sec-v4.0-rtic-memory";
896 reg = <0x40 0x20 0x300 0x80>;
897 };
898
899 rtic_d: rtic-d@60 {
900 compatible = "fsl,sec-v4.2-rtic-memory",
901 "fsl,sec-v4.0-rtic-memory";
902 reg = <0x60 0x20 0x500 0x80>;
903 };
904 };
905 };
906
907 sec_mon: sec_mon@314000 {
908 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
909 reg = <0x314000 0x1000>;
910 interrupts = <93 2 0 0>;
911 };
912
913 pme: pme@316000 {
914 compatible = "fsl,pme";
915 reg = <0x316000 0x10000>;
916 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
917 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
918 interrupts = <16 2 1 5>;
919 };
920
921 qman: qman@318000 {
922 compatible = "fsl,p2041-qman", "fsl,qman";
923 reg = <0x318000 0x1000>;
924 interrupts = <16 2 1 3>;
925 /* Commented out, use default allocation */
926 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
927 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
928 };
929
930 bman: bman@31a000 {
931 compatible = "fsl,p2041-bman", "fsl,bman";
932 reg = <0x31a000 0x1000>;
933 interrupts = <16 2 1 2>;
934 /* Same as "fsl,qman-*, use default allocation */
935 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
936 };
937
938 fman0: fman@400000 {
939 #address-cells = <1>;
940 #size-cells = <1>;
941 cell-index = <0>;
942 compatible = "fsl,p2041-fman", "fsl,fman", "simple-bus";
943 ranges = <0 0x400000 0x100000>;
944 reg = <0x400000 0x100000>;
945 clock-frequency = <0>;
946 interrupts = <
947 96 2 0 0
948 16 2 1 1>;
949
950 cc@0 {
951 compatible = "fsl,p2041-fman-cc", "fsl,fman-cc";
952 };
953
954 parser@c7000 {
955 compatible = "fsl,p2041-fman-parser", "fsl,fman-parser";
956 reg = <0xc7000 0x1000>;
957 };
958
959 keygen@c1000 {
960 compatible = "fsl,p2041-fman-keygen", "fsl,fman-keygen";
961 reg = <0xc1000 0x1000>;
962 };
963
964 policer@c0000 {
965 compatible = "fsl,p2041-fman-policer", "fsl,fman-policer";
966 reg = <0xc0000 0x1000>;
967 };
968
969 muram@0 {
970 compatible = "fsl,p2041-fman-muram", "fsl,fman-muram";
971 reg = <0x0 0x28000>;
972 };
973
974 bmi@80000 {
975 compatible = "fsl,p2041-fman-bmi", "fsl,fman-bmi";
976 reg = <0x80000 0x400>;
977 };
978
979 qmi@80400 {
980 compatible = "fsl,p2041-fman-qmi", "fsl,fman-qmi";
981 reg = <0x80400 0x400>;
982 };
983
984 fman0_rx0: port@88000 {
985 cell-index = <0>;
986 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx";
987 reg = <0x88000 0x1000>;
988 };
989 fman0_rx1: port@89000 {
990 cell-index = <1>;
991 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx";
992 reg = <0x89000 0x1000>;
993 };
994 fman0_rx2: port@8a000 {
995 cell-index = <2>;
996 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx";
997 reg = <0x8a000 0x1000>;
998 };
999 fman0_rx3: port@8b000 {
1000 cell-index = <3>;
1001 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx";
1002 reg = <0x8b000 0x1000>;
1003 };
1004 fman0_rx4: port@8c000 {
1005 cell-index = <4>;
1006 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx";
1007 reg = <0x8c000 0x1000>;
1008 };
1009 fman0_rx5: port@90000 {
1010 cell-index = <0>;
1011 compatible = "fsl,p2041-fman-port-10g-rx", "fsl,fman-port-10g-rx";
1012 reg = <0x90000 0x1000>;
1013 };
1014
1015 fman0_tx5: port@b0000 {
1016 cell-index = <0>;
1017 compatible = "fsl,p2041-fman-port-10g-tx", "fsl,fman-port-10g-tx";
1018 reg = <0xb0000 0x1000>;
1019 fsl,qman-channel-id = <0x40>;
1020 };
1021 fman0_tx0: port@a8000 {
1022 cell-index = <0>;
1023 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx";
1024 reg = <0xa8000 0x1000>;
1025 fsl,qman-channel-id = <0x41>;
1026 };
1027 fman0_tx1: port@a9000 {
1028 cell-index = <1>;
1029 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx";
1030 reg = <0xa9000 0x1000>;
1031 fsl,qman-channel-id = <0x42>;
1032 };
1033 fman0_tx2: port@aa000 {
1034 cell-index = <2>;
1035 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx";
1036 reg = <0xaa000 0x1000>;
1037 fsl,qman-channel-id = <0x43>;
1038 };
1039 fman0_tx3: port@ab000 {
1040 cell-index = <3>;
1041 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx";
1042 reg = <0xab000 0x1000>;
1043 fsl,qman-channel-id = <0x44>;
1044 };
1045 fman0_tx4: port@ac000 {
1046 cell-index = <4>;
1047 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx";
1048 reg = <0xac000 0x1000>;
1049 fsl,qman-channel-id = <0x45>;
1050 };
1051
1052 fman0_oh0: port@81000 {
1053 cell-index = <0>;
1054 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1055 reg = <0x81000 0x1000>;
1056 fsl,qman-channel-id = <0x46>;
1057 };
1058 fman0_oh1: port@82000 {
1059 cell-index = <1>;
1060 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1061 reg = <0x82000 0x1000>;
1062 fsl,qman-channel-id = <0x47>;
1063 };
1064 fman0_oh2: port@83000 {
1065 cell-index = <2>;
1066 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1067 reg = <0x83000 0x1000>;
1068 fsl,qman-channel-id = <0x48>;
1069 };
1070 fman0_oh3: port@84000 {
1071 cell-index = <3>;
1072 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1073 reg = <0x84000 0x1000>;
1074 fsl,qman-channel-id = <0x49>;
1075 };
1076 fman0_oh4: port@85000 {
1077 cell-index = <4>;
1078 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1079 reg = <0x85000 0x1000>;
1080 fsl,qman-channel-id = <0x4a>;
1081 };
1082 fman0_oh5: port@86000 {
1083 cell-index = <5>;
1084 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1085 reg = <0x86000 0x1000>;
1086 fsl,qman-channel-id = <0x4b>;
1087 };
1088 fman0_oh6: port@87000 {
1089 cell-index = <6>;
1090 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
1091 reg = <0x87000 0x1000>;
1092 };
1093
1094 enet0: ethernet@e0000 {
1095 cell-index = <0>;
1096 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec";
1097 reg = <0xe0000 0x1000>;
1098 fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
1099 };
1100
1101 mdio0: mdio@e1120 {
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 compatible = "fsl,fman-mdio";
1105 reg = <0xe1120 0xee0>;
1106 interrupts = <100 1 0 0>;
1107 };
1108
1109 enet1: ethernet@e2000 {
1110 cell-index = <1>;
1111 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec";
1112 reg = <0xe2000 0x1000>;
1113 fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
1114 };
1115
1116 mdio@e3120 {
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 compatible = "fsl,fman-tbi";
1120 reg = <0xe3120 0xee0>;
1121 interrupts = <100 1 0 0>;
1122 };
1123
1124 enet2: ethernet@e4000 {
1125 cell-index = <2>;
1126 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec";
1127 reg = <0xe4000 0x1000>;
1128 fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
1129 };
1130
1131 mdio@e5120 {
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1134 compatible = "fsl,fman-tbi";
1135 reg = <0xe5120 0xee0>;
1136 interrupts = <100 1 0 0>;
1137 };
1138
1139 enet3: ethernet@e6000 {
1140 cell-index = <3>;
1141 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec";
1142 reg = <0xe6000 0x1000>;
1143 fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
1144 };
1145
1146 mdio@e7120 {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 compatible = "fsl,fman-tbi";
1150 reg = <0xe7120 0xee0>;
1151 interrupts = <100 1 0 0>;
1152 };
1153
1154 enet4: ethernet@e8000 {
1155 cell-index = <4>;
1156 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec";
1157 reg = <0xe8000 0x1000>;
1158 fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
1159 };
1160
1161 mdio@e9120 {
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164 compatible = "fsl,fman-tbi";
1165 reg = <0xe9120 0xee0>;
1166 interrupts = <100 1 0 0>;
1167 };
1168
1169 enet5: ethernet@f0000 {
1170 cell-index = <0>;
1171 compatible = "fsl,p2041-fman-10g-mac", "fsl,fman-10g-mac", "fsl,fman-xgec";
1172 reg = <0xf0000 0x1000>;
1173 fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
1174 };
1175
1176 mdio@f1000 {
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1179 compatible = "fsl,fman-xmdio";
1180 reg = <0xf1000 0x1000>;
1181 interrupts = <100 1 0 0>;
1182 };
1183 };
1184 };
1185
1186 rapidio@ffe0c0000 {
1187 compatible = "fsl,srio";
1188 interrupts = <16 2 1 11>;
1189 #address-cells = <2>;
1190 #size-cells = <2>;
1191 ranges;
1192
1193 port1 {
1194 #address-cells = <2>;
1195 #size-cells = <2>;
1196 cell-index = <1>;
1197 };
1198
1199 port2 {
1200 #address-cells = <2>;
1201 #size-cells = <2>;
1202 cell-index = <2>;
1203 };
1204 };
1205
1206 localbus@ffe124000 {
1207 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
1208 interrupts = <25 2 0 0>;
1209 #address-cells = <2>;
1210 #size-cells = <1>;
1211 };
1212
1213 pci0: pcie@ffe200000 {
1214 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
1215 device_type = "pci";
1216 status = "disabled";
1217 #size-cells = <2>;
1218 #address-cells = <3>;
1219 bus-range = <0x0 0xff>;
1220 clock-frequency = <33333333>;
1221 fsl,msi = <&msi0>;
1222 interrupts = <16 2 1 15>;
1223 pcie@0 {
1224 reg = <0 0 0 0 0>;
1225 #interrupt-cells = <1>;
1226 #size-cells = <2>;
1227 #address-cells = <3>;
1228 device_type = "pci";
1229 interrupts = <16 2 1 15>;
1230 interrupt-map-mask = <0xf800 0 0 7>;
1231 interrupt-map = <
1232 /* IDSEL 0x0 */
1233 0000 0 0 1 &mpic 40 1 0 0
1234 0000 0 0 2 &mpic 1 1 0 0
1235 0000 0 0 3 &mpic 2 1 0 0
1236 0000 0 0 4 &mpic 3 1 0 0
1237 >;
1238 };
1239 };
1240
1241 pci1: pcie@ffe201000 {
1242 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
1243 device_type = "pci";
1244 status = "okay";
1245 #size-cells = <2>;
1246 #address-cells = <3>;
1247 bus-range = <0 0xff>;
1248 clock-frequency = <33333333>;
1249 fsl,msi = <&msi1>;
1250 interrupts = <16 2 1 14>;
1251 pcie@0 {
1252 reg = <0 0 0 0 0>;
1253 #interrupt-cells = <1>;
1254 #size-cells = <2>;
1255 #address-cells = <3>;
1256 device_type = "pci";
1257 interrupts = <16 2 1 14>;
1258 interrupt-map-mask = <0xf800 0 0 7>;
1259 interrupt-map = <
1260 /* IDSEL 0x0 */
1261 0000 0 0 1 &mpic 41 1 0 0
1262 0000 0 0 2 &mpic 5 1 0 0
1263 0000 0 0 3 &mpic 6 1 0 0
1264 0000 0 0 4 &mpic 7 1 0 0
1265 >;
1266 };
1267 };
1268
1269 pci2: pcie@ffe202000 {
1270 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
1271 device_type = "pci";
1272 status = "disabled";
1273 #size-cells = <2>;
1274 #address-cells = <3>;
1275 bus-range = <0x0 0xff>;
1276 clock-frequency = <33333333>;
1277 fsl,msi = <&msi2>;
1278 interrupts = <16 2 1 13>;
1279 pcie@0 {
1280 reg = <0 0 0 0 0>;
1281 #interrupt-cells = <1>;
1282 #size-cells = <2>;
1283 #address-cells = <3>;
1284 device_type = "pci";
1285 interrupts = <16 2 1 13>;
1286 interrupt-map-mask = <0xf800 0 0 7>;
1287 interrupt-map = <
1288 /* IDSEL 0x0 */
1289 0000 0 0 1 &mpic 42 1 0 0
1290 0000 0 0 2 &mpic 9 1 0 0
1291 0000 0 0 3 &mpic 10 1 0 0
1292 0000 0 0 4 &mpic 11 1 0 0
1293 >;
1294 };
1295 };
1296 };
Cache object: 26d808a70aeaf10f30d9f32e474e4202
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