1 /*
2 * P3041DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 /* $FreeBSD$ */
35
36 /include/ "p3041si.dtsi"
37
38 / {
39 model = "fsl,P3041DS";
40 compatible = "fsl,P3041DS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 phy_rgmii_0 = &phy_rgmii_0;
47 phy_rgmii_1 = &phy_rgmii_1;
48 phy_sgmii_1c = &phy_sgmii_1c;
49 phy_sgmii_1d = &phy_sgmii_1d;
50 phy_sgmii_1e = &phy_sgmii_1e;
51 phy_sgmii_1f = &phy_sgmii_1f;
52 phy_xgmii_1 = &phy_xgmii_1;
53 phy_xgmii_2 = &phy_xgmii_2;
54 emi1_rgmii = &hydra_mdio_rgmii;
55 emi1_sgmii = &hydra_mdio_sgmii;
56 emi2_xgmii = &hydra_mdio_xgmii;
57 };
58
59 memory {
60 device_type = "memory";
61 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
62 };
63
64 dcsr: dcsr@f00000000 {
65 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
66 };
67
68 bman-portals@ff4000000 {
69 bman-portal@0 {
70 cpu-handle = <&cpu0>;
71 };
72 bman-portal@4000 {
73 cpu-handle = <&cpu1>;
74 };
75 bman-portal@8000 {
76 cpu-handle = <&cpu2>;
77 };
78 bman-portal@c000 {
79 cpu-handle = <&cpu3>;
80 };
81 bman-portal@10000 {
82 };
83 bman-portal@14000 {
84 };
85 bman-portal@18000 {
86 };
87 bman-portal@1c000 {
88 };
89 bman-portal@20000 {
90 };
91 bman-portal@24000 {
92 };
93
94 buffer-pool@0 {
95 compatible = "fsl,p3041-bpool", "fsl,bpool";
96 fsl,bpid = <0>;
97 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
98 };
99 };
100
101 qman-portals@ff4200000 {
102 qportal0: qman-portal@0 {
103 cpu-handle = <&cpu0>;
104 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
105 &qpool4 &qpool5 &qpool6
106 &qpool7 &qpool8 &qpool9
107 &qpool10 &qpool11 &qpool12
108 &qpool13 &qpool14 &qpool15>;
109 };
110
111 qportal1: qman-portal@4000 {
112 cpu-handle = <&cpu1>;
113 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
114 &qpool4 &qpool5 &qpool6
115 &qpool7 &qpool8 &qpool9
116 &qpool10 &qpool11 &qpool12
117 &qpool13 &qpool14 &qpool15>;
118 };
119
120 qportal2: qman-portal@8000 {
121 cpu-handle = <&cpu2>;
122 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
123 &qpool4 &qpool5 &qpool6
124 &qpool7 &qpool8 &qpool9
125 &qpool10 &qpool11 &qpool12
126 &qpool13 &qpool14 &qpool15>;
127 };
128
129 qportal3: qman-portal@c000 {
130 cpu-handle = <&cpu3>;
131 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
132 &qpool4 &qpool5 &qpool6
133 &qpool7 &qpool8 &qpool9
134 &qpool10 &qpool11 &qpool12
135 &qpool13 &qpool14 &qpool15>;
136 };
137
138 qportal4: qman-portal@10000 {
139 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
140 &qpool4 &qpool5 &qpool6
141 &qpool7 &qpool8 &qpool9
142 &qpool10 &qpool11 &qpool12
143 &qpool13 &qpool14 &qpool15>;
144 };
145
146 qportal5: qman-portal@14000 {
147 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
148 &qpool4 &qpool5 &qpool6
149 &qpool7 &qpool8 &qpool9
150 &qpool10 &qpool11 &qpool12
151 &qpool13 &qpool14 &qpool15>;
152 };
153
154 qportal6: qman-portal@18000 {
155 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
156 &qpool4 &qpool5 &qpool6
157 &qpool7 &qpool8 &qpool9
158 &qpool10 &qpool11 &qpool12
159 &qpool13 &qpool14 &qpool15>;
160 };
161
162 qportal7: qman-portal@1c000 {
163 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
164 &qpool4 &qpool5 &qpool6
165 &qpool7 &qpool8 &qpool9
166 &qpool10 &qpool11 &qpool12
167 &qpool13 &qpool14 &qpool15>;
168 };
169
170 qportal8: qman-portal@20000 {
171 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
172 &qpool4 &qpool5 &qpool6
173 &qpool7 &qpool8 &qpool9
174 &qpool10 &qpool11 &qpool12
175 &qpool13 &qpool14 &qpool15>;
176 };
177
178 qportal9: qman-portal@24000 {
179 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
180 &qpool4 &qpool5 &qpool6
181 &qpool7 &qpool8 &qpool9
182 &qpool10 &qpool11 &qpool12
183 &qpool13 &qpool14 &qpool15>;
184 };
185 };
186
187 soc: soc@ffe000000 {
188 spi@110000 {
189 flash@0 {
190 #address-cells = <1>;
191 #size-cells = <1>;
192 compatible = "spansion,s25sl12801";
193 reg = <0>;
194 spi-max-frequency = <35000000>; /* input clock */
195 partition@u-boot {
196 label = "u-boot";
197 reg = <0x00000000 0x00100000>;
198 read-only;
199 };
200 partition@kernel {
201 label = "kernel";
202 reg = <0x00100000 0x00500000>;
203 read-only;
204 };
205 partition@dtb {
206 label = "dtb";
207 reg = <0x00600000 0x00100000>;
208 read-only;
209 };
210 partition@fs {
211 label = "file system";
212 reg = <0x00700000 0x00900000>;
213 };
214 };
215 };
216
217 i2c@118100 {
218 eeprom@51 {
219 compatible = "at24,24c256";
220 reg = <0x51>;
221 };
222 eeprom@52 {
223 compatible = "at24,24c256";
224 reg = <0x52>;
225 };
226 };
227
228 i2c@119100 {
229 rtc@68 {
230 compatible = "dallas,ds3232";
231 reg = <0x68>;
232 interrupts = <0x1 0x1 0 0>;
233 };
234 };
235
236 pme: pme@316000 {
237 /* Commented out, use default allocation */
238 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
239 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
240 };
241
242 qman: qman@318000 {
243 /* Commented out, use default allocation */
244 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
245 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
246 };
247
248 bman: bman@31a000 {
249 /* Same as fsl,qman-*, use default allocation */
250 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
251 };
252
253 fman0: fman@400000 {
254 enet0: ethernet@e0000 {
255 tbi-handle = <&tbi0>;
256 phy-handle = <&phy_rgmii_0>;
257 phy-connection-type = "rgmii";
258 };
259
260 mdio0: mdio@e1120 {
261 tbi0: tbi-phy@8 {
262 reg = <0x8>;
263 device_type = "tbi-phy";
264 };
265
266 /*
267 * Virtual MDIO for the two on-board RGMII
268 * ports. The fsl,hydra-mdio-muxval property
269 * is already correct.
270 */
271 hydra_mdio_rgmii: hydra-mdio-rgmii {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "fsl,hydra-mdio";
275 fsl,mdio-handle = <&mdio0>;
276 fsl,hydra-mdio-muxval = <0x00>;
277 status = "disabled";
278
279 phy_rgmii_0: ethernet-phy@0 {
280 reg = <0x0>;
281 };
282 phy_rgmii_1: ethernet-phy@1 {
283 reg = <0x1>;
284 };
285 };
286
287 /*
288 * Virtual MDIO for the four-port SGMII card.
289 * The fsl,hydra-mdio-muxval property will be
290 * fixed-up by U-Boot based on the slot that
291 * the SGMII card is in.
292 *
293 * Note: we do not support DTSEC5 connected to
294 * SGMII, so this is the only SGMII node.
295 */
296 hydra_mdio_sgmii: hydra-mdio-sgmii {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "fsl,hydra-mdio";
300 fsl,mdio-handle = <&mdio0>;
301 fsl,hydra-mdio-muxval = <0x00>;
302 status = "disabled";
303
304 phy_sgmii_1c: ethernet-phy@1c {
305 reg = <0x1c>;
306 };
307 phy_sgmii_1d: ethernet-phy@1d {
308 reg = <0x1d>;
309 };
310 phy_sgmii_1e: ethernet-phy@1e {
311 reg = <0x1e>;
312 };
313 phy_sgmii_1f: ethernet-phy@1f {
314 reg = <0x1f>;
315 };
316 };
317 };
318
319 enet1: ethernet@e2000 {
320 tbi-handle = <&tbi1>;
321 phy-handle = <&phy_sgmii_1d>;
322 phy-connection-type = "sgmii";
323 };
324
325 mdio@e3120 {
326 tbi1: tbi-phy@8 {
327 reg = <8>;
328 device_type = "tbi-phy";
329 };
330 };
331
332 enet2: ethernet@e4000 {
333 tbi-handle = <&tbi2>;
334 phy-handle = <&phy_sgmii_1e>;
335 phy-connection-type = "sgmii";
336 };
337
338 mdio@e5120 {
339 tbi2: tbi-phy@8 {
340 reg = <8>;
341 device_type = "tbi-phy";
342 };
343 };
344
345 enet3: ethernet@e6000 {
346 tbi-handle = <&tbi3>;
347 phy-handle = <&phy_sgmii_1f>;
348 phy-connection-type = "sgmii";
349 };
350
351 mdio@e7120 {
352 #address-cells = <1>;
353 #size-cells = <0>;
354 compatible = "fsl,fman-tbi";
355 reg = <0xe7120 0xee0>;
356 interrupts = <100 1 0 0>;
357
358 tbi3: tbi-phy@8 {
359 reg = <8>;
360 device_type = "tbi-phy";
361 };
362 };
363
364 enet4: ethernet@e8000 {
365 tbi-handle = <&tbi4>;
366 phy-handle = <&phy_rgmii_1>;
367 phy-connection-type = "rgmii";
368 };
369
370 mdio@e9120 {
371 tbi4: tbi-phy@8 {
372 reg = <8>;
373 device_type = "tbi-phy";
374 };
375 };
376
377 enet5: ethernet@f0000 {
378 /*
379 * phy-handle will be updated by U-Boot to
380 * reflect the actual slot the XAUI card is in.
381 */
382 phy-handle = <&phy_xgmii_1>;
383 phy-connection-type = "xgmii";
384 };
385
386 /*
387 * We only support one XAUI card, so the MDIO muxing
388 * is set by U-Boot, and Linux never touches it.
389 * Therefore, we don't need a virtual MDIO node.
390 * However, the phy address depends on the slot, so
391 * only one of the ethernet-phy nodes below will be
392 * used.
393 */
394 hydra_mdio_xgmii: mdio@f1000 {
395 status = "disabled";
396
397 /* XAUI card in slot 1 */
398 phy_xgmii_1: ethernet-phy@4 {
399 reg = <0x4>;
400 };
401
402 /* XAUI card in slot 2 */
403 phy_xgmii_2: ethernet-phy@0 {
404 reg = <0x0>;
405 };
406 };
407 };
408 };
409
410 rapidio@ffe0c0000 {
411 reg = <0xf 0xfe0c0000 0 0x11000>;
412
413 port1 {
414 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
415 };
416 port2 {
417 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
418 };
419 };
420
421 localbus@ffe124000 {
422 reg = <0xf 0xfe124000 0 0x1000>;
423 ranges = <0 0 0xf 0xb8000000 0x04000000>;
424
425 flash@0,0 {
426 compatible = "cfi-flash";
427 /*
428 * Map 64Mb of 128MB NOR flash memory. Since highest
429 * line of address of NOR flash memory are set by
430 * FPGA, memory are divided into two pages equal to
431 * 64MB. One of the pages can be accessed at once.
432 */
433 reg = <0 0 0x04000000>;
434 bank-width = <2>;
435 device-width = <2>;
436 };
437
438 nand@2,0 {
439 #address-cells = <1>;
440 #size-cells = <1>;
441 compatible = "fsl,elbc-fcm-nand";
442 reg = <0x2 0x0 0x40000>;
443
444 partition@0 {
445 label = "NAND U-Boot Image";
446 reg = <0x0 0x02000000>;
447 read-only;
448 };
449
450 partition@2000000 {
451 label = "NAND Root File System";
452 reg = <0x02000000 0x10000000>;
453 };
454
455 partition@12000000 {
456 label = "NAND Compressed RFS Image";
457 reg = <0x12000000 0x08000000>;
458 };
459
460 partition@1a000000 {
461 label = "NAND Linux Kernel Image";
462 reg = <0x1a000000 0x04000000>;
463 };
464
465 partition@1e000000 {
466 label = "NAND DTB Image";
467 reg = <0x1e000000 0x01000000>;
468 };
469
470 partition@1f000000 {
471 label = "NAND Writable User area";
472 reg = <0x1f000000 0x21000000>;
473 };
474 };
475
476 board-control@3,0 {
477 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
478 reg = <3 0 0x30>;
479 };
480 };
481
482 pci0: pcie@ffe200000 {
483 reg = <0xf 0xfe200000 0 0x1000>;
484 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
485 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
486 pcie@0 {
487 ranges = <0x02000000 0 0x80000000
488 0x02000000 0 0x80000000
489 0 0x10000000
490
491 0x01000000 0 0x00000000
492 0x01000000 0 0xff000000
493 0 0x00010000>;
494 };
495 };
496
497 pci1: pcie@ffe201000 {
498 reg = <0xf 0xfe201000 0 0x1000>;
499 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
500 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
501 pcie@0 {
502 ranges = <0x02000000 0 0x90000000
503 0x02000000 0 0x90000000
504 0 0x10000000
505
506 0x01000000 0 0x00000000
507 0x01000000 0 0xff010000
508 0 0x00010000>;
509 };
510 };
511
512 pci2: pcie@ffe202000 {
513 reg = <0xf 0xfe202000 0 0x1000>;
514 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
515 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
516 pcie@0 {
517 ranges = <0x02000000 0 0xa0000000
518 0x02000000 0 0xa0000000
519 0 0x10000000
520
521 0x01000000 0 0x00000000
522 0x01000000 0 0xff020000
523 0 0x00010000>;
524 };
525 };
526
527 pci3: pcie@ffe203000 {
528 reg = <0xf 0xfe203000 0 0x1000>;
529 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
530 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
531 pcie@0 {
532 ranges = <0x02000000 0 0xb0000000
533 0x02000000 0 0xb0000000
534 0 0x08000000
535
536 0x01000000 0 0x00000000
537 0x01000000 0 0xff030000
538 0 0x00010000>;
539 };
540 };
541
542 chosen {
543 stdin = "serial0";
544 stdout = "serial0";
545 };
546 };
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